Programmable Logic Devices: PDF Created With Pdffactory Pro Trial Version

Programmable Logic Devices
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n PLDs
¡ Programmable Logic Devices (PLD)

n General purpose chip for implementing circuits
n Can be customized using programmable switches
¡ Main types of PLDs

n PLA
n PAL
n ROM
n CPLD
n FPGA
¡ Custom chips: standard cells, sea of gates

n PLD as a Black Box
Logic gates
Inputs and Outputs
(logic variables) programmable (logic functions)
switches

n Programmable Logic Array (PLA)
x1 x2 xn
¡ Use to implement
circuits in SOP form
Input buffers
¡ The connections in and
inverters
the AND plane are
programmable x1 x1 xn xn
P1
¡ The connections in
the OR plane are AND plane OR plane
programmable Pk
f1 fm

n Gate Level Version of PLA
x1 x2 x3
Programmable
connections
f1 = x1x2+x1x3'+x1'x2'x3 OR plane
P1
f2 = x1x2+x1'x2'x3+x1x3
P2
P3
P4
AND plane
f1 f2

n Customary Schematic of a PLA
x1 x2 x3
OR plane
f1 = x1x2+x1x3'+x1'x2'x3
P1
f2 = x1x2+x1'x2'x3+x1x3
P2
P3
P4
x marks the connections left in AND plane

place after programming
f1 f2

n Limitations of PLAs
¡ PLAs come in various sizes

n Typical size is 16 inputs, 32 product terms, 8 outputs
¡ Each AND gate has large fan-in à this limits the number of
inputs that can be provided in a PLA
¡ 16 inputs à 216 = possible input combinations; only 32

permitted (since 32 AND gates) in a typical PLA
¡ 32 AND terms permitted à large fan-in for OR gates as well

n This makes PLAs slower and slightly more expensive than
some alternatives to be discussed shortly
¡ 8 outputs à could have shared minterms, but not required

n Programmable Array Logic (PAL)
x1 x2 xn
¡ Also used to implement
circuits in SOP form
Input buffers
¡ The connections in and fixed connections
inverters
the AND plane are
programmable x1 x1 xn xn
P1
¡ The connections in
the OR plane are AND plane OR plane
NOT programmable Pk
f1 fm

n Example Schematic of a PAL
x1 x2 x3
f1 = x1x2x3'+x1'x2x3
f2 = x1'x2'+x1x2x3 P1
f1
P2
P3
f2
P4
AND plane

n Comparing PALs and PLAs
¡ PALs have the same limitations as PLAs (small

number of allowed AND terms) plus they have a
fixed OR plane à less flexibility than PLAs
¡ PALs are simpler to manufacture, cheaper, and

faster (better performance)
¡ PALs also often have extra circuitry connected to the

output of each OR gate
n The OR gate plus this circuitry is called a macrocell

n Macrocell
Select
Enable
OR gate from PAL 0
f1
1
D Q
Flip-flop
Clock
back to AND plane

n Macrocell Functions
¡ Enable = 0 can be used to allow the output pin for f1

to be used as an additional input pin to the PAL
¡ Enable = 1, Select = 0 is normal

for typical PAL operation Select
Enable
0
f1
1
¡ Enable = Select = 1 allows D Q

the PAL to synchronize the Clock
output changes with a clock
pulse back to AND plane
¡ The feedback to the AND plane provides for multi-

level design

n Multi-Level Design with PALs
¡ f = A'BC + A'B'C' + ABC' + AB'C = A'g + Ag'

n where g = BC + B'C' and C = h below
A B
Sel = 0
En = 0
0
1
h
D Q
Sel = 0
Clock En = 1
0
g
1
D Q
Select
Clock
0
f
1
D Q
Clock

n ROM
¡ A ROM (Read Only Memory) has a fixed AND plane

and a programmable OR plane
¡ Size of AND plane is 2n where n = number of input

pins
n Has an AND gate for every possible minterm so that all
input combinations access a different AND gate
¡ OR plane dictates function mapped by the ROM

n 4x4 ROM
¡ 22x4 bit ROM has 4 addresses that are decoded
2-to-4 decoder
a0
a1
d3 d2 d1 d0

n Programming SPLDs
¡ PLAs, PALs, and ROMs are also called SPLDs –

Simple Programmable Logic Devices
¡ SPLDs must be programmed so that the switches

are in the correct places
n CAD tools are usually used to do this
¡ A fuse map is created by the CAD tool and then that map is
downloaded to the device via a special programming unit
n There are two basic types of programming techniques

¡ Removable sockets on a PCB
¡ In system programming (ISP) on a PCB
n This approach is not very common for PLAs and PALs but
it is quite common for more complex PLDs

n An SPLD Programming Unit
¡ The SPLD is removed from the PCB, placed into the

unit and programmed there

n Removable SPLD Socket Package
¡ PLCC (plastic-leaded chip carrier)
PLCC socket soldered to

the PCB
d
boar
it
circu
d
r i nte
P

n In System Programming (ISP)
¡ Used when the SPLD cannot be removed from the

PCB
¡ A special cable and PCB connection are required to

program the SPLD from an attached computer
¡ Very common approach to programming more

complex PLDs like CPLDs, FPGAs, etc.

n CPLD
¡ Complex Programmable Logic Devices (CPLD)
¡ SPLDs (PLA, PAL) are limited in size due to the

small number of input and output pins and the limited
number of product terms
n Combined number of inputs + outputs < 32 or so
¡ CPLDs contain multiple circuit blocks on a single

chip
n Each block is like a PAL: PAL-like block
n Connections are provided between PAL-like blocks via an
interconnection network that is programmable
n Each block is connected to an I/O block as well

n Structure of a CPLD
I/O block
I/O block
PAL-like PAL-like
block block
Interconnection wires
I/O block
I/O block
PAL-like PAL-like
block block

n Internal Structure of a PAL-like Block
¡ Includes macrocells
n Usually about 16 each
PAL-like block
¡ Fixed OR planes
n OR gates have fan-in
between 5-20 PAL-like block
DQ
¡ XOR gates provide
negation ability DQ
n XOR has a control

DQ
input

n More on PAL-like Blocks
¡ CPLD pins are provided to control XOR, MUX, and

tri-state gates
¡ When tri-state gate is disabled, the corresponding

output pin can be used as an input pin
n The associated PAL-like block is then useless
¡ The AND plane and interconnection network are

programmable
¡ Commercial CPLDs have between 2-100 PAL-like

blocks

n Programming a CPLD
¡ CPLDs have many pins – large ones have > 200

n Removal of CPLD from a PCB is difficult without breaking
the pins
n Use ISP (in system programming) to program the CPLD
n JTAG (Joint Test Action Group) port used to connect the
CPLD to a computer

n Example CPLD
¡ Use a CPLD to implement the function

n f = x1x3x6' + x1x4x5x6' + x2x3x7 + x2x4x5x7
(from interconnection wires)

x1 x2 x3 x4 x5 x6 x7 unused
PAL-like block
0 1
0
f
D Q

n FPGA
¡ SPLDs and CPLDs are relatively small and useful for

simple logic devices
n Up to about 20000 gates
¡ Field Programmable Gate Arrays (FPGA) can handle

larger circuits
n No AND/OR planes
n Provide logic blocks, I/O blocks, and interconnection wires
and switches
n Logic blocks provide functionality

n Interconnection switches allow logic blocks to be connected
to each other and to the I/O pins

n Structure of an FPGA
I/O block
interconnection
switch
I/O block
I/O block
logic block
I/O block

n LUTs
¡ Logic blocks are implemented using a lookup table

(LUT)
n Small number of inputs, one output
n Contains storage cells that can be loaded with the desired
values
n A 2 input LUT uses 3 MUXes

to implement any desired function x1
of 2 variables 0/1
¡ Shannon's expansion at work!
0/1
f
0/1
0/1
x2

n Example 2 Input LUT
x1 x2 f
0 0 1 f = x1'x2' + x1x2, or using Shannon's expansion:
0 1 0
1 0 0
1 1 1
x1
1
0
f
0
1
x2

n 3 Input LUT
¡ 7 2x1 MUXes and x1

8 storage cells are x2
required 0/1
0/1
¡ Commercial LUTs have 0/1
4-5 inputs, and 16-32
0/1
storage cells f
0/1
0/1
0/1
0/1
x3

n Programming an FPGA
¡ ISP method is used
¡ LUTs contain volatile storage cells

n None of the other PLD technologies are volatile
n FPGA storage cells are loaded via a PROM when power is
first applied
¡ The UP2 Education Board by Altera contains a

JTAG port, a MAX 7000 CPLD, and a FLEX 10K
FPGA
n The MAX 7000 CPLD chip is EPM7128SLC84-7
n EPM7 à MAX 7000 family; 128 macrocells; LC84 à 84 pin
PLCC package; 7 à speed grade

n Example FPGA
¡ Use an FPGA with 2 input LUTS to implement the

function f = x1x2 + x2'x3
x3 f
n f1 = x1x2
n f2 = x2'x3 x1
n f = f1 + f2 x1 0 x2 0
0 f1 1 f2
0 0
x2 x2 x3
1 0
f1 0
1 f
1
f2
1

n Another Example FPGA
¡ Use an FPGA with 2 input LUTS to implement the

function f = x1x3x6' + x1x4x5x6' + x2x3x7 + x2x4x5x7
n Fan-in of expression is too large for FPGA (this was simple

to do in a CPLD)
n Factor f to get sub-expressions with max fan-in = 2

¡ f = x1x6'(x3 + x4x5) + x2x7(x3 + x4x5)
= (x1x6' + x2x7)(x3 + x4x5)
n Could use Shannon's expansion instead

¡ Goal is to build expressions out of 2-input LUTs

n FPGA Implementation
¡ f = (x1x6' + x2x7)(x3 + x4x5)

x4 x5 x3 f
x1
x1 0 x4 0 x3 0
0 A 0 C 1 E
x6 x6 1 x5 0 C 1
1
0 1
x2
x2 0 A 0 D 0
0 B 1 D 0 f
x7 x7 0 1
B 1
0
E 1
1

n Custom Chips
¡ PLDs are limited by number of programmable

switches
n Consume space
n Reduce speed
¡ Custom chips are created from scratch

n Expensive à used when high speed is required, volume
sales are expected, and chip size is small but with high
density of gates
n ASICs (Application Specific Integrated Circuits) are custom
chips that use a standard cell layout to reduce design costs

n Standard Cells
¡ Rows of logic gates can be connected by wires in

the routing channels
n Designers (via CAD tools) select prefab gates from a library
and place them in rows
n Interconnections are made by wires in routing channels
¡ Multiple layers may be used to avoid short circuiting
¡ A hard-wired connection between layers is called a via
x1 f2
x2
x3
f1

n Example: Standard Cells
¡ f1 = x1x2 + x1'x2'x3 + x1x3'

¡ f2 = x1x2 + x1'x2'x3 + x1x3
x1 f2
x2
x3
f1

n Sea of Gates Gate Array
¡ A Sea of Gates gate array is just like a standard cell

except all gates are of the same type
n Interconnections are run in channels and use multiple
layers
n Cheaper to manufacture due to regularity

n Example: Sea of Gates
¡ f1 = x2x3' + x1x3
black à bottom
layer channels
red à top layer channels

n Digital Logic Technology Tradeoffs
Full custom
VLSI design
ASICs
Speed / Density /
Complexity / Likely
Market Volume CPLDs
FPGAs
PLDs
Engineering cost / Time to develop

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Programmable Logic Devices

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¡ Programmable Logic Devices (PLD)

¡ Main types of PLDs

¡ Custom chips: standard cells, sea of gates

PDF created with pdfFactory Pro trial version www.pdffactory.com

PDF created with pdfFactory Pro trial version www.pdffactory.com

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x marks the connections left in AND plane

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¡ PLAs come in various sizes

¡ 16 inputs à 216 = possible input combinations; only 32

¡ 32 AND terms permitted à large fan-in for OR gates as well

¡ 8 outputs à could have shared minterms, but not required

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PDF created with pdfFactory Pro trial version www.pdffactory.com

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¡ PALs have the same limitations as PLAs (small

¡ PALs are simpler to manufacture, cheaper, and

¡ PALs also often have extra circuitry connected to the

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back to AND plane

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¡ Enable = 0 can be used to allow the output pin for f1

¡ Enable = 1, Select = 0 is normal

¡ Enable = Select = 1 allows D Q

¡ The feedback to the AND plane provides for multi-

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¡ f = A'BC + A'B'C' + ABC' + AB'C = A'g + Ag'

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¡ A ROM (Read Only Memory) has a fixed AND plane

¡ Size of AND plane is 2n where n = number of input

¡ OR plane dictates function mapped by the ROM

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¡ 22x4 bit ROM has 4 addresses that are decoded

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¡ PLAs, PALs, and ROMs are also called SPLDs –

¡ SPLDs must be programmed so that the switches

n There are two basic types of programming techniques

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¡ The SPLD is removed from the PCB, placed into the

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¡ PLCC (plastic-leaded chip carrier)

PLCC socket soldered to

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¡ Used when the SPLD cannot be removed from the

¡ A special cable and PCB connection are required to

¡ Very common approach to programming more

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¡ Complex Programmable Logic Devices (CPLD)

¡ SPLDs (PLA, PAL) are limited in size due to the

¡ CPLDs contain multiple circuit blocks on a single

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n XOR has a control

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¡ CPLD pins are provided to control XOR, MUX, and

¡ When tri-state gate is disabled, the corresponding

¡ The AND plane and interconnection network are

¡ Commercial CPLDs have between 2-100 PAL-like

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