VLSI IEEE Projects Titles – 2016-2017

LeMeniz Infotech
36, 100 feet Road, Natesan Nagar( Near Indira Gandhi Statue and Next to Fish-O-Fish),
Pondicherry-605 005

Web : www.ieeemaster.com / www.lemenizinfotech.com

Mail : info@lemenizinfotech.com / projects@lemenizinfotech.com

Phone : 9566355386 / 9962588976

S.No Title Year

IEEE based on Low Power

1 A Fully Digital Front-End Architecture for ECG Acquisition System with 2016
0.5v Supply

2 Low-Cost High Performance VLSI Architecture for Montgomery 2016

Modular Multiplication

3 RF Power Gating: A Low-Power Technique for Adaptive Radios 2016

4 A New Parallel VLSI Architecture for Real-Time Electrical Capacitance 2016

Tomography

5 Low-Power FPGA Design Using Memoization-Based Approximate 2016

Computing

6 Low-Power Split-Radix FFT Processors Using Radix-2 Butterfly Units 2016

7 A 3-D CPU-FPGA_DRAM Hybrid architecture for Low-Power 2016
Computation

8 Design of a Network of Digital Sensor Macros for Extracting Power 2016

Supply Noise Profile in SoCs

9 The Flexible ECC Management for Low-Cost Transient Error 2016

Protection of Last-Level Caches

High Speed Data Transmission

1 A High-Speed FPGA Implementation of an RSD-Based ECC Processor 2016

2 High-Speed and Energy-Efficient Carry Skip Adder Operating Under a 2016

Wide Range of Supply Voltage Levels

3 A 0.52/1 V Fast Lock-in ADPLL for Supporting Dynamic Voltage and 2016
Frequency Scaling

4 Code Compression for Embedded Systems Using Separated 2016

Dictionaries

5 A Dynamically Reconfigurable Multi-ASIP Architecture for Multi- 2016

standard and Multimode Turbo Decoding

6 Design and Implementation of High-Speed All-Pass Transformation- 2016

Based Variable Digital Filters by Breaking the Dependence of
Operating Frequency on Filter Order

7 Statistical Framework and Built-In Self Speed-Binning System for 2016

Speed Binning Using On-Chip Ring Oscillators
 2016
8 A Low-Power Broad-Bandwidth Noise Cancellation VLSI Circuit Design
for In-Ear Headphones

9 Source Coding and Preemphasis for Double-Edged Pulse width 2016

Modulation Serial Communication

10 A Fast-Acquisition All-Digital Delay-Locked Loop Using a Starting-Bit 2016

Prediction Algorithm for the Successive-Approximation Register

11 GPU-Accelerated Parallel Sparse LU Factorization Method for Fast 2016

Circuit Analysis

12 An All-Digital Approach to Supply Noise Cancellation in Digital Phase- 2016

Locked Loop

13 Design of Modified Second-Order Frequency Transformations Based 2016

Variable Digital Filters With Large Cutoff Frequency Range and
Improved Transition Band Characteristics

AREA EFFICIENT/ TIMING & DELAY REDUCTION

1 A Mixed-Decimation MDF Architecture for Radix-2K Parallel FFT 2016

2 Algorithm and Architecture of Configurable Joint Detection and 2016`

Decoding for MIMO Wireless Communications With Convolution
Codes

3 One-Cycle Correction of Timing Errors in Pipelines With Standard 2016

Clocked Elements
4 Hardware and Energy-Efficient Stochastic LU Decomposition Scheme 2016
for MIMO Receivers

5 Hybrid LUT/Multiplexer FPGA Logic Architectures 2016

6 Implementing Minimum-Energy-Point Systems With Adaptive Logic 2016

7 High-Performance Pipelined Architecture of Elliptic Curve Scalar 2016

Multiplication Over GF(2m)

8 LUT Optimization for Distributed Arithmetic-Based Block Least Mean 2016

Square Adaptive Filter

9 Graph-Based Transistor Network Generation Method for Supergate 2016

Design

10 Flexible DSP Accelerator Architecture Exploiting Carry-Save 2016

Arithmetic

11 A Cellular Network Architecture With Polynomial Weight Functions 2016

12 A High-Performance FIR Filter Architecture for Fixed and 2016

Reconfigurable Applications

13 Fault Tolerant Parallel FFTs Using Error Correction Codes and 2016
Parseval Checks

14 Unequal-Error-Protection Error Correction Codes for the Embedded 2016

Memories in Digital Signal Processors
15 A Normal I/O Order Radix-2 FFT Architecture to Process Twin Data 2016
Streams for MIMO

16 Low-Power/Cost RNS Comparison via Partitioning the Dynamic 2016

Range

17 Understanding the Relation Between the Performance and 2016

Reliability of NAND Flash/SCM Hybrid Solid-State Drive

18 Optimized Built-In Self-Repair for Multiple Memories 2016

19 Measuring Improvement When Using HUB Formats to Implement 2016

Floating-Point Systems Under Round-to-Nearest

20 A High-Throughput Hardware Design of a One-Dimensional SPIHT 2016

Algorithm

21 Enhanced Wear-Rate Leveling for PRAM Lifetime Improvement 2016

Considering Process Variation

22 Speculative Look ahead for Energy-Efficient Microprocessors 2016

23 Efficient Synchronization for Distributed Embedded Multiprocessors 2016

24 NAND Flash Memory With Multiple Page Sizes for High-Performance 2016
Storage Devices

25 A Performance Degradation Tolerable Cache Design by Exploiting 2016

Memory Hierarchies
26 A New Optimal Algorithm for Energy Saving in Embedded System 2016
With Multiple Sleep Modes

27 A Fast Fault-Tolerant Architecture for Sauvola Local Image 2016

Thresholding Algorithm Using Stochastic Computing

28 Efficiency Enablers of Lightweight SDR for MIMO Baseband 2016

Processing

29 A Novel Quantum-Dot Cellular Automata X-bit ×32-bit SRAM 2016

30 Ultralow-Energy Variation-Aware Design: Adder Architecture Study 2016

31 Write Buffer-Oriented Energy Reduction in the L1 Data Cache for 2016

Embedded Systems

32 Toward Solving Multichannel RF-SoC Integration Issues Through 2016

Digital Fractional Division

33 Error Resilient and Energy Efficient MRF Message-Passing-Based 2016

Stereo Matching

34 Floating-Point Butterfly Architecture Based on Binary Signed-Digit 2016

Representation

35 On Efficient Retiming of Fixed-Point Circuits 2016

36 Trigger-Centric Loop Mapping on CGRAs 2016

37 Area-Aware Cache Update Trackers for Post silicon Validation 2016

38 PEVA: A Page Endurance Variance Aware Strategy for the Lifetime 2016
Extension of NAND Flash

39 Memory-Aware Loop Mapping on Coarse-Grained Reconfigurable 2016

Architectures

40 An Efficient Single and Double-Adjacent Error Correcting Parallel 2016

Decoder for the (24,12) Extended Golay Code

41 Concept, Design, and Implementation of Reconfigurable CORDIC 2016

AUDIO, IMAGE & VIDEO PROCESSING

1 Input-Based Dynamic Reconfiguration of Approximate Arithmetic 2016

Units for Video Encoding

2 A Configurable Parallel Hardware Architecture for Efficient Integral 2016

Histogram Image Computing

2016
3 A New Binary-Halved Clustering Method and ERT Processor for ASSR
System

4 The VLSI Architecture of a Highly Efficient De-blocking Filter for HEVC 2016
Systems

VERIFICATION

1 Source Code Error Detection in High-Level Synthesis Functional 2016

 Verification

NETWORKING

1 In-Field Test for Permanent Faults in FIFO Buffers of NoC Routers 2016

2 FCUDA-NoC : A Scalable and Efficient Network-on-Chip 2016

Implementation for the CUDA-to-FPGA Flow

3 Process Variation Delay and Congestion Aware Routing Algorithm for 2016
Asynchronous NoC Design

4 Argo: A Real-Time Network-on-Chip Architecture With an Efficient 2016

GALS Implementation

5 Efficient Dynamic Virtual Channel Organization and Architecture for 2016

NoC Systems

6 A New CDMA Encoding/Decoding Method for on-Chip 2016

Communication Network

TANNER & MICROWIND/DSCH3

1 A Single-Ended With Dynamic Feedback Control 8T Subthreshold 2016

SRAM Cell

2 OTA-Based Logarithmic Circuit for Arbitrary Input Signal and Its 2016
Application

3 A Robust Energy/Area-Efficient Forwarded-Clock Receiver With All- 2016

 Digital Clock and Data Recovery in 28-nm CMOS for High-Density
Interconnects

4 Full-Swing Local Bitline SRAM Architecture Based on the 22-nm 2016

FinFET Technology for Low-Voltage Operation

5 A 0.1–3.5-GHz Duty-Cycle Measurement and Correction Technique in 2016

130-nm CMOS

6 A Systematic Design Methodology of Asynchronous SAR ADCs 2016

7 Read Bit line Sensing and Fast Local Write-Back Techniques in 2016
Hierarchical Bit line Architecture for Ultralow-Voltage SRAMs

8 Online Measurement of Degradation Due to Bias Temperature 2016

Instability in SRAMs

9 Incorporating Process Variations Into SRAM Electromigration 2016

Reliability Assessment Using Atomic Flux Divergence

10 PROCEED: A Pareto Optimization-Based Circuit-Level Evaluator for 2016

Emerging Devices

11 A Fast-Transient Wide-Voltage-Range Digital-Controlled Buck 2016

Converter With Cycle-Controlled DPWM

12 Designing Tunable Subthreshold Logic Circuits Using Adaptive 2016

Feedback Equalization

13 Dual-Calibration Technique for Improving Static Linearity of 2016

 Thermometer DACs for I/O

14 An Add-On Type Real-Time Jitter Tolerance Enhancer for Digital 2016

Communication Receivers

15 SRAM-Based Unique Chip Identifier Techniques 2016

16 A Low-Power Robust Easily Cascaded PentaMTJ-Based Combinational 2016

and Sequential Circuits

17 Low-Power Variation-Tolerant Nonvolatile Lookup Table Design 2016

18 Low-Energy Power-ON-Reset Circuit for Dual Supply SRAM 2016

19 Frequency-Boost Jitter Reduction for Voltage-Controlled Ring 2016

Oscillators

20 High-Speed, Low-Power, and Highly Reliable Frequency Multiplier for 2016

DLL-Based Clock Generator

21 EMDBAM: A Low-Power Dual Bit Associative Memory With Match 2016

Error and Mask Control

22 A Single-Stage Low-Dropout Regulator With a Wide Dynamic Range 2016

for Generic Applications

23 Power Efficient Level Shifter for 16 nm FinFET Near Threshold Circuits 2016