International Academy of Engineering and Medical Research, 2017

Volume-2, Issue-6
Published Online June 2017 in IAEMR (http://www.iaemr.com)

Design & Comparison of a 2*1 Multiplexer Using

Adiabatic Logics
G.N.V. Sai Sushanth, B.N.S. Bhanusingh, S. Sai Murthy, A.D. Sai Teja,

Mrs. T. Venkata Lakshmi Dr. M. Kamaraju

Department of ECE Department of ECE
Associate Professor Professor & HOD

Department of Electronics and Communication Engineering, Gudlavalleru Engineering

College, Gudlavalleru, Andhra Pradesh.
Abstract— Minimization of Power Consumption is one of the systems and several adiabatic logic families have been
primary concerns in today’s technology. Dynamic logics have proposed for low power logic applications. The energy
many advantages over old static logics but it also have some dissipated in adiabatic circuits is considerably lesser than that
drawbacks which are very important. The main drawback of in the static CMOS circuits; hence adiabatic circuits are
dynamic logic is the Power Dissipation. To overcome that
desired for low power circuits that can be operated in the
drawback a new technique is used to reduce the Power
Consumption in VLSI Design. Basically these Multiplexers are frequency range in which signals are digitally processed.
much used in today Digital circuits in Communication System,
Networks and Transmission of Data through a single channel. A E = RCL /T *CLVdd^
technique named 2PASCL (2 Phase clocked Adiabatic Static
CMOS Logic) utilizes the principles of Adiabatic Switching and
Energy Recovery. The low power 2PASCL circuit uses two II. OPERATION OF ADIABATIC LOGIC
complementary split-level sinusoidal power supply clocks whose The term ADIABATIC is originated from Greek word that is
height is equal to Vdd. This technique has switching activity that
used to describe the thermodynamic process in which no
is lower than that of dynamic logic. By using this technique the
Power Dissipation can be reduced to a maximum extent of about
exchange of energy occurs between the system and the
98% than any other logics. external environment. But in practical computing such ideal
condition cannot be achieved due to the presence of
Keywords— Static CMOS, Adiabatic Logic, Energy dissipative elements like resistances. However one can
Dissipation, 2PASCL, Adiabatic Switching, Energy achieve very low power dissipation by reducing the speed of
Recovery. operation and only switching transistors under certain
conditions. The adiabatic logic is also known as Energy
Recovery CMOS. In literature, there are two types of adiabatic
I. INTRODUCTION circuits presented. One is full adiabatic and other is quasi-
adiabatic or partial adiabatic circuits. In most practical cases
Low power dissipation is the basic criteria in any electronic two type of dissipation occurs in adiabatic circuit adiabatic
gadgets. This chapter introduces the need of low power loss and non-adiabatic loss. Adiabatic loss occurs by switching
design. Power consumption is one of the basic parameter of resistances of transistor when a flow through the transistor and
any kind of integrated circuit (IC). Power and performance are
always traded off to meet the system requirements. Power has
a direct impact on the system cost. If an IC is consuming more
power, then a better cooling mechanism would be required to
keep the circuit in normal conditions. Otherwise, its
performance is degraded and on continuous use of it may be
permanently damaged. The Explosive growth in laptop,
portable systems, and cellular network has intensified the
research efforts in low power microelectronics. In recent
years,adiabatic computing has been applied to low power

Figure 1: Adiabatic Logic Circuit

 International Academy of Engineering and Medical Research, 2017
Volume-2, Issue-6
Published Online June 2017 in IAEMR (http://www.iaemr.com)
the non- adiabatic Here the load capacitance is charged by the
constant current source while in conventional CMOS constant
voltage source is used. Here R is the resistance PMOS
network. A constant charging current corresponds to a linear
voltage ramp. Assume the capacitor voltage is initially zero.
E = (I2R) T = (RCL /T) *CLVdd2
Where
E is the energy dissipated during charging time,
Q is the charge transferred to the load,
C is the value of the load capacitance,
R is the on-resistance of the PMOS switch,
V is the final value of the voltage at the load,
T is the charging time.
Theoretically the energy dissipation is nearly zero when the
switching time of the driving voltage is long. When goes from
HIGH to LOW discharging process takes place through the
NMOS. The energy dissipation can be minimized by
increasing the switching time. The energy dissipation is
proportional to R. Thus by decreasing the on-resistance of
PMOS network will decrease the energy dissipation.
III. MULTIPLEXER
In electronics, a multiplexer is a device that selects one signal CMOS in power dissipation.
for transmission out of several analog or digital input signals
and forwards the selected input into a single line. A
multiplexer of 2n inputs has n select lines, which are used to
select which input line to send to the output. Multiplexers are
mainly used to increase the amount of data that can be sent
over the network within a certain amount of time and
bandwidth. A multiplexer is also called a data selector as it
selects a signal from many signals. Multiplexers can also be
used to implement Boolean functions of multiple variables.
Fig.2 Multiplexer Symbol
An electronic multiplexer makes it possible for several signals
to share one device or resource, for example one A/D
converter or one communication line, instead of having one
device per input signal.An electronic multiplexer can be
considered as a multiple-input, single-output switch. The
schematic symbol for a multiplexer is an isosceles trapezoid
with the longer parallel side containing the input pins and the
short parallel side containing the output pin. The image to the
right demonstrates this benefit. In this case, the cost of
implementing separate channels for each data source is higher
than the cost and inconvenience of providing the
multiplexing/de-multiplexing functions.
IV. ADIABATIC LOGIC FAMILIES
The adiabatic logic family can be divided in partial adiabatic
and full adiabatic. Some charge is transferred to the ground in
partial adiabatic circuit while in full adiabatic circuits all the
charges are recovered. Adiabatic logic family consist of many
design techniques like Efficient Charge Recovery Logic
(ECRL), Positive Feedback Adiabatic Logic (PFAL), Diode
Free Adiabatic Logic (DFAL) and Two phase adiabatic static
clocked logic (2PASCL).But in this paper we are going
through ECRL,PFAL, DFAL and 2PASCL. By using these
techniques multiplexer circuit has been designed. These
designs show good improvement as compared to conventional
A. DESIGN OF MULTIPLEXER USING ECRL
ECRL has two cross coupled PMOS and two NMOS tree
structure. An AC power supply is used to recover the charge
& reuse the supplied energy. Both Out and is generated so that
power clock generator always drive a constant load
capacitance independent of the input signal. The logic function
which is to be implemented is realized using NMOS
transistors, in both true and complementary forms. In above
figure, let us assume in is high & in bar is at low. When power
supply ramps up from 0 to VDD, ‘out’ remains at a ground
level & out bar follows power clock (φ) through P2.When
power clock reaches VDD, out & out bar holds the valid logic
levels & these values are maintained during the hold phase
and are used for the evaluation of the next stage. As φ ramps
down from Vdd to ground, out bar returns its energy to power
clock i.e. delivered charge is recovered back to the power
supply. The logic density of ECRL is more as compared to
conventional CMOS that is achieved by elimination of PMOS
transistors from each logic function. All functions are
implemented using NMOS only, and PMOS transistors serve
only as the pull-up devices. In ECRL circuits, the latch is
realized using 2 cross-coupled PMOS transistors & the
cascade complementary logic array is realized with a NMOS
logic tree.
 International Academy of Engineering and Medical Research, 2017
Volume-2, Issue-6
Published Online June 2017 in IAEMR (http://www.iaemr.com)
swings down and in the hold phase,VPC swings down and
PCBAR swings up. In evaluation phase, PMOS tree is turned
ON & load capacitance gets charged through PMOS transistor
resulting in the High state at the output. When NMOS tree
turns ON then value at the output node gets discharged
through NMOS transistor. In hold phase, NMOS tree is ON &
output is Low then no transitions occur at the output. During
the hold phase, dynamic switching is reduced and thus energy
dissipation is also reduced.

Fig.3 Multiplexer using ECRL

B. DESIGN OF MULTIPLEXER USING PFAL

PFAL consists of two cross-coupled inverters as latch known
as sense amplifier, which drives the two complementary
outputs of the circuit & the logic function NF, and its
compliment are realized using NMOS networks which is
connected parallel to PMOS. One of the logic blocks connects
the concerned input to the power clock with a low resistance
path and on the same time the other network provides a very
high resistance in between the power clock and the other Fig.4 Multiplexer using PFAL
output. But the inverter’s down network provides the second
output a conducting path to the ground. In this way one of the Using DFAL 2:1 Mux, we can achieve low power dissipation
two outputs (either complementary or un-complementary one) as compared to CMOS logic design circuit.
is pulled up to the power clock and other down to the ground.
PFAL uses four phase clocking technique to recover the
charge delivered by the power supply. The two cross-coupled
inverter drives the two complementary outputs of the circuit.
The logic function F = ASbar + BS is realized using NMOS
network which is connected parallel to PMOS transistor &
results in the reduction of equivalent resistance of the logic
network thereby reducing the power dissipation.

C. DESIGN OF MULTIPLEXER USING DFAL

In this logic, no diode is used in the charging or discharging
path. DFAL uses a two phase clocked split-level sinusoidal
power clock supply PC and to minimize the voltage difference
between the current-carrying electrodes and consequently
reduce the power consumption. Split level clock
charges/discharges the load capacitance comparatively slowly
than the other adiabatic power clocks. Since the efficiency of
adiabatic logic circuits depends upon slowly the load
capacitance is charged or discharged so power dissipation is
reduced further. Circuit operation is divided into two stages,
evaluation and hold depending on the supply clock signal Fig.5 Multiplexer using DFAL
phases. In evaluation phase, VPC swings up while PCBAR
 International Academy of Engineering and Medical Research, 2017
Volume-2, Issue-6
Published Online June 2017 in IAEMR (http://www.iaemr.com)

When select line is high then DFAL inverter output becomes

low and select line directly gets connected to NMOS, as a
result of this PMOS and NMOS transistor gets ON and In2
input comes to output. When select line is low, then DFAL
inverter output becomes high and select line directly connects
PMOS, so both PMOS and NMOS transistor turns on and
input In1 will appear at the output.

D. DESIGN OF MULTIPLEXER USING 2PASCL

2PASCL is termed to be 2 Phase Clocked Adiabatic Static
CMOS Logic, in this logic sinusoidal is used as the supply
voltage for the circuit. In this Circuit some of the power Fig.7 Output Waveform of Static CMOS
consumption is stored as the hold state and the remaining
energy is used for the work to be done. In the other half the
clock cycle the energy stored in the state is recovered back to
the Circuit for the re-use in the next clock cycle. Here there
are two clocks which are opposite in phase. In-phase clock is
placed in between basic cmos circuit and the output, whereas
the clock Out-phase to the above clock in between two basic
cmos circuit and the ground. This is taken in order to reduce
the high fluctuations in the output of the circuit. So, these
clocks counter each other to have a accurate output.

Fig.8 Output Waveform of DFAL

Fig.9 Output Waveform of PFAL

Fig.6 Multiplexer using 2PASCL

V. RESULTS
The below are the output waveforms of the various Adiabatic
logics

Fig.10 Output Waveform of ECRL

 International Academy of Engineering and Medical Research, 2017
Volume-2, Issue-6
Published Online June 2017 in IAEMR (http://www.iaemr.com)
VI. FUTURE WORK
From the study it was found that the adiabatic logic circuits
can play a significant role in designing applications where
power conservation is one of prime importance such as in high
performance, hand held and portable digital systems running
on batteries. The above circuit’s shows power reduction
compared to CMOS. In future, we will design circuits using
DFAL, ECRL, PFAL, and 2PASCL etc adiabatic logic so that
we can get minimum power dissipation.

VII. CONCLUSION
Multiplexer through various logic styles has been designed
and simulated using Mentor Graphics. These logic styles
Fig.11 Output Waveform of 2PASCL include Static CMOS, DFAL, PFAL, ECRL and 2PASCL
multiplexer designs. Among all these logic styles 2PASCL
Comparison between various Logics Power Dissipation : MUX is more power efficient. Further Static multiplexer is
compared with the proposed adiabatic multiplexer which is
designed using 2PASCL logic and it has been seen that
Technique Power Dissipation proposed MUX shows better performance in terms of power
consumption. It is recorded that 99% improvement is obtained
Static CMOS 1.0668mW in terms power consumption as compare to Static multiplexer.
All results are verified at different supply voltage. Proposed
Diode Free Adiabatic 182.10 µW Multiplexer shows good performance with supply voltage as
Logic compare to Static CMOS, DFAL, PFAL and ECRL
Positive Feedback 120.07µW multiplexer.
Adiabatic Logic
Efficient Charge 85.332µW
VIII. REFERENCE
Recovery Logic
2 Phase Clocked 16.997µW
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Fig.12 Power Dissipation of various Logics