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VNH2SP30 Datasheet
VNH2SP30 Datasheet
■ CROSS-CONDUCTION PROTECTION
The Low-Side switches are vertical MOSFETs
■ LINEAR CURRENT LIMITER manufactured using STMicroelectronic’s
■ VERY LOW STAND-BY POWER proprietary EHD (‘STripFET™’) process.The three
CONSUMPTION dice are assembled in MultiPowerSO-30 package
■ PWM OPERATION UP TO 20 KHz on electrically isolated leadframes. This package,
specifically designed for the harsh automotive
■ PROTECTION AGAINST:
environment offers improved thermal performance
LOSS OF GROUND AND LOSS OF VCC thanks to exposed die pads. Moreover, its fully
■ CURRENT SENSE OUTPUT PROPORTIONAL symmetrical mechanical design allows superior
TO MOTOR CURRENT manufacturability at board level. The input signals
IN A and IN B can directly interface to the
■ IN COMPLIANCE WITH THE 2002/95/EC
microcontroller to select the motor direction and
EUROPEAN DIRECTIVE the brake condition. The DIAG A/ENA or DIAGB/
EN B, when connected to an external pull-up
resistor, enable one leg of the bridge. They also
DESCRIPTION provide a feedback digital diagnostic signal. The
The VNH2SP30-E is a full bridge motor driver normal condition operation is explained in the truth
intended for a wide range of automotive table on page 14. The CS pin allows to monitor the
applications. The device incorporates a dual motor current by delivering a current proportional
monolithic High-Side drivers and two Low-Side to its value. The PWM, up to 20KHz, lets us to
switches. The High-Side driver switch is designed control the speed of the motor in all possible
using STMicroelectronic’s well known and proven conditions. In all cases, a low level state on the
proprietary VIPower™ M0 technology that allows PWM pin will turn off both the LSA and LSB
to efficiently integrate on the same die a true switches. When PWM rises to a high level, LSA or
Power MOSFET with an intelligent signal/ LSB turn on again depending on the input pin
protection circuitry. state.
Rev. 1
September 2004 1/26
VNH2SP30-E
VCC
OVERTEMPERATURE A OV + UV OVERTEMPERATURE B
CURRENT CURRENT
LIMITATION A LIMITATION B
DRIVER DRIVER
LSA LSB
LSA LSB
OUTA 1 30 OUTA
Nc Nc
OUTA
VCC GNDA
Heat Slug3
Nc GNDA
INA GNDA
ENA/DIAGA OUTA
Nc VCC Nc
PWM Heat Slug1 VCC
CS Nc
ENB/DIAGB OUTB
INB GNDB
Nc OUTB GNDB
Heat Slug2
VCC GNDB
Nc Nc
OUTB 15 16 OUTB
2/26
VNH2SP30-E
3/26
VNH2SP30-E
IS
VCC
IINA VCC
INA IOUTA
IINB OUTA
IOUTB
IN B OUTB
IENA ISENSE VOUTA
DIAGA/ENA CS
IENB
DIAGB/ENB VSENSE VOUTB
VINA GND A GNDB
PWM
VINB Ipw
VENA GND
VENB
IGND
Vpw
4/26
VNH2SP30-E
ELECTRICAL CHARACTERISTICS
(VCC=9V up to 16V; -40°C<Tj<150°C; unless otherwise specified)
Table 8. Power
Symbol Parameter Test Conditions Min. Typ. Max. Unit
VCC Operating supply voltage 5.5 16 V
Off state:
INA=INB=PWM=0; Tj=25 °C;
VCC=13V 12 30 µA
IS Supply Current INA=INB=PWM=0 60 µA
On state:
INA or INB=5V, no PWM 10 mA
Dynamic
IRM Cross-conduction IOUT=15A (see fig. 8) 0.7 A
Current
5/26
VNH2SP30-E
6/26
VNH2SP30-E
Note:(*) Analog sense current drift is deviation of factor K for a given device over (-40°C to 150°C and 9V<VCC<16V) with respect to it’s
value measured at T j=25°C, VCC=13V.
7/26
VNH2SP30-E
Figure 5. Typical Application Circuit For Dc To 20khz PWM OperationShort Circuit Protection
VCC
Reg 5V +5V
+ 5V
1K DIAGB/ENB
1K
DIAGA/ENA
1K HSA HSB
PWM
µC OUTA OUTB
1K INA INB
1K
LSA LSB
10K CS
M > 50uF
33nF 1.5K
GNDA GNDB
S
100K G
b) N MOSFET
In case of a fault condition the DIAGX/ENX pin is which power element is in fault by monitoring the IN A,
considered as an output pin by the device. INB, DIAGA/ENA and DIAGB/ENB pins.
The fault conditions are: In any case, when a fault is detected, the faulty leg of the
- overtemperature on one or both high sides (for example bridge is latched off. To turn-on the respective output
if a short to ground occurs as it could be the case (OUTX) again, the input signal must rise from low to high
described in line 1 and 2 in the table below); level.
- short to battery condition on the output (saturation
detection on the Low-Side Power MOSFET).
8/26
VNH2SP30-E
ISO T/R
Test Levels Result Test Levels Result Test Levels Result Test Levels Result
7637/1
I II III IV
Test Pulse
1 C C C C
2 C C C C
3a C C C C
3b C C C C
4 C C C C
5 C E E E
Class Contents
C All functions of the device are performed as designed after exposure to disturbance.
One or more functions of the device are not performed as designed after exposure to disturbance
E
and cannot be returned to proper operation without replacing the device.
Reverse Battery Protection The device sustains no more than -30A in reverse
Three possible solutions can be thought of: battery conditions because of the two Body diodes
a) a Schottky diode D connected to V CC pin of the Power MOSFETs. Additionally, in reverse
b) a N-channel MOSFET connected to the GND battery condition the I/Os of VNH2SP30-E will be
pulled down to the VCC line (approximately -1.5V).
pin (see Typical Application Circuit on page 8)
Series resistor must be inserted to limit the current
c) a P-channel MOSFET connected to the VCC pin sunk from the microcontroller I/Os. If IRmax is the
maximum target reverse current through µC I/Os,
series resistor is:
V –V
IOs CC
R = ---------------------------------
I
Rmax
9/26
VNH2SP30-E
VINA,
t
VINB
t
PWM
ILOAD
tDEL
tDEL
PWM
VOUTA, B
90% 80%
tf
20% 10% tr t
10/26
VNH2SP30-E
t
VOUTA
90%
10%
IN A=1, IN B=0
PWM
t
IMOTOR
VOUTB
t
ICC
IRM
trr
11/26
VNH2SP30-E
OUTB
IOUTA->OUTB
CS (*)
tDEL tDEL
(*) CS BEHAVIOUR DURING PWM MODE WILL DEPEND ON PWM FREQUENCY AND DUTY CYCLE
CS
INA
INB
ILIM
IOUTA->OUTB
TTSD
TTR
Tj Tj > TTR
DIAGA/ENA
DIAGB/ENB
CS
12/26
VNH2SP30-E
INA
INB
OUTA undefined
OUTB undefined
IOUTA->OUTB
DIAGB/ENB
DIAGA/ENA
CS V<nominal
13/26
VNH2SP30-E
The VNH2SP30-E can be used as a high power half-bridge driver achieving an On resistance
per leg of 9.5mΩ. Suggested configuration is the following:
VCC
INA INA
INB INB
DIAGA/ENA DIAGA/ENA
DIAGB/ENB DIAGB/ENB
PWM PWM
The VNH2SP30-E can easily be designed in multi-motors driving applications such as seat
positioning systems where only one motor must be driven at a time. DIAG X/EN X pins allow
to put unused half-bridges in high impedance. Suggested configuration is the following:
VCC
INA INA
INB INB
DIAGA/ENA DIAGA/ENA
DIAGB/ENB DIAGB/ENB
PWM PWM
M1 M3
14/26
VNH2SP30-E
Figure 14. On State Supply Current Figure 17. Off State Supply Current
Is (mA) Is (µA)
6 50
5.5 45
Vcc=13V Vcc=13V
5
INA or INB=5V 40
4.5
35
4
3.5 30
3 25
2.5 20
2
15
1.5
10
1
0.5 5
0 0
-50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175
Tc (°C) Tc (°C)
Figure 15. High Level Input Current Figure 18. Input Clamp Voltage
Iinh (µA) Vicl (V)
5 8
4.5 7.75
Vin=3.25V
Iin =1mA
7.5
4
7.25
3.5
7
3 6.75
2.5 6.5
2 6.25
6
1.5
5.75
1
5.5
0.5 5.25
0 5
-50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175
Tc (°C) Tc (°C)
Figure 16. Input High Level Voltage Figure 19. Input Low Level Voltage
Vih (V) Vil (V)
3 3
2.9
2.75
2.8
2.5
2.7
2.25
2.6
2.5 2
2.4
1.75
2.3
1.5
2.2
1.25
2.1
2 1
-50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175
Tc (°C) Tc (°C)
15/26
VNH2SP30-E
Figure 20. Input Hysteresis Voltage Figure 23. High Level Enable Pin Current
Vihyst (V) Ienh (µA)
2 8
1.75 7
Vcc=13V Ven=3.25V
1.5 6
1.25 5
1 4
0.75 3
0.5 2
0.25 1
0 0
-50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175
Tc (°C) Tc (°C)
Figure 21. Delay Time during change of Figure 24. Enable Clamp Voltage
operation mode
tdel (µs) Vencl (V)
1000
-0.2
900
-0.3
800 Ien=-1mA
-0.4
700
600 -0.5
500 -0.6
400
-0.7
300
-0.8
200
100 -0.9
0 -1
-50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175
Tc (°C) Tc (°C)
Figure 22. High Level Enable Voltage Figure 25. Low Level Enable Voltage
Venh (V) Venl (V)
3.6 3
3.4 2.8
Vcc=9V Vcc=9V
3.2 2.6
3 2.4
2.8 2.2
2.6 2
2.4 1.8
2.2 1.6
2 1.4
1.8 1.2
1.6 1
-50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175
Tc (°C) Tc (°C)
16/26
VNH2SP30-E
Figure 26. PWM High Level Voltage Figure 29. PWM Low Level Voltage
Vpwh (V) Vpwl (V)
5 2.6
4.5
2.4
Vcc=9V
4 Vcc=9V
2.2
3.5
2
3
2.5 1.8
2
1.6
1.5
1.4
1
1.2
0.5
0 1
-50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175
Tc (°C) Tc (°C)
Figure 27. PWM High Level Current Figure 30. Overvoltage Shutdown
Ipwh (µA) Vov (V)
8 30
7 27.5
Vcc=9V
Vpw=3.25V
6 25
5 22.5
4 20
3 17.5
2 15
1 12.5
0 10
-50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175
Tc (°C) Tc (°C)
75
7
70
6
65
5
60
4 55
50
3
45
2
40
1
35
0 30
-50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175
Tc (°C) Tc (°C)
17/26
VNH2SP30-E
Figure 32. On State High Side Resistance Vs. Figure 35. On State Low Side Resistance Vs.
Tcase Tcase
Ronhs (mOhm) Ronls (mOhm)
40 40
35 35
Vcc=9V; 16V Iload=12A
Iout=15A Vcc=9V; 13V; 18V
30 30
25 25
20 20
15 15
10 10
5 5
0 0
-50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175
Tc (°C) Tc (ºC)
Figure 33. Turn-on Delay Time Figure 36. Turn-off Delay Time
td(on) (µs) td(off) (µs)
260 200
240 190
220 180
200 170
180 160
160 150
140 140
120 130
100 120
80 110
60 100
-50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175
Tc (°C) Tc (°C)
Figure 34. Output Voltage Rise Time Figure 37. Output Voltage Fall Time
tr (µs) tf (µs)
2 8
1.8
7
1.6
6
1.4
5
1.2
4
1
3
0.8
0.6 2
0.4 1
0.2 0
-50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175
Tc (°C) Tc (°C)
18/26
VNH2SP30-E
Layout condition of Rth and Zth measurements (PCB FR4 area= 58mm x 58mm, PCB thickness=2mm,
Cu thickness=35µm, Copper areas: from minimum pad lay-out to 16cm2).
HIGH SIDE
CHIP
HSAB
Figure 40. Auto and mutual Rthj-amb Vs PCB copper area in open box free air condition (according
to page 20 definitions)
45
RthHS
40 RthLS
RthHSLS
35
RthLSLS
30
25
20
15
°C/W
10
5
0
0 5 10 15 20
cm2 of Cu Area (refer to PCB layout)
19/26
VNH2SP30-E
Table 17. Thermal Calculation In Clockwise And Anti-clockwise Operation In Steady-state Mode
HSA HSB LSA LSB TjHSAB TjLSA TjLSB
PdHSA x RthHS + PdLSB x PdHSA x RthHSLS + PdLSB x PdHSA x RthHSLS + PdLSB x
ON OFF OFF ON
RthHSLS + Tamb RthLSLS + Tamb RthLS + Tamb
PdHSB x RthHS + PdLSA x PdHSB x RthHSLS + PdLSA x PdHSB x RthHSLS + PdLSA x
OFF ON ON OFF
RthHSLS + Tamb RthLS + Tamb RthLSLS + Tamb
RthHS = RthHSA = RthHSB = High Side Chip ZthHS = High Side Chip Thermal Impedance
Thermal Resistance Junction to Ambient (HS A or Junction to Ambient
HSB in ON state) ZthLS = ZthLSA = ZthLSB = Low Side Chip Thermal
RthLS = R thLSA = R thLSB = Low Side Chip Thermal Impedance Junction to Ambient
Resistance Junction to Ambient ZthHSLS = ZthHSABLSA = ZthHSABLSB = Mutual
RthHSLS = RthHSALSB = RthHSBLSA = Mutual Thermal Impedance Junction to Ambient between
Thermal Resistance Junction to Ambient between High Side and Low Side Chips
High Side and Low Side Chips ZthLSLS = ZthLSALSB = Mutual Thermal Impedance
Junction to Ambient between Low Side Chips
RthLSLS = RthLSALSB = Mutual Thermal Resistance
Junction to Ambient between Low Side Chips
20/26
VNH2SP30-E
Figure 41. MultiPowerSO-30 HSD Thermal Impedance Junction Ambient Single Pulse
100
Footprint
4 cm2
8 cm2
ZthHS 16 cm2
Footprint
10 4 cm2
8 cm2
16 cm2
ZthHSLS
°C/W
0 .1
0 .0 0 1 0 .0 1 0 .1 ti m e ( se c ) 1 10 10 0 100 0
Figure 42. MultiPowerSo-30 LSD Thermal Impedance Junction Ambient Single Pulse
100
Footprint
4 cm2
ZthLS 8 cm2
16 cm2
Footprint
10 4 cm2
8 cm2
ZthLSLS 16 cm2
°C/W
0 .1
0 .0 0 1 0 .0 1 0 .1 t i m e ( se c ) 1 10 100 1000
21/26
VNH2SP30-E
Note: (*) The blank space means that the value is the same as the previous one.
22/26
VNH2SP30-E
PACKAGE MECHANICAL
23/26
VNH2SP30-E
24/26
VNH2SP30-E
REVISION HISTORY
Date Revision Description of Changes
Sep. 2004 1 - First issue.
25/26
VNH2SP30-E
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
26/26
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