5 Giao Tiep ISA PCI PDF

GIAO TIẾP QUA RÃNH
ISA - PCI
12/8/2015 ©Nguyen Trong Tai –Dr. 1
•ISA (Industry Standard Architecture)
•Hiện nay các mainboard P4 không còn rãnh cắm
ắ này tuy nhiên việc
nghiên cứu rãnh cắm ISA vẫn là cần thiết.
•Rãnh cắm ISA có màu đen trên mainboard
•Rãnh ISA gồm hai phần:
•Phần đầu 62 chân, mỗi hàngg 31 chân dùngg cho trao đổi dữ liệu 8 bit.
•Phần thứ hai 36 chân, mỗi hàng 18 chân dùng hỗ trợ thêm khi cần dữ liệu
16 bit
SA19-SAO (System Tuyến địa chỉ 20 bit dùng truy cập bộ nhớ 1 Mbyte và ngoại vi. Có thể
Address
dd bus
b 190)) d
dùng vớii LA23LA17 truy cập 16 Mbyte
b bộ b nhớ.
h Khihi truy cập ngoạii vii
(I/O) dùng 16 bit thấp cho phép truy cập 64K địa chỉ ngoại vi.
Ở chế độ đọc hay ghi khi BALE mức cao, địa chỉ được xuất ra và được
cài lại ở cạnh xuống của BALE.
Các tín hiệu này được điều khiển bởi vi xử lý hay bộ điều khiển DMA
nhưng cũng có thể được chiếm bởi card điều khiển gắn vào rãnh cắm
LA23-LA17 Dùng cùng với SA19÷0 để truy cập 16 Mbyte bộ nhớ, không được cài
(Unlatched Address lại
bus 2317)(I/O)
AEN (Address Cho phép bộ điều khiển DMA chiếm tuyến của vi xử lý khi ở mức cao
E bl ) (O)
Enable)
BALE (Buffered Dùng để cài địa chỉ LA2317 hay dùng để giải mã các địa chỉ này.
Address Latch Enable)
(O)
CLK (System Clock) Xung nhịp 4.77 MHz
(O)
SD15 - SD0 (S
(System
stem 16 bit dữ liệu
liệ
Data) (I/O)
–DACK0 - –DACK3, 0 - 3 và 5 - 7 dùng thông báo cho biết vi xử lý chấp nhận DMA khi có
–DACK5 - –DACK7 yêu cầu
ầ ở các chân
h DRQ0 - DRQ3 và DRQ5 - DRQ7
(DMA Acknowledge)
(O)
DRQ0 - DRQ3,
DRQ3 DRQ5 Dùng khi ngoại vi yêu cầu chiếm tuyến của vi xử lý ISA phục vụ cho
- DRQ7 DMA (Direct Access Memory) để trao đổi thông tin trực tiếp với bộ
(DMA Requests) (I) nhớ. DRQ sẽ ở mức cao cho đến khi DACK tương ứng ở mức thấp
– IOCHCK (I/O Ở mức cao khi có lỗi,
lỗi ngoài ra có thể do board ISA điều khiển để yêu
Channel Check) (I) cầu ngắt NMI
– IOCHRDY (I/O Cho phép các board chậm bắt vi xử lý chờ bằng cách kéo đường này
Channel Ready)
y) (I)
() xuốngg thấpp khi đangg ở chu kỳ
ỳ đọc
ọ viết, lúc đó vi xử lý
ý sẽ vào chu kỳ
ỳ
chờ cho đến khi đường này lên mức cao
– IOR (Read) (I/O) Báo ngoại vi xuất dữ liệu ra tuyến
– IOW ((Write)) (I/O)
( ) Báo ngoại
g ạ vi đọc
ọ dữ liệu
ệ trên tuyến
y
IRQ9 - IRQ12, IRQ14 Tín hiệu vào báo ngoại vi cần ngắt, IRQ sẽ ở mức cao cho đến khi vi
- IRQ15, IRQ3 - IRQ7 xử lý chấp nhận bằng chương trình phục vụ ngắt
(Interrupt Requests)
– SMEMR (System Memory Điều khiên bộ nhớ dưới 1 MB xuất dữ liệu ra
Read)(O)
d)( )
– SMEMW (System Memory Điều khiển ghi dữ liệu vào bộ nhớ dưới 1 Mbyte
Write) (O)
– MEMR (Memory Read) (O) Dùng đểể đọc dữ liệu từ bộ nhớ
– MEMW (Memory Write) (O) Ghi dữ liệu vào bộ nhớ
– REFRESH (Memory Refresh) Ở mức thấp nhất trong chu kỳ làm tươi bộ nhớ
(I/O)
OSC (Oscillator) (O) Xung nhịp 14.31818 MHz.
RESET DRV ((Reset Drive)) ((O)) Tín hiệu
ệ reset,, ở mức cao khi boot máyy
TC (Terminal Count) (O) Báo đã đếm hết trong hoạt động DMA
– MASTER (I) Khi board ISA có yêu cầu DMA nhận được DACK, nó sẽ cho
Master mức thấp để kiểm soát các tuyến
– MEM CS16 (Memory Chip Ở mức thấp khi truyền dữ liệu 16 bit với bộ nhớ
Select 16) (I)
– IO CS16 (Chip Select 16) (I) Do ngoại vi diều khiển ở mức thấp khi muốn truyền dữ liệu
16 bit
bi
– OWS (Zero Wait State) (I) Do ngoại vi điều khiển ở mức thấp cho biết không cần trạng
thái chờ
– SBHE (System Byte High Ở mức thấp
ấ khi truyền
ề byte cao
Enable)
•Thông qua rãnh cắm ISA có thể truy cập 1024 địa chỉ ngoại vi từ 000
đế 3FF
đến
•Trong đó một số đã sử dụng cho các thiết bị có sẵn của máy tính
000 –00F Truy cập bộ nhớ trực tiếp ( DMA Direct memory access controller)
020 –021 Điều khiển ngắt ( PIC Programmable interrupt controller)
040 – 043 Timer hệ thống (System timer)
060 – 060 Bàn phím ( Keyboard)
061 – 061 Loa trong ( System speaker)
064 – 064 Bàn phím
070 – 071 RAM hệ thống và đồng hồ thời gian thực (System CMOS/ RTC)
081 – 083 DMA
087 – 087 DMA
089 – 08B DMA
08F – 091 DMA
đế 3FF
đến
0A0 – 0A1 PIC

0C0 0DF
0C0 – DMA
0F0 – 0FF Đồng xử lý số học (Numeric data processor)
168 – 16F Điều khiển đĩa cứng (Standard IDE/ESDI Hard Disk Controller)
170 – 177 Điều khiển IDE (Secondary IDE controller Intel 82371 AB/EB )
1F0 – 1F7 Điều khiển IDE (Primary IDE controller)
201 – 201
201 Que trò chơi (Game port Joystick)
208 – 20F Dành cho mainboard (Motherboard resources)
220 – 22F Card âm thanh (ES 1868 Plug and Play Audio Drive)
274 – 277 IO read data port for ISA Plug and Play enumerator
dd f l d l
2F8 – 2FF Cổng truyền thông 2 (COM2)
đế 3FF
đến
330 – 331 Card âm thanh

36E – 36F Điều
iề khiển
khiể đĩa
đ cứng (Standard
( d d IDE/ESDI
/ Hardd Disk
i k Controller
ll
376 – 376 Điều khiển IDE (Secondary IDE controller)
378 – 37F Cổng song song (LPT1)
388 – 38B Card âm thanh
3B0 – 3BB Card video S3 Inc. Trio3D/2X (Engineering Release)
3C0 – 3DF Card video S3 Inc.
Inc Trio3D/2X (Engineering Release)
3F2 – 3F5 Điều khiển ổ đĩa mềm (Standard Floppy Disk Controller)
3F6 – 3F6 Điều khiển IDE (Primary IDE controller)
3F8 – 3FF Cổng
ổ truyềnề thông 1 (COM1)
•Tuyến ISA có nhiều chân nhưng thực tế sử dụng ta chỉ cần các đường
Địa chỉ SA0..SA9,
Dữ liệu SD0..SD15,
Điều khiển –IOR,
IOR, -IOW,
IOW, AEN, -IOCS16,
IOCS16, -SBHE,
SBHE,
Ngõ vào ngắt IRQ,
Xung nhịp CLK và nguồn.
Các ngoại vi được gọi là port thường là 8 bit và việc xuất nhập thực hiện
theo 8 bit, nếu xuất nhập 16 bit thì dùng hai port địa chỉ kế nhau
Việc thiết kế card ISA xuất nhập 8 bit tương đối đơn giản, bao gồm mạch giải mã địa
chỉ, mạch chốt dữ liệu ra và mạch đệm dữ liệu vào
•Giãn đồ thời gian ghi/đọc dữ liệu
•Ví dụ sử dụng địa chỉ 300H ta dùng mạch logic tạo tín hiệu /CS, mạch chốt và đệm
dùng vi mạch 74LS373
•
• Card peripheral adapter sử dụng hai vi mạch 74245 đệm tuyến hai chiều cho số liệu,
hai vi mạch 74244 đệm tuyến địa chỉ và điều khiểnkhiển.
• Vi mạch 74138 giải mã địa chỉ 300 đến 31F, khi truy cập vùng địa chỉ này, chân Y4
của (/IO decode) xuống thấp đưa vào (74LS244) cho phép xuất ra đường MEMW và
I/O decode 8 bit.
bit
• Cầu nối 8/16 bit cho phép chọn chế độ 8 bit hay 16 bit.
• Khi chọn chế độ 8 bit (cầu nối hở). thì 8 bit cao được truyền khi đường địa chỉ ở mức
cao (địa
(đị chỉ
hỉ lẻ) vàà 8 bit thấp
thấ đđược ttruyền
ề khi đđường
ờ đị địa chỉ
hỉ Ao ở mức
ứ thấp
thấ (địa
(đị chỉ
hỉ
chẵn)
•Mạch mở rộng 4 8-bit Input line và 4 8-bit Output line
The P.O.S.T. card can be constructed fairly easily. For the design in this
d
document, an EPROM programmer must be b available.
il bl EPROMs
EPROM are usedd
as combinational logic to go from a 4-bit binary number to the pins on a
7-segment
g display.
p y
•Address and control signal decoding
•Data register
•Binary-to-7-segment conversion and display
7404 Hex Inverter 2
7430 8‐input NAND 1
7432 Quad OR 1
74374 Octal latch 1
2732 EPROM 2
Common Anode 7‐Seg. Display 2
•The address and control signal decoding is accomplished with IC1, IC2,
IC3 IC4 in
IC3, i the
h schematic.
h i
•When the address 80 hexadecimal is sent out on the address lines, and
AEN is low, and IOW pulses low, these three conditions cause pin 11 of
IC4 to go low, clocking the data into the register (IC5).
• From here, the upper 4 bits of the data (which comprise the most
significant
i ifi hex
h digit)
di i ) are sent to an EPROM andd 7-segment
7 di l
display,
while the lower 4 bits are sent to the other EPROM and display.
•Each EPROM is a combinational logic block which converts a 4-bit
bi
binary number
b ( a single
i l hexh digit)
di i ) into
i the
h 7 lines
li needed
d d for
f a 7-
7
segment display.
•Those
Those familiar with the 7447 chip (BCD(BCD-to-7-segment
to 7 segment decoder) will be
familiar with this concept; the only difference is that the 7447 takes a
Binary Coded Decimal number as input and drives a 7-segment display
on the output,
output while the EPROM takes a single hex digit (4-bit (4 bit binary
number) as the input and drives a 7-segment display on the output.
• I could not locate a chipp to do the jjob,, so I used EPROMs instead. The
4-bit binary number is fed to the address lines of the EPROM, and the
corresponding 7-segment code then appears on the EPROM data lines.
You can see that this is a 'look-up
look-up table
table' approach of logic conversion.
conversion
Hex Input Display 7‐Seg. Codes
Hex EPROM
(EPROM
(EPROM Segments (EPROM
(EPROM
Data
Address) Turned On Data)
0 a b c d e f 1000 0001 81
1 b c 1100 1111 CF
2 a b g e d 1001 0010 92
3 a b c d g 1000 0110 86
4 f g b c 1100 1100 CC
5 a f g c d 1010 0100 A4
6 a f g e c d 1010 0000 A0
7 a b c 1000 1111 8F
8 a b c d e f g 1000 0000 80
9 a b g f c d 1000 0100 84
A a b g f c d 1000 1000 88
B a b g f c e 1110 0000 E0
C a f e d 1011 0001 B1
D b c d e g 1100 0010 C2
E a f g e d 1011 0000 B0
F a f g e 1011 1000 B8
•Example 1
•Example 2
•Example 2
Example 3
Example 4
Example 5
GIAO TIẾP QUA RÃNH PCI
Peripheral Component Interconnect (PCI).
Local Bus Concept
• More bandwidth
More bandwidth
– Video Card
– Hard disks
H d di k
• Faster CPUs
– But still slow IO bus
• Bus close to CPU and memory bus
Dual Independent Bus (DIB)
• Backside Bus
• Frontside
F id Bus
B
• PCI
– Direct
Direct access to system
access to system
memory for connected
devices
– Uses a bridge to
b d
connect to the
frontside bus and
therefore to the CPU
Different level of Busses
Bus Comparisons
Bus Bus Bus MB/se

T
Type Width S
Speedd c
ISA 16 bits 8 MHz 16 MBps
EISA 32 bit
bits 8 MH
MHz 32 MB
MBps
VL-bus 32 bits 25 MHz 100 MBps
VL-bus 32 bits 33 MHz 132 MBps
PCI 32 bits 33 MHz 132 MBps
PCI 64 bits 133 MHz 1 GBps
North / South bridge
An Example
Typical PCI Card
A typical PCI card
PCI card – 47 pins
PCI Revision 2.1 Features
• Processor independence
• Low-power
p consumption
p
• Burst use for all read and write transfers
• Bus speed up to 66 MHz
• 64-bit bus width
• Low pin count (PCI Target: 47,PCI Initiator: 49 pins)
• C
Concurrent t bus
b operation
ti
• Bus master support
• Hidden bus arbitration
• Auto configuration
Intro to PCI Bus Operation
Key Terms
• Initiator
• — Or Master
• — Owns the bus and initiates the data transfer
• — Every Initiator must also be a Target
• Target
• — Or Slave
• — Target of the data transfer (read or write)
• Agent
• — Any initiator/target or target on the PCI bus
PCI Bus Clock
• All action synchronize to the PCI clock
• Clock may be any where from 0 MHz to 33 MHz and all PCI device must be support this
range
• The revision 2.1 specification define speed up to 66 MHz
Address phase
• At the same time,, initiator identifiers target
g device and the type
yp of transaction
• The initiator assert the FRAME# signal
• Every PCI target device latch the address and decode it
Data Phase
• Number of data bytes to be transformed is determined by the number of
Command/Byte y Enable signals
g asserted byy initiator
• Both of initiator and target must t ready to complete data phase
• IRDY# and TRDY# used
Transaction Duration
• By asserting FRAME# at start of address phase and remain until the final
d t phase
data h
Transaction completion and return of bus to idle state
• By deasserting the FRAME# but asserting IRDY#
• When the last data transfer has completed the initiator returns the PCI bus to
idle state by deasserting IRDY#
PCI Signals
• - Clock and Reset

• Transaction Control
1. Initiator Signals
2. Target Signals
3. Configuration Signals
• Address and Data Signals
• Arbitration Signals
• Error Signals
g
PCI Lines
Clock and Reset
• CLK
– — PCI input clock
– — All signals sampled on rising edge
– — 33MHz is really 33.33333MHz (30ns clk. period)
– — The clock is allowed to vary from 0 to 33 MHz
• – The frequency can change “on
on the fly
fly”
• – Because of this, no PLLs are allowed
• RST#
– — Asynchronous reset
– — PCI device must tri-state all I/Os during reset
Transaction Control - Target Signals
• TRDY# – I/O
– — “T-Ready”
– — When
Wh theth target
t t asserts
t this
thi signal,
i l it tells
t ll th
the iinitiator
iti t ththatt it
is ready to send or receive data
• STOP# – I/O
– — Used by target to indicate that it needs to terminate the
– transaction
Transaction Control - Target Signals
• DEVSEL# – I/O
– — Device select
– — Part
P t off PCI’
PCI’s distributed
di t ib t d address
dd decoding
d di
• – Each target is responsible for decoding the address associated with
each transaction
• – When a target recognizes its address, it asserts DEVSEL# to claim
the corresponding transaction
Transaction Control – Initiator Signals
• FRAME# – I/O
– — Signals the start and end of a transaction
• IRDY# – I/O
– — “I-Ready”
– — Assertion by initiator indicates that it is ready to send receive
data
Transaction Control - Configuration Signals
• Uses the same signals as the target,
target plus . . .
• IDSEL – I
– — “ID
ID-Sel
Sel”
– — Individual device select for configuration – one unique
IDSEL line per agent
– — Solves the “chicken-and-egg” problem
– – Allows the system
y host to configure
g agents
g before these
agents know the PCI addresses to which they must respond
Address and Data Signals
• AD[31:0] – I/O
– — 32-bit address/data bus
– — PCI is little endian (lowest numeric index is LSB)
• C/BE#[3:0] – I/O
– — 4-bit command/byte
y enable bus
– — Defines the PCI command during address phase
– — Indicates byte enable during data phases
• – Each bit corresponds to a “byte-lane” in AD[31:0] – for example,C/BE#[0] is the
byte enable for AD[7:0]
Address and Data Signals
• PAR – I/O
– — Parity bit
– — Used
U d tot verify
if correctt ttransmittal
itt l off address/data
dd /d t andd
command/byte-enable
– — The XOR of AD[31:0]
AD[31:0], C/BE#[3:0]
C/BE#[3:0], and PAR should return
zero (even parity)
• – In other words,
words the number of 1’s
1 s across these 37 signals should be
even
Arbitration Signals
• For initiators only!
• REQ# – O
– — Asserted byy initiator to request
q bus ownershipp
– — Point-to-point connection to arbiter – each initiator has its own REQ#
line
• GNT# – I
– — Asserted by system arbiter to grant bus ownership to the initiator
– — Point-to-point
Point to point connection from arbiter – each initiator has its own GNT#
line
Error Signals
• PERR# – I/O
– — Indicates that a data parity error has occurred
– — An agent that can report parity errors can have its PERR#
turned off during PCI configuration
• S
SERR## – I/O
/O
– — Indicates a serious system error has occurred
• – Example: Address parity error
– — May invoke NMI (non-maskable interrupt, i.e., a restart) in
some systems
Basic Bus Operations
Terms
• Doubleword
• — 32 bits, most often known as a “DWORD”
DWORD
• Quadword
• — 64 bits,, sometimes known as a “QWORD”
Q
• Burst transaction
• — Anyy transaction consistingg of more than one data pphase
• Idle state (no bus activity)
• — Indicated by FRAME# and IRDY# deasserted
Transfer Modes
Burst Mode
Example #1 – Basic Write
• A four-DWORD burst from an initiator to a

target
Write Transfer
PCI Bus Cycles
Basic Write Transaction
Write Example – Things to Note
• The initiator has a phase profile of 3-1-1-1
3111
– — First data can be transferred in three clock cycles (idle +
address +data = “3”)
3)
– — The 2 nd , 3 rd , and last data are transferred one cycle each
( 1-1-1 )
(“1-1-1”)
Write Example – Things to Note
• The target profile is 55-1-1-1
111
– — Medium decode – DEVSEL# asserted on 2 nd clock after FRAME#
– — One clock period of latency (or wait state) in the beginning of the
transfer
– – DEVSEL# asserted on clock 3, but TRDY# not asserted unti clock 4
– — Ideal target write is 33-1-1-1
111
• Total of 4 data phases, but required 8 clocks
– — Onlyy 50% efficiencyy
Target Address Decoding
• PCI uses distributed address decoding
– — A transaction begins over the PCI bus
– — Each potential target on the bus decodes the transaction
transaction’ss
PCI address to determine whether it belongs to that target’s
assigned address space
• – One target may be assigned a larger address space than another,
and would thus respond to more addresses
– — The target that owns the PCI address then claims the
transaction by asserting DEVSEL#
Distributed Address Decoding
Target Decode
• Address decoders come in different speeds
• If a transaction g
goes unclaimed (nobody
( y asserts DEVSEL#),
) “Master Abort” occurs
Example #2 – Target Read
• A four-DWORD burst read from a target by an initiator
More Terms
• Turnaround cycle
– — “Dead” bus cycle to prevent bus contention
• Wait state
– — A bus cycle where it is possible to transfer data, but no data
– transfer occurs
– — Target
T t ddeasserts
t TRDY# to
t signal
i l it iis nott ready
d
– — Initiator deasserts IRDY# to signal it is not ready
• Target termination
– — Target asserts STOP# to indicate that it needs to terminate the current
transaction
Target Read – Things to Note
• Wait states may be inserted dynamically by the
initiator or target by deasserting IRDY# or TRDY#
• Either agent may signal the end of a transaction
– — The target signals termination by asserting STOP#
– — The initiator signals completion by deasserting FRAME#
Zero and One Wait State
• A one-wait-state
one wait state agent inserts a wait state at the
beginning of each data phase
– — This is done if an agent – built in older,
older slower silicon –
needs to pipeline critical paths internally
– — Reduces bandwidth by 50%
Zero and One Wait State
• The need to insert a wait state is typically an issue only when
the agent is sourcing data (initiator write or target read)
– — Thiss iss because suc
such aan age
agent would
ou d havea e too sa
sample
p e itss cou
counterpart’s
e pa s
xRDY# signal to see if that agent accepted data,then fan out to 36 or
more clock enables (for AD[31:0] and possibly C/BE#[3:0]) to drive the
next piece of data onto the PCI bus . . . all within 11 ns!
– – And even that 11 ns would be eaten up by a chip’s internal clock-
distribution delayy
PCI
C Addressing
and Bus Commands
PCI Address Space
• A PCI target can implement up to three different types of
address spaces
g
• — Configuration space
p
– – Stores basic information about the device
– – Allows the central resource or O/S to program a device with operational
settings
• — I/O space
– – Used mainlyy with PC pperipherals
p and not much else
• — Memory space
– – Used for just about everything else
Types of PCI Address Space
• Configuration space
• — Contains basic device information, e.g., vendor or class of
device
• — Also permits Plug-N-Play
– – Base address registers allow an agent to be mapped dynamically into
memory or I/O space
– – A programmable interrupt-line setting allows a software driver to
program a PC card with an IRQ upon power-up (without jumpers!)
Types of PCI Address Space
• Configuration space (cont
(cont’d)
d)
• — Contains 256 bytes
– – The first 64 bytes (00h – 3Fh) make up the standard
configuration header, predefined by the PCI spec
– – The remaining 192 bytes (40h – FFh) represent user
user-
definable configuration space
• • This region may store, for example, information specific to a PC card
for use
se by
b its accompan
accompanyinging soft
software
are dri
driver
er
IO Space
• — This space is where basic PC peripherals (keyboard,
(keyboard
serial port,etc.) are mapped
• — The
Th PCI spec allowsll an agentt to
t requestt 4 bbytes
t tot
2GB of I/O space
– – For x86 systems, the maximum is 256 bytes because of
legacy ISA issues
Memory Space
• Memory space
• — This space is used by most everything else – it’s the general-
ppurpose
p address space
p
– – The PCI spec recommends that a device use memory space, even if it
is a peripheral
• — An agent can request between 16 bytes and 2GB of memory
space
– – The PCI spec
p recommends that an agentg use at least 4kB of memoryy
space, to reduce the width of the agent’s address decoder
PCI Commands
• PCI allows the use of up to 16 different 4-bit commands
– — Configuration commands
– — Memory commands
– — I/O commands
– — Special-purpose commands
• A command is presented on the C/BE# bus by the initiator
during an address phase (a transaction’s first assertion of
FRAME#)
PCI Commands
PCI Configuration
The Plug-and-Play Concept
• Plug-and-Play
Plug and Play (PNP)
• — Allows add-in cards to be plugged into any slot without
changing
g g jjumpers
p or switches
– – Address mapping, IRQs, COM ports, etc., are assigned dynamically at
system start-up
• — For PNP to work,
work add-in
add in cards must contain basic information
for the BIOS and/or O/S, e.g.:
– – Type
yp of card and device
– – Memory-space requirements
– – Interrupt requirements
Configuration Transactions
• Are generated by a host or PCI
PCI-to-PCI
to PCI bridge
• Use a set of IDSEL signals as chip selects
– — Dedicated address decodingg
– — Each agent is given a unique IDSEL signal
• Are typically single data phase
– — Bursting is allowed, but is very rarely used
• Two types (specified via AD[1:0] in addr. phase)
– — Type 0: Configures agents on same bus segment
– — Type 1: Configures across PCI-to-PCI bridges
Required
q byy PCI Spec
p 2.2
Why PCI‐X 2.0?
Bus Bandwidths
PCI‐X 2.0 Write ‐ Example
Productization Timeline

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GIAO TIẾP QUA RÃNH

0A0 – 0A1 PIC

330 – 331 Card âm thanh

Peripheral Component Interconnect (PCI).

Bus Bus Bus MB/se

VL-bus 32 bits 25 MHz 100 MBps

VL-bus 32 bits 33 MHz 132 MBps

PCI 32 bits 33 MHz 132 MBps

PCI 64 bits 33 MHz 264 MBps

PCI 64 bits 66 MHz 512 MBps

PCI 64 bits 133 MHz 1 GBps

A typical PCI card

• - Clock and Reset

• A four-DWORD burst from an initiator to a

• A four-DWORD burst read from a target by an initiator

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