Chapter 1 Introduction To VLSI Testing PDF

VLSI TESTING
積體電路測試
CHAPTER 1
INTRODUCTION
TO VLSI TESTING
賴秉樑
PING-LIANG LAI 1
VLSI TESTING 2012 Chapter 1-1

What is this Chapter About?
 Introduce fundamental concepts and various aspects of VLSI

testing
 Focus on
– Importance of testing in the design and manufacturing processes
– Levels of abstraction in VLSI testing
– Challenges in test generation and fault modeling
 Provide overview of VLSI test technology
PING-LIANG LAI VLSI TESTING 2012 Chapter 1-2

Outline
 Introduction
 Design and Testing
 Cost of an Integrated Circuit (IC)
 Testing During VLSI Life Cycle
 Test Generation, Fault Model, Fault Coverage and Defect Level
 Levels of Abstraction
 Overview of VLSI Test Technology
 Concluding Remarks
 LAB1

Introduction
 Integrated Circuits (ICs) have grown in size and complexity since the late 1950’s
– SSI, MSI, LSI, and Very Large Scale Integration (VLSI)
 Moore’s Law: scale of ICs doubles every 18 months
– Growing size and complexity poses many and new testing challenges
1.E+09
1.E+08
1.E+07
Number of Transistors
1.E+06
1.E+05
1.E+04
1.E+03 VLSI
1.E+02
M LSI
S S
1.E+01 S
I
I
1.E+00
1960s 1970s 1980s 1990s 2000s

Importance of Testing (1/2)
 Moore’s Law results from decreasing feature size (dimensions)

– From 10s of μm to 10s of nm for transistors and interconnecting wires
 Operating frequencies have increased from 100 KHz to several
GHz
 Decreasing feature size increases probability of defects during
manufacturing process
– A single faulty transistor or wire results in faulty IC
– Testing required to guarantee fault-free products

Importance of Testing (2/2)
 Rule of Ten: cost to detect faulty IC increases by an order of

magnitude as we move from
– Device → PCB → System → Field operation
• Testing performed at all of these levels
 Testing also used during
– Manufacturing to improve yield
• Failure Mode Analysis (FMA)
– Field operation to ensure fault-free system operation
• Initiate repairs when faults are detected

Outline
 Introduction
 LAB1

ASICs Design
 Type of Application-Specific Integrated circuits (ASICs)

– Full-custom ASICs
– Semi-custom ASICs
• Cell-based ASICs
• Gate Array-based ASICs
– Programmable ASICs
• Programmable Logic Devices
• Field Programmable Gate Array
Building block Interconnection

Full-custom Yes Yes
Semi-custom No Yes
Programmable No No

ASICs Design Flow
Cell Based Design Flow
Advanced VLSI Research Center Specification
System-Level
Design & Sim SPW Matlab
BONeS
ASIC
Behavior
Synthesis Visual Architect
Full-Custom Cell-Based FPGA MathWork RTW
Full Custom Design Flow RTL-Level Sim

Verilog-XL Synopsys VCS
Circuit-Level Design
Composer
RTL Synthesis
Ambit
Pre-Layout Circuit-Sim Cell Library
Design-Compiler
Hspice
Spice Model
SBTSPICE Gate-Level Sim
Synopsys VCS
Cell Library
Physical Layout Model Verilog-XL
Virtuoso
Physical
Verification Apollo/Hercules
Physical Verification
& RC Extraction Dracula Silicon Ensemble Ultra / Dracula
RC Extraction
Post-Layout Sim Star-RC Dracula
Hspice
Spice Model
& RC SBTSPICE Post-Layout Sim
TimeMill Star-time Star-sim
Tape Out
Tape Out
VLSI TESTING 2012 Chapter 1-9
The VLSI Testing Process
 Verification Testing (also called Design Verification)

– Verifies correctness of design and test procedure
– More common to correct design than test procedure
– Functional test, AC and DC parameter test
 Manufacturing Testing
– Factory testing of all manufactured chips for parametric faults and for random
defects
 Reliability Testing
– Reliability testing guarantees the reliability of product
– Various higher power supply, increasing test time and high temperature
 Acceptance Testing (incoming inspection)
– Customer performs tests on purchased parts to ensure quality

Verification vs. Testing
 Design Verification vs. Manufacturing Test

– Design Verification ensure “design” matches intent
– Manufacturing Test ensures “parts” are manufactured correctly
HW Design Manufacturing
Verification Testing
Specification Netlist Silicon
 How is Manufacturing Test performed?

– Automatic Test Equipment (ATE) applies input stimulus to the Device Under
Test (DUT) and measure the output response.
– If the ATE observes a response different from the expected response, the DUT
fails that test
Testing Principle
 Testing Principle: three components, input patterns, DUT, and stored golden
response
– When the chip is digital, the stimuli are called test patterns or test vectors.
Input patterns Output response
PIs or POs or
Scan in Scan out
Stored golden response
 ATE carries out this process

– A powerful computer operating under the control of a test program, a program written
in a high level language
– Digital Signal Processor (DSP) used for analog testing

ATE for Manufacturing Test
 Major ATE Companies: Agilent Technologies, Advantest, Credence

Systems Corporation, HCL Technologies, LTX, National Instruments,
Rohde & Schwarz, SPEA, Teradyne, Verigy…..

Flow of Manufacturing Test

Outline
 Introduction
 LAB1

Silicon Wafer and Dies
 Exponential cost decrease – technology basically the same

– A wafer is tested and chopped into dies that are packaged
Packaging process dies along the edge
Die (晶粒)
Wafer (晶圓)
Die → Chip (晶片)
AMD K8, source: http://www.amd.com

Cost of an Integrated Circuit (IC)
Cost of die  Cost of testing die  Cost of packaging and final test
Cost of IC 
Final test yield
(A greater portion of the cost that varies between machines)
Cost of wafer
Cost of die 
# Dies per wafer  Die yield
π  Wafer radius 
2
π  Wafer diameter
# Dies per wafer  
Die area 2  Die area
(sensitive to die size) (# of dies along the edge)
α
 Defect desity  Die area 
Die yield  Wafer yield  1  
 α 
Today’s technology:   4.0, defect density 0.4 ~ 0.8 per cm2

Examples of Cost of an IC
 Example 1: Find the number of dies per 30-cm wafer for a die that is 0.7 cm on a side.
– The total die area is 0.49 cm2. Thus
π  Wafer radius 
2
π  Wafer diameter
# Dies per wafer  
Die area 2  Die area
  30 / 2 2   30 706.5 94.2
     1,347
0.49 2  0.49 0.49 0.99
 Example 2: Find the die yield for dies that are 1 cm on a side and 0.7 cm on a side, assuming a defect
density of 0.6 per cm2.
– The total die areas are 1 cm2 and 0.49 cm2. For the large die the yield is
α
 Detect desity  Die area 
Die yield  Wafer yield  1  
 α 
4
 0.6  1 
 1    0.35
 4.0 
For the small die, it is
4
 0.6  0.49 
Die yield  1    0.58
 4.0 
Outline
 Introduction
 LAB1

Testing During VLSI Life Cycle
 Testing typically consists of (three parts)

– Applying set of test stimuli to
– Inputs of Circuit Under Test (CUT), and
– Analyzing output responses
• If incorrect (fail), CUT assumed to be faulty
• If correct (pass), CUT assumed to be fault-free
Input1 Output1
Input Circuit Output
Test Under Test Response Pass/Fail
Inputn Outputm
Stimuli (CUT) Analysis

Testing During VLSI Development
 Design Verification targets Design Specification

design errors
– Corrections made prior to Design Design Verification
fabrication
 Remaining tests target Fabrication Wafer Test
manufacturing defects
– A defect is a flaw or physical
Packaging Package Test
imperfection that can lead to
a fault
Quality Assurance Final Testing

Design Verification
 Different levels of abstraction during Design Specification

design
– CAD tools used to synthesize design
from RTL to physical level Behavioral (Architecture) Level
 Simulation used at various level to
test for Register-Transfer Level
– Design errors in behavioral or RTL
– Design meeting system timing
requirements Logical (Gate) Level
Physical (Transistor) Level

Yield and Reject Rate
 We expect faulty chips due to manufacturing defects

– Called yield
number of acceptable parts
yield 
total number of parts fabricated
 2 types of yield loss

– Catastrophic – due to random defects
– Parametric – due to process variations
 Undesirable results during testing
– Faulty chip appears to be good (passes test)
• Called reject rate
number of faulty parts passing final test
reject rate 
total number of parts passing final test
– Good chip appears to be faulty (fails test)
• Due to poorly designed tests or lack of Design for Testability (DFT)

Electronic System Manufacturing
 A system consists of PCBs that PCB Fabrication Bare Board Test

consist of
– VLSI devices
PCB Assembly Board Test
 PCB fabrication similar to VLSI
fabrication
– Susceptible to defects Unit Assembly Unit Test
 Assembly steps also susceptible

to defects System Assembly System Test
– Testing performed at all stages of
manufacturing

System-Level Operation (1/2)
 Faults occur during system operation
S Normal system operation
1
0
t0 t1 t2 t3 t4 t
failures
 Exponential failure law
– Interval of normal system operation is random number exponentially
distributed
 Reliability
– Probability that system will operate normally until time t P(Tn  t )  e  t
k
– Failure rate , is sum of individual component failure rates, i    i
i 0

System-Level Operation (2/2)

1

 t
 Mean Time Between Failures (MTBF) MTBF  e dt 
0

 Repair time (R) also assumed to obey

exponential distribution
P ( R  t )  e  t
–  is repair rate
1
 Mean Time To Repair (MTTR) MTTR 

 Fraction of time that system is operating

normally called system availability
– High reliability systems have system MTBF
system availability 
availabilities greater than 0.9999 MTBF  MTTR
• Referred to as “four 9s”

System-Level Testing
 Testing required to ensure system availability

 Types of system-level testing
– On-line testing – concurrent with system operation
– Off-line testing – while system (or portion of) is taken out of service
• Performed periodically during low-demand periods
• Used for diagnosis (identification and location) of faulty replaceable
components to improve repair time

Outline
 Introduction
 LAB1

Test Generation (1/4)
 A test is a sequence of test patterns, called test vectors, applied to

the CUT whose outputs are monitored and analyzed for the correct
response
– Exhaustive testing – applying all possible test patterns to CUT
– Functional testing – testing every truth table entry for a combinational logic
CUT
• Neither of these are practical for large CUTs
 Fault coverage is a quantitative measure of quality of a set of test
vectors
29
 Test usually is including (test vector file, instructions of test program)
 Test Vector, Test pattern or true table (0, 1, L, H, Z, X)
– Test time of each test vector is called test period (test cycle)
 Type of Test method
– Exhaustive Vector: list all possible input as test vector to reach 100% fault coverage
• N-inputs, 2N test vectors
• 14-inputs of 74181ALU, 214=16,384 test vectors
• 10 MHz and 38-inputs of 16-bit ALU need 7.64 hours. (WOW!!)
– Functional Vector
• Major using in verification test
• 71181 ALU only need 448 test vectors
• However, few algorithm to verify all function on a chip
– Structural Vector
• A vector based on a specific fault model, but fault model must extract (is it possible?);
• Using EDA tools to automatic generate test vectors
• 74181ALU only 47 test vectors

 Fault coverage for a given set of test vectors
number of detected faults

fault coverage 
total number of faults
 100% fault coverage may be impossible due to undetectable faults
 Reject rate = 1 – yield (1 – fault coverage)

– A PCB with 40 chips, each with 90% fault coverage and 90% yield, has a
reject rate of 34.4%
• Or 344,000 defective parts per million (PPM)
number of detected faults

fault detection efficiency 
total number of faults  number of undetectable faults

 Goal: find efficient set of test vectors with maximum fault
coverage
 Fault simulation used to determine fault coverage
– Requires fault models to emulate behavior of defects
 A good fault model
– Is computationally efficient for simulation
– Accurately reflects behavior of defects
 No single fault model works for all possible defects

An Example – A Test Pattern
 A test pattern
0 stuck-at 1
0 0/1
1 0/1
1 1
 A test pattern with don't cares
1 stuck-at 0
1/0 (Good value and faulty value are
x 1/0
x x different at a PO)
x x
 Test generation: generates a test for a target fault

An Example – Fault Modeling
 The effects of physical defects

 Most commonly used fault model: single stuck-at-fault
A E A: s-a-1 B: s-a-1 C: s-a-1 D: s-a-1

B A: s-a-0 B: s-a-0 C: s-a-0 D: s-a-0
G
E: s-a-1 F: s-a-1 G: s-a-1
C F E: s-a-0 F: s-a-0 G: s-a-0
D
2 × 7 = 14 faults
 Other fault models

– Break faults, Bridging faults, Transistor stuck-open faults, Transistor stuck-on
faults, Delay faults

An Example – Fault Coverage (FC)
 Fault Coverage
# faults detected
FC 
# faults in fault list
 Example:
a 6 stuck-at faults
c
b {a/0, a/1, b/0, b/1, c/0, c/1}
Test Faults detected FC

{(0,0)} c/1 16.67%
{(0,1)} a/1, c/1 33.33%
{(1,1)} a/0, b/0, c/0 50.00%
{(0,0), (1,1)} a/0, b/0, c/0, c/1 66.67%
{(1,0), (0,1), (1,1)} All 100.00%

An Example – Testing and Quality
Shipped Parts
Yield (Y): Quality:
Fraction of good Defective parts
parts per million
(DPM)
Rejects
 Quality of shipped parts is a function of yield Y and the test (fault)

coverage T
 Defect level (DL): fraction of shipped parts that are defective

An Example – Defect Level, Yield and Fault Coverage
DL: defect level

DL = 1- Y (1-T) Y: yield
T: fault coverage
Yield (Y) Fault Coverage (T) DPM (DL)

50% 90% 67,000
75% 90% 28,000
90% 90% 10,000
95% 90% 5,000
99% 90% 1,000
90% 90% 10,000

90% 95% 5,000
90% 99% 1,000
90% 99.9% 100

Outline
 Introduction
 LAB1

Levels of Abstraction
 High levels have few implementation details needed for effective

test generation
– Fault models based on gate & physical levels
 Example: two circuits for same specification
– Ckt B test vectors do not detect 4 faults in Ckt A
a SA1
f(a, b, c)=m(2, 7) + d(6) = abc + abc + Xabc b
c
SA1 f
ab
c 00 01 11 10 f = abc + abc SA1 Circuit A
0 1 X SA1
Circuit A Test Vectors
1 1 {111, 110, 101, 011, 010, 000}
a
ab b
c 00 01 11 10 Circuit B
f = ab + bc f
0 1 X
Circuit B Test Vectors
1 1 {111, 101, 010, 000} c

Outline
 Introduction
 LAB1

Overview of VLSI Test Technology
 ATE consists of
– Computer – for central control and flexible test & measurement for different
products
– Pin electronics & fixtures – to apply test patterns to pins & sample responses
– Test program – controls timing of test patterns & compares response to
known good responses
 Automatic Test Pattern Generation (ATPG)
– Algorithms generating sequence of test vectors for a given circuit based on
specific fault models
 Fault simulation
– Emulates fault models in CUT and applies test vectors to determine fault
coverage
– Simulation time (significant due to large number of faults to emulate) can be
reduced by
• Parallel, deductive, and concurrent fault simulation

Overview of VLSI Test Technology
 Design for Testability (DFT)

– Generally incorporated in design
– Goal: improve controllability and/or observability of internal nodes of a chip
or PCB
 Three basic approaches
– Ad-hoc techniques
– Scan design
• Boundary Scan
– Built-In Self-Test (BIST)

Design of Testability – Ad-hoc
 Ad-hoc DFT techniques

– Add internal test points (usually multiplexers) for
• Controllability
• Observability
– Added on a case-by-case basis
• Primarily targets “hard to test” portions of chip
Normal system data 0 Normal system data 0

Internal node to be
Test data input 1 Internal node 1 Primary
observed
to be output
Test mode select controlled Test mode select
controllability test point observability test point

Design for Testability – Scan Primary Primary
Inputs Combinational Outputs
Logic
 Scan design
– Transforms flip-flops of chip FFs
into a shift register
1
– Scan mode facilitates Di
• Shifting in test vectors Di Qi 0 Qi
FF 1 FF
• Shifting out responses Qi-1
2
 Good CAD tool support Clk Scan Clk
Mode
– Transforming flip-flops to shift 3
register
Primary Primary
– ATPG Combinational Outputs
Inputs
Logic
Scan
Data
FFs Out
Scan Data In 44

Design for Testability – Scan
 Boundary Scan (BS) – scan design applied to I/O buffers of chip

– Used for testing interconnect on PCB
• Provides access to internal DFT capabilities
– IEEE standard 4-wire Test Access Port (TAP)
TAP pin I/O Function
TCK input Test clock
TMS input Test Mode Select tri-state control
TDI input Test Data In from IC Control
TDO output Test Data Out Scan Out BS Cell
Input Output BS Cell

0 Output
0 1
Scan In 1 capture update Pad
FF FF
Shift
Input
Capture Update
input data BS Cell
to IC

A Board Containing 4 IC’s with BS
Boundary-scan cell Boundary-scan chain
Serial
Data in
Internal Internal
Logic Logic
Internal Internal
Serial Logic Logic
Data out
System interconnect

Design for Testability – BIST
 Built-In Self-Test (BIST): major for at-speed requirement

– Incorporates test pattern generator (TPG) and output response analyzer
(ORA) internal to design
• Chip can test itself
– Can be used at all levels of testing
• Device  PCB  System  Field operation
Primary Inputs
0 Circuit Primary Outputs
Under
TPG 1 Test
Pass
BIST Mode ORA
Fail

Outline
 Introduction
 LAB1

Concluding Remarks
 Many new testing challenges presented by

– Increasing size and complexity of VLSI devices
– Decreasing feature size
 This chapter presented introduction to VLSI testing
 Remaining chapters present more details as well as solutions to
these challenges

Outline
 Introduction
 LAB1

LAB1
 LAB1 – An Verilog Example for Design Verification using

Functional Test
– Hardware: Personal-Computer (PC) only
– Software tools: ModelSim Simulator (Mentor), Xilinx ISE Synthesizer
– Language: Verilog HDL
– LAB1 download: http://soc.cs.nchu.edu.tw/pllai
 LAB goals:
– 撰寫基本可合成的 Verilog 設計程式
– 撰寫基本的 Testbench 測試程式
– 完成前置模擬
– 完成後置模擬
– 使用文字檔案作為待測電路的輸入
– 模擬結果輸出至文字檔案

Chapter 1 Introduction To VLSI Testing PDF

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Chapter 1 Introduction To VLSI Testing PDF

Uploaded by

Copyright:

Available Formats

VLSI TESTING

VLSI TESTING 2012 Chapter 1-1

 Introduce fundamental concepts and various aspects of VLSI

PING-LIANG LAI VLSI TESTING 2012 Chapter 1-2

PING-LIANG LAI VLSI TESTING 2012 Chapter 1-3

PING-LIANG LAI VLSI TESTING 2012 Chapter 1-4

 Moore’s Law results from decreasing feature size (dimensions)

PING-LIANG LAI VLSI TESTING 2012 Chapter 1-5

 Rule of Ten: cost to detect faulty IC increases by an order of

PING-LIANG LAI VLSI TESTING 2012 Chapter 1-6

PING-LIANG LAI VLSI TESTING 2012 Chapter 1-7

 Type of Application-Specific Integrated circuits (ASICs)

Building block Interconnection

PING-LIANG LAI VLSI TESTING 2012 Chapter 1-8

Full Custom Design Flow RTL-Level Sim

 Verification Testing (also called Design Verification)

PING-LIANG LAI VLSI TESTING 2012 Chapter 1-10

 Design Verification vs. Manufacturing Test

Specification Netlist Silicon

 How is Manufacturing Test performed?

Input patterns Output response

Stored golden response

 ATE carries out this process

PING-LIANG LAI VLSI TESTING 2012 Chapter 1-12

 Major ATE Companies: Agilent Technologies, Advantest, Credence

PING-LIANG LAI VLSI TESTING 2012 Chapter 1-13

PING-LIANG LAI VLSI TESTING 2012 Chapter 1-14

PING-LIANG LAI VLSI TESTING 2012 Chapter 1-15

 Exponential cost decrease – technology basically the same

Packaging process dies along the edge

AMD K8, source: http://www.amd.com

PING-LIANG LAI VLSI TESTING 2012 Chapter 1-16

PING-LIANG LAI VLSI TESTING 2012 Chapter 1-17

PING-LIANG LAI VLSI TESTING 2012 Chapter 1-19

 Testing typically consists of (three parts)

PING-LIANG LAI VLSI TESTING 2012 Chapter 1-20

 Design Verification targets Design Specification

PING-LIANG LAI VLSI TESTING 2012 Chapter 1-21

 Different levels of abstraction during Design Specification

Physical (Transistor) Level

PING-LIANG LAI VLSI TESTING 2012 Chapter 1-22

 We expect faulty chips due to manufacturing defects

 2 types of yield loss

PING-LIANG LAI VLSI TESTING 2012 Chapter 1-23

 A system consists of PCBs that PCB Fabrication Bare Board Test

 Assembly steps also susceptible

PING-LIANG LAI VLSI TESTING 2012 Chapter 1-24

PING-LIANG LAI VLSI TESTING 2012 Chapter 1-25

 Repair time (R) also assumed to obey

 Fraction of time that system is operating

PING-LIANG LAI VLSI TESTING 2012 Chapter 1-26

 Testing required to ensure system availability

PING-LIANG LAI VLSI TESTING 2012 Chapter 1-27

PING-LIANG LAI VLSI TESTING 2012 Chapter 1-28

 A test is a sequence of test patterns, called test vectors, applied to

PING-LIANG LAI VLSI TESTING 2012 Chapter 1-30

 Fault coverage for a given set of test vectors

number of detected faults

 100% fault coverage may be impossible due to undetectable faults

 Reject rate = 1 – yield (1 – fault coverage)

number of detected faults

PING-LIANG LAI VLSI TESTING 2012 Chapter 1-31

PING-LIANG LAI VLSI TESTING 2012 Chapter 1-32