Ch.07 Ref: Logic and Computer Design Fundamental By M. Morris Mano, Charles R.

Kime Page 1/21

Chapter 7 Registers and Register Transfer

Outline: - More structure, with multiple stages or cells that are identical or
close to identical circuits are considered.
- Registers are particular useful for storing information during the
processing of data.
- Counters assist us in sequencing the processing.
- Register transfer notation (microoperations)

7-1) Registers and Load Enable

4-Bit Register

June 04 Lecture note for ENE 431 By Dejwoot KHAWPARISUTH

Ch.07 Ref: Logic and Computer Design Fundamental By M. Morris Mano, Charles R. Kime Page 2/21

- Register with Parallel Load

4-Bit Register with Parallel Load

7-2) Registers Transfers

Digital systems are designed using a modular, hierarchical

approach. In most digital system designs, we partition the system into two
types of modules:
- a datapath: A datapath consists of processing logic and a collection
of registers that performs data processing
- a control unit: A control unit is made up of logic that determines the
sequence of data-processing operations performed by the datapath

June 04 Lecture note for ENE 431 By Dejwoot KHAWPARISUTH

Ch.07 Ref: Logic and Computer Design Fundamental By M. Morris Mano, Charles R. Kime Page 3/21

The movement of the data stored in registers and the processing

performed on the data are referred to as register transfer operations.
The register transfer operations of digital systems are specified by the
following three basic components:
1. the set of registers in the system
2. the operations that are performed on the data stored in the
registers, and
3. The control that supervised the sequence of operations in the
system.
The elementary operations performed on the data stored in registers
are called microoperations. (Ex: load, count, add, subtract, shift, etc.) A
counter with parallel load is able to perform two microoperations: increment
and load.

Interaction between Datapath and Control Unit

7-3) Registers Transfers Operations

June 04 Lecture note for ENE 431 By Dejwoot KHAWPARISUTH

Ch.07 Ref: Logic and Computer Design Fundamental By M. Morris Mano, Charles R. Kime Page 4/21

K1 : R 2 ← R1

Transfer from R1 to R2 when K1 = 1

K 2 : R 2 ← R1, R1 ← R 2 ; Exchange

7-4) A Note for VHDL and Verilog Users

June 04 Lecture note for ENE 431 By Dejwoot KHAWPARISUTH

Ch.07 Ref: Logic and Computer Design Fundamental By M. Morris Mano, Charles R. Kime Page 5/21

7-5) Microoperations
Microoperation is an elementary operation performed on data stored in
registers or memory.

- Transfer Microoperations
- Arithmetic Microoperations

X K1 : R1 ← R1 + R 2

XK1 : R1 ← R1 + R 2 + 1
Note: (
X K1 + XK1 = X + X K1 = K1 )

Implementation of Add and Subtract Microoperations

June 04 Lecture note for ENE 431 By Dejwoot KHAWPARISUTH

Ch.07 Ref: Logic and Computer Design Fundamental By M. Morris Mano, Charles R. Kime Page 6/21

- Logic Microoperations

- The AND microoperations can be used for clearing one or more bits
in a register to 0
10101101 10101011 R1 (data)
00000000 10101011 R2 (mask)
00000000 10101011 R1 ← R1 ∧ R 2

- The OR microoperations is used to set one or more bits in a

register.
10101101 10101011 R1 (data)
11111111 10101011 R2 (mask)
11111111 10101011 R1 ← R1 ∨ R 2

- The XOR microoperations can be used to complement one or more

bits in a register.
10101101 10101011 R1 (data)
11111111 00000000 R2 (mask)
01010010 10101011 R1 ← R1 ⊕ R 2

June 04 Lecture note for ENE 431 By Dejwoot KHAWPARISUTH

Ch.07 Ref: Logic and Computer Design Fundamental By M. Morris Mano, Charles R. Kime Page 7/21

- Shift Microoperations

7-6) Microoperations on a Single Register

- Multiplexer-Based Transfers
If (K = 1) then (R0 ← R1) else if (K
1 2 = 1) then (R0 ← R 2)
K1 : R 0 ← R1

K1 K 2 : R 0 ← R 2

Use of Multiplexers to Select between Two Registers

June 04 Lecture note for ENE 431 By Dejwoot KHAWPARISUTH

Ch.07 Ref: Logic and Computer Design Fundamental By M. Morris Mano, Charles R. Kime Page 8/21

Generalization of Multiplexer Selection for n Sources

- Shift Registers

4-Bit Shift Register

June 04 Lecture note for ENE 431 By Dejwoot KHAWPARISUTH

Ch.07 Ref: Logic and Computer Design Fundamental By M. Morris Mano, Charles R. Kime Page 9/21

Shift Register with Parallel Load

Shift : Q ← slQ
Shift ⋅ Load : Q ← D

June 04 Lecture note for ENE 431 By Dejwoot KHAWPARISUTH

Ch.07 Ref: Logic and Computer Design Fundamental By M. Morris Mano, Charles R. Kime Page 10/21

- Bidirectional Shift Register

Bidirectional Shift Register with Parallel Load

S1 ⋅ S 0 : Q ← slQ
S1 ⋅ S 0 : Q ← srQ
S1 ⋅ S 0 : Q ← D

June 04 Lecture note for ENE 431 By Dejwoot KHAWPARISUTH

Ch.07 Ref: Logic and Computer Design Fundamental By M. Morris Mano, Charles R. Kime Page 11/21

- Ripple Counter

4-Bit Ripple Counter

June 04 Lecture note for ENE 431 By Dejwoot KHAWPARISUTH

Ch.07 Ref: Logic and Computer Design Fundamental By M. Morris Mano, Charles R. Kime Page 12/21

- Synchronous Binary Counter

4-Bit Synchronous Binary Counter

- Serial and Parallel Counters

- Up-Down Binary Counters
A 4-bit up-down binary counter
D A0 = Q0 ⊕ EN

D A1 = Q1 ⊕ ((Q0 ⋅ S + Q0 ⋅ S ) ⋅ EN )

D A 2 = Q2 ⊕ ((Q0 ⋅ Q1 ⋅ S + Q0 ⋅ Q1 ⋅ S ) ⋅ EN )

D A3 = Q3 ⊕ ((Q0 ⋅ Q1 ⋅ Q2 ⋅ S + Q0 ⋅ Q1 ⋅ Q2 ⋅ S ) ⋅ EN )

June 04 Lecture note for ENE 431 By Dejwoot KHAWPARISUTH

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- Binary Counters with Parallel Load

4-Bit Binary Counters with Parallel Load

- Other Counters
- BCD Counter

June 04 Lecture note for ENE 431 By Dejwoot KHAWPARISUTH

Ch.07 Ref: Logic and Computer Design Fundamental By M. Morris Mano, Charles R. Kime Page 14/21

- Arbitrary Count sequence

Counter with Arbitrary Count

June 04 Lecture note for ENE 431 By Dejwoot KHAWPARISUTH

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7-7) Register Cell Design

Example: [7-1] Register Cell Design
Register A is to implement the following register transfer
AND: A ← A ∧ B
EXOR: A ← A ⊕ B
OR: A ← A ∨ B

( )
Di = A(t + 1) = AND ⋅ Ai ⋅ Bi + EXOR ⋅ Ai Bi + Ai Bi + OR ⋅ ( Ai + Bi ) + AND ⋅ EXOR ⋅ OR ⋅ Ai

Logic Diagram – Register Cell Design

June 04 Lecture note for ENE 431 By Dejwoot KHAWPARISUTH

Ch.07 Ref: Logic and Computer Design Fundamental By M. Morris Mano, Charles R. Kime Page 16/21

Example: [7-2] Register Cell Design

Register A is to implement the following register transfer
SHL: A ← slA
EXOR: A ← A ⊕ B
ADD: A ← A + B

Logic Diagram – Register Cell Design

June 04 Lecture note for ENE 431 By Dejwoot KHAWPARISUTH

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7-8) Multiplexer and Bus-Based Transfers for Multiple Registers

- Three Stage Bus: In a multiplexer, a large number of sources means a

high fan-in OR, which requires multiple levels of OR gates, introducing
more logic and increasing delay. In contrast, three-state buffers provide
a practical way to construct fast buses with many sources.

June 04 Lecture note for ENE 431 By Dejwoot KHAWPARISUTH

Ch.07 Ref: Logic and Computer Design Fundamental By M. Morris Mano, Charles R. Kime Page 18/21

- Memory Transfer
Read: DR ← M [ AR]
Write: M [ AR] ← DR

7-9) Serial Transfer and Microoperations

Serial Transfer

June 04 Lecture note for ENE 431 By Dejwoot KHAWPARISUTH

Ch.07 Ref: Logic and Computer Design Fundamental By M. Morris Mano, Charles R. Kime Page 19/21

- Serial Addition

7-10) HDL Representation for Shift Registers and Counters – VHDL

Example: [7-3] VHDL for a 4-Bit Shift Register

June 04 Lecture note for ENE 431 By Dejwoot KHAWPARISUTH

Ch.07 Ref: Logic and Computer Design Fundamental By M. Morris Mano, Charles R. Kime Page 20/21

Example: [7-4] VHDL for a 4-Bit Counter

June 04 Lecture note for ENE 431 By Dejwoot KHAWPARISUTH

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7-11) HDL Representation for Shift Registers and Counters - Verilog

Example: [7-5] Verilog for a 4-Bit Shift Register

Example: [7-6] Verilog for a 4-Bit Counter

June 04 Lecture note for ENE 431 By Dejwoot KHAWPARISUTH