LEVENTM CONFIDENTIAL

Mayuri Dhone

Contact No: 9175129973

Career Objective: To work in an organization where I can use my skills and knowledge to deliver
value added results that provides me job satisfaction and self development which help me achieve
personal as well as organizational goals.

VLSI Domain Skills

Programming Languages: Verilog, System Verilog (SV)

Verification Methodologies: Universal Verification Methodology (UVM).

EDA Tools : ISE-Xilinix-14.7, Questa sim, EDA Playground.

Domain : ASIC/FPGA Design Flow, Front-end Design and Verification.
Knowledge : RTL Coding, Functional & Code Coverage

Experience: 2.5 years of experience in Digital design and Verification. Working as an Engineer in
Design and Verification team.

Core Competency :
 Knowledge of Digital Logic Design.
 Knowledge of ASIC Design flow.
 RTL Verification using Verilog, System Verilog, UVM
 Concepts of OOPS Inheritance, Polymorphism and Encapsulation.
 Code Coverage, Functional Coverage and assertions.
 Coverage based verification, random stimulus generation for different test cases.

Projects worked:

www.leventm.com 1
 LEVENTM CONFIDENTIAL

RISC V based UART IP verification using UVM – Verification

Tools used : Questa Sim.

Description: This project idea is to offer a synthesizable SoC which can be uploaded to every FPGA and
be compatible with every FPGA board without the requirement of changing its code.

Responsibilities:
Good understanding of the specification.
Listing down features and creating test plan for these.

Development of AXI based verification using system verilog –

Tools used: Questa sim

Description: The whole verification process is carried out using the system verilog based modeling
approach. The AXI verification scenario includes the Read and Write transaction phases. The functional
verification of the AXI is carried out using Mentor Graphics Questa- sim .

Responsibilities:
Architected the design. Implemented RTL using Verilog HDL.
Architected the class-based verification environment using SystemVerilog.
Verified the RTL model using System Verilog.

Development of APB protocol Using System verilog:

Description: The Advanced Peripheral Bus (APB) VIP is unpipelined protocol has been developed to
interfaces with any peripherals that are low-bandwidth and to provide access to the programmable
control
registers of peripheral devices. It has One Master (APB Bridge) and one slave. I was involved in
development of driver, monitor, scoreboard, and APB VIP components.

www.leventm.com 2
 LEVENTM CONFIDENTIAL

Tool Used: Questa sim

Responsibilities:
Understanding the Specification.
Extracted features from Design specification and Created Test Plan.

Educational Details

B.E. in Electronics and Telecomm Rashtrasant Tukdoji Maharaj University 2016

(RTMNU). Percentage -73.3%

H.S.C Yugantar junior college – 71.83% 2012

S.S.C from Kale Ashirwad high School Percentage – 89.09% 2010

Extra-Curricular Activities:

Worked as VOLUNTEER in EVENTS dept. for TECH SAGA 2015, National level Tech Fest in ACET Nagpur
held during 2015.
Participated in cultural program dept for Celestial 2016 in ACET Nagpur.

www.leventm.com 3