Low Power/Energy BIST Scheme for Datapaths
'*,=2328/26 1.5$1,7,6  
$3$6&+$/,6
 
Department of Informatics, University of Piraeus, Greece
dgizop@unipi.gr
 
Department of Informatics, University of Athens, Greece
paschali@di.uoa.gr
Abstract
Power in processing cores (microprocessors, DSPs) is
primarily consumed in the functional modules of the
datapath. Among these modules, multipliers consume
the largest amount of power due to their size and
complexity. We propose low power BIST schemes for
datapath architectures built around multiplier-
accumulator pairs, based on deterministic test
patterns. Two alternatives are proposed depending on
whether the target is low energy dissipation during a
BIST session or low power dissipation (i.e. average
energy dissipation between successive test vectors).
The proposed BIST schemes are more efficient than
pseudorandom BIST for the same high fault coverage
target. Up to 78.33% energy saving is achieved by the
proposed low energy BIST scheme and up to 82.22%
power saving is achieved by the proposed low power
BIST scheme, compared with pseudorandom BIST.
1 Introduction
Power/energy consumption has recently become a
serious consideration in IC design and testing. Low
power/energy consumption is very important in
battery-operated systems since a careful design
strategy in terms of power consumption may prolong
the life of the batteries and increase the length of the
operating periods of the system. The rapidly increasing
number of such portable, battery-operated systems
(cellular phones, laptops, etc) makes their overall
power consumption a serious environmental
consideration. Excessive power consumption may
require expensive packages and cooling mechanisms,
thus increasing the overall system cost [1].
Circuit activity that leads to power consumption in
CMOS circuits is significantly higher during test or
self-test intervals. It has been shown in [2] that the
power consumption of VLSI devices during testing can
be as high as 200% of the power consumption in
normal mode and that input distributions during
normal mode cannot be a guideline for low power
consumption during testing. Increased power
consumption during testing is a key factor that must be
0-7695-0613-5/00 $10.00 ã 2000 I
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036$5$.,6 <=25,$1
II&T, NCSR “Demokritos”, Athens, Greece
{nkran | mpsarak}@iit.demokritos.gr
LogicVision, San Jose, CA, USA
zorian@logicvision.com
taken under consideration in test development for
complex VLSI devices.
In Built-In Self-Test (BIST) a large number of
uncorrelated test vectors are applied to the circuit
causing a significantly higher circuit activity compared
to circuit activity during normal mode of operation. In
current System-on-Chip designs many IP (intellectual
property) cores are tested in parallel within the same
BIST session causing even higher circuit activity.
Increased circuit activity and thus power/energy
consumption leads to increased current flows during
testing making the use of expensive packages for the
removal of excessive heat an imperative need. High
power dissipation and thus increased heat leads also to
serious silicon failure mechanisms (such as
electromigration [3]) that reduce the reliability of a
system operating under such conditions.
In battery-operated systems periodic self-tests
consume large amounts of battery power compared to
standby mode [4]. The life of a battery is thus
significantly affected by the power consumption
during self-test intervals. In today’s small-sized, low
power, low cost, portable applications there is no
possibility of providing special heat removal
equipment or expensive packages. The straightforward
solution of reducing the frequency of the system
during test mode for power consumption reduction can
not be applied in chip manufacturing test since ICs
must be tested at the actual speed (at-speed testing) for
the detection of the physical failure mechanisms of
today’s deep submicron technologies [4].
In most complex SoC designs characterized by very
poor controllability and observability, BIST is
probably the only practical solution for efficient
testing. Energy and power consumption for such
systems is a key issue during the development of
efficient BIST architectures.
The reduction of power consumption during BIST has
been considered in [2], [5] with the main target of
reducing the number of concurrently tested modules.
This approach leads to reduction of the average power
consumption by increasing the test sessions lengths.
Another approach presented in [6], proposes a new
LFSR-based TPG which reduces power consumption
by reducing the transition densities of test vectors
generated by a slow LFSR.
Three methods for low power BIST have been
proposed in [4], [7] and [8]. In [4], [7] low power
consumption is achieved by masking the application of
non-detecting vectors generated by pseudorandom
TPGs (LFSRs). Special care is taken for the low power
design of the vector masking control logic. In [8], a
modified scan cell design is proposed so that circuit
inputs are not affected when shifting of test vectors
takes place in scan based BIST architectures.
In this work, we focus on low energy and low power
BIST methodologies for the central operating part of
the processing elements i.e. the datapath. In such
modules which are in most cases used in SoC designs
power is consumed in the datapath functional modules.
We propose a deterministic BIST TPG approach for
multiplier-accumulator pairs which is proved to be
much more efficient compared to pseudorandom BIST
in terms of power/energy consumption.
We propose two different BIST architectures. The first
one is based on a very compact test set generated by a
fixed size counter-based TPG. The test set is a
significant low energy oriented enhancement of a very
efficient BIST test set presented in the past by the
authors in [9], [10]. The original test set of [9], [10] is
reduced in less than a half of its size and also modified
to produce very low circuit input activity. This way the
total energy consumption during the BIST session is
much lower than any of the compared schemes with
fault coverage targets of more than 99% and with a
very small hardware overhead. This first architecture is
clearly very efficient for portable applications when
the energy consumed from batteries must be minimum.
The second architecture is based on a linear-sized test
set. The benefit of this architecture is a very large
reduction in the average power consumption per vector
pair compared to other schemes. This architecture is
clearly useful when the low average power
consumption is the key issue for the reduction of costs
related to packaging and cooling equipment.
In the comprehensive set of simulations performed to
justify the effectiveness of the proposed architecture
we investigate various implementations of the datapath
functional modules (standard carry-save array
multiplier, Booth encoded Wallace tree multiplier,
ripple-carry adder, carry lookahead adder, Brent-Kung
adder) and we compare the proposed architecture with
other pseudorandom or deterministic alternatives over
which it is proved to be much more efficient.
2 Power Dissipation Preliminaries
In digital CMOS technology power dissipation is
either static or dynamic. Leakage currents is the
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primary cause for static power dissipation which
contributes very slightly in the overall power
dissipation. The dominant factor in power dissipation
is dynamic power [1] which is consumed when nodes
switch from 0 to 1 or from 1 to 0. When such
switching activity takes place power is consumed due
to short circuit current flows and the charging and
discharging of load capacitances.
The energy consumed in a circuit node over a period of
time is estimated by the formula [12], [13]:
Ei = ½ Vdd2 c0 Fi Si
Where Vdd is the power supply voltage, c0 is the
minimum output load capacitance, Fi is the fanout of
the node (when a node is connected to more than one
gate inputs, its capacitance is proportional to the fanout
of the node [13]) and Si is the number of node
switchings over the period of time. The sum of the
energy consumption for all circuit nodes Ei gives the
total energy consumed over a period of time.
The average power consumed in a circuit node is
estimated by the formula:
Pi = ½ Vdd2 c0 Fi S’i f
Where S’i is the average number of node switchings
per clock period and f is the circuit clock frequency.
The sum of the average power consumption for all
circuit nodes Pi gives the total power consumed over a
clock period.
The variable part in the above formulas is the product
Fi Si (or Fi S’i) which is termed the Weighted
Switching Activity (WSA) and used as a metric for the
evaluation of the power consumption of the circuit.
Custom tools are usually developed for the fast
evaluation of power consumption via WSA calculation
[4], [7], [14].
Low power test and self-test methodologies have
usually two targets. The first target is the minimization
of the average power consumption between successive
test vectors so that the thermal capacity of the IC is not
exceeded. Heat dissipation can exceed the thermal
capacity only for a few vector pairs without damaging
the device but the average heat dissipation for a
sequence of vectors must clearly be below this limit
[15]. The second target is the total energy consumed
over a period of time (a self-test session for example)
which is important for the life of a battery in a portable
or wireless application.
Energy and power dissipation evaluations depend on
the delay model assumptions for the circuit under test
[15]. The zero delay model is commonly used by test
generators and fault simulators. It has been observed in
[16] that the results obtained by the zero delay model
are correlated with the results obtained by the general
delay model with exact gate delays.
In this paper we calculate power dissipation using a
commercial power analysis tool, DesignPower™
provided by Synopsys [17] which analyzes power
of the gate-level design and computes average power
consumption based on nets activity. During power
analysis, DesignPower uses switching activity back-
annotated on the design from register transfer level
(RTL) or gate-level simulations. We used the most
accurate delay model for the gate-level simulations.
It is important to note at this point that the above
discussion is an approximation of the power
consumption mechanisms in CMOS. Other factors
play important roles like wiring capacitances in deep
submicron which are more critical than node fanouts.
The common basis in all cases is that switching
activity reduction leads to power/energy reduction.
Thus, switching activity reduction achieved by the
proposed methodologies can be applied in different
technologies since in any case switching activity is
crusial. The experimental results of this paper are
provided by an accurate commercial toolset that
considers node and wiring capacitances and are
therefore highly reliable.
3 Datapath Built-In Self-Test
The most difficult testability problems in datapaths
appear in their functional modules. Additionally, these
modules consume the vast amount of the total circuit
energy/power. For these reasons we concentrate this
work in the development of low power BIST
architectures for the most common combination of
functional modules which is the multiplier-
accumulator pair. The results presented in detail in the
rest of the paper deal with various architectures of the
pair. The multiplier-adder pair is shown in Figure 1. In
this pair we assume that the width of the adder is
double than the width of the multiplier so that the
entire multiplication product can be accumulated.
UH
 G
5 G
$ binary counter into a Gray counter that generates only
0XOWLSOLHU
 first architecture is the utilization of 2 modified 4-bit
5
Figure 1: Multiplier-adder pair
In pseudorandom BIST a large number of test patterns
are generated by a pseudorandom generator like a
Linear Feedback Shift Register (LFSR) or a Cellular
Automaton. Output Data Evaluation is performed by
Multiple Input Shift Register (MISR). Another
excellent alternative in pseudorandom BIST for
datapath architectures is Arithmetic BIST [18]. In this
scheme, pseudorandom tests are generated and
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responses compacted by arithmetic modules. ABIST
efficiency was proved equal to LFSR testing while it
imposes near zero hardware overhead since BIST is
performed by pre-existing modules of the datapath.
Deterministic BIST for datapath architectures has been
proposed [19]. The generation of deterministic test set
is performed by fixed length count-based machines or
by slight modifications of the input registers. Response
compaction is performed by existing arithmetic
modules like adders or subtractors. The efficiency of
the BIST architecture is the same in any datapath
width or any implementation of the functional
modules. We propose modifications on the datapath
BIST architecture of [19] with the target of low
energy/power consumption during BIST.
4 Proposed Low Energy/Power
Datapath BIST Architectures
The efficiency of deterministic repetitive test vectors
in BIST for multiplier units, ALUs and datapaths in
general was shown in [9], [10], [11], [19], [20] for
combinational and sequential faults. In these BIST
architectures test vectors are generated by small fixed
or linear size counter-based TPGs or by small
modifications of the input registers. In this paper we
apply deterministic repetitive test vectors with the
primary goal of reducing the energy and power
consumed in BIST sessions while retaining the same
high fault coverage for any datapath width.
4.1 Low Energy BIST Scheme
In the multiplier-accumulator pair, the original scheme
proposed in [9], [10] applies 256 (or 225) test vectors
generated by an 8-bit counter. This scheme provides
for any multiplier architecture a fault coverage >99%
for any datapath width and for any gate-level
implementation of the multiplier and adder cells.
In the first of the proposed BIST schemes we set the
goal to retain the very high fault coverage and propose
modifications that reduce the energy dissipation during
the entire BIST session. The simple first step in
 reducing power/energy is the modification of the 8-bit
5
one output transition at a time. The contribution of the
Gray counters that go through only 10 of the 16 states:
+(;$'(&,0$/ %,1$5<
1 Hex 0001 Bin
3 Hex 0011 Bin
7 Hex 0111 Bin
6 Hex 0110 Bin
E Hex 1110 Bin
C Hex 1100 Bin
8 Hex 1000 Bin
A Hex 1010 Bin
B Hex 1011 Bin
9 Hex 1001 Bin
The original number of 256 tests (already reduced in ;23(5$1' <23(5$1' ;23(5$1' <23(5$1'
[19] in 225) is now reduced in only 100 test vectors
(10 x 10) which is the smallest regular subset of the 11…1 11…1 EE…E 11…1
original test set that can provide the target very high 11…1 33…3 … …
fault coverage (>99%). This result comes from 11…1 77…7 EE…E 99…9
monitoring the detection capabilities of the original
11…1 66…6 CC…C 99…9
256 test vector (some of these test vectors are not
necessary for achieving high fault coverage) and also 11…1 EE…E … …
keeping BIST Test Pattern Generation regularity in 11…1 CC…C CC…C 11…1
mind. 11…1 88…8 88…8 11…1
The total BIST session duration is less than half the 11…1 AA…A … …
duration of the original architecture and thus the total 11…1 BB…B 88…8 99…9
energy dissipation is significantly reduced as we will
11…1 99…9 AA…A 99…9
see in the experimental results session.
33…3 99…9 … …
The low energy BIST TPG shown in Figure 2 is based
on the use of two 4-bit modified Gray counters, i.e. 33…3 BB…B AA…A 11…1
counters that generate a subset of the 4-bit Gray … … BB…B 11…1
sequence. 33…3 33…3 … …
Each counter applies 4-bit repetitive patterns to one of 33…3 11…1 BB…B 99…9
the two multiplier operands. The counter that applies
77…7 11…1 99…9 99…9
patterns to the Y operand can count both directions (up
and down). The overall sequence generated by the … … … …
TPG of Figure 2 consists of 100 test vectors which are 77…7 99…9 99…9 11…1
sufficient to provide a very high fault coverage with a 66…6 99…9
very small energy consumption.
… …
4-bit '8 4-bit
66…6 11…1
(1
Modified Gray (1 Modified Gray
&/. 4>@ &/. 4>@
FON FON
The proposed low energy BIST scheme has a very
high fault detection capability, since it applies 4-bit
'HF 'HF repetitive patterns as in the original scheme. The large
reduction in energy consumption is due to:
 • the use of only 100 out of the 256 4-bit repetitive
patterns, thus reducing the test application time in
4 (1 4 (1
less than one half of the original and
FON FON

4¶
&/.

4¶
&/.
• applying 4-bit patterns with only one bit change
' '
for each 4-bits group, thus reducing the switching
activity that leads to energy consumption

;>@ <>@
4.2 Low Power BIST Scheme
In the second BIST scheme, the target is the lowest
Figure 2: Low energy TPG possible average energy consumption, i.e. the lowest
power consumption between successive test vectors
The two blocks “Dec 0001” and “Dec 1001” applied during the BIST session.
decode the values of vectors 0001 and 1001 To achieve this target we propose a BIST scheme that
respectively in the output of the right counter. generates Single Input Changes (SIC) in successive
These blocks in combination with a D flip-flop BIST test vectors. The application of SIC pairs leads to
determine the right counter direction. A second flip- low circuit input activity, i.e. low power consumption.
flop (the left one) is used to enable or disable both 4- In this architecture the test application time is not
bit counters. constant as in the case of the low energy BIST scheme
(100 tests), but it grows linearly with the size of the
The 100 test vectors sequence generated by the TPG of datapath.
Figure 2 is in hexadecimal:

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 &/.

(1
8-bit
Gray Counter
micron double-metal 5V CMOS standard cell library
4>@ 4>@ provided by AMS. The circuit frequency was 10 MHz.
&/.
Enable Generator We used 2 multiplier architectures: (i) a standard
((((((((

carry-save multiplier (CSA) and (ii) a Booth encoded

tree (Wallace) multiplier (BWM). We used 3 adder
architectures for the accumulator: (i) a simple low cost
(1

&/.
'>@

4>@
(1

&/.
'>@

4>@
(1

&/.
'>@

4>@
(1

&/.
'>@

4>@
(1

&/.
'>@

4>@
(1

&/.
'>@

4>@
(1

&/.
'>@

4>@
(1

&/.
'>@

4>@
ripple carry adder (RPL), (ii) a carry lookahead adder
(CLA) and (iii) a Brent-Kung adder (BKA) [22]
;>@ <>@

&ON 73* 08/7 $'' )& +: 32 (1

%,1 &6$ 53/ 100.0 5.15 15.29 391.4
(
*5$< &6$ 53/ 100.0 5.69 11.74 300.5
( /)65 &6$ 53/ 100.0 6.92 19.37 495.9
( *5$< &6$ 53/ 99.8 6.40 13.26 132.6
/,1($5 &6$ 53/ 100.0 10.74 4.84 991.2
(
%,1 &6$ &/$ 99.9 4.87 16.14 413.8
( *5$< &6$ &/$ 100.0 5.54 12.15 311.0
( /)65 &6$ &/$ 100.0 6.75 19.86 508.4
*5$< &6$ &/$ 99.7 6.23 13.78 137.8
(
/,1($5 &6$ &/$ 100.0 10.47 5.06 1036.3
( %,1 &6$ %.$ 99.9 5.13 15.24 390.1
*5$< &6$ %.$ 99.9 5.66 11.69 299.3
Figure 3: Low power TPG
/)65 &6$ %.$ 99.8 6.91 19.31 494.3
According to this scheme only one bit changes in the *5$< &6$ %.$ 99.7 6.37 13.21 132.1
entire operands of the multiplier, and instead of /,1($5 &6$ %.$ 100.0 10.70 4.85 993.3
applying one change per 4-bits we apply one change %,1 %:0 53/ 99.9 5.83 12.43 318.2
per entire operand. The overall test set size in this *5$< %:0 53/ 99.9 6.46 9.79 250.6
scheme is 256(N/2), where N is the datapath width. /)65 %:0 53/ 100.0 7.84 18.13 464.0
The TPG for this scheme is depicted in Figure 3. *5$< %:0 53/ 99.4 7.33 10.07 100.7
An 8-bit Gray counter is employed in this scheme that /,1($5 %:0 53/ 99.9 12.15 4.14 847.9
generates a new value when the previous one has been %,1 %:0 &/$ 99.9 5.64 13.02 333.3
loaded in the entire multiplier operands. During each *5$< %:0 &/$ 99.9 6.25 10.26 262.7
clock cycle a 4-bit part of the multiplier operands is /)65 %:0 &/$ 100.0 7.58 18.71 479.0
loaded with a counter output (the 4 low order bits are *5$< %:0 &/$ 99.4 7.08 10.56 105.6
loaded to the Y operand while the 4 high order bits are /,1($5 %:0 &/$ 100.0 11.75 4.35 890.9
loaded to the X operand). In the TPG architecture %,1 %:0 %.$ 99.9 5.76 12.47 319.2
depicted in Figure 3, the Enable Generator block *5$< %:0 %.$ 99.9 6.41 9.78 250.4
generates a set of enable signals, (waveforms are also /)65 %:0 %.$ 100.0 7.78 18.15 464.7
shown) that determine the loading of the 4-bit patterns *5$< %:0 %.$ 99.3 7.25 10.07 100.7
in the operand registers. /,1($5 %:0 %.$ 100.0 12.05 4.13 845.8

The configuration of Figure 3 (4-bit groups for both X Table 1: Experimental results with accumulator
and Y) is used in the carry-save and carry-propagate
multipliers while in the case of Booth encoded Wallace The BIST TPG schemes compared are: (i) the original
multiplier X receives 3-bit repetitive patterns and Y 8-bit binary counter (BIN256), (ii) the straightforward
operand 5-bit ones (see [21]). 8-bit Gray counter (GRAY256), (iii) the LFSR-based
Input switching activity is minimized in the proposed pseudorandom TPG (LFSR256) for a total of 256
scheme. The overall test application time is increased random test vectors, (iv) the low energy BIST scheme
due to the linear test set with the benefit of very small of Figure 2 (GRAY100) and (v) the low power BIST
power consumption between successive test vectors. scheme of Figure 3 (LINEAR)
5 Experimental Results - Comparisons We have also performed a set of experiments in the
We have implemented various 16-bit architectures for case that the original datapath does not contain an
the multiplier-adder scheme with many TPG adder. In this case we have synthesized an extra MISR
alternatives. All designs were implemented using a 0.8 for output compaction.

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