SiHD5N50D

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Vishay Siliconix
D Series Power MOSFET
FEATURES
PRODUCT SUMMARY
• Optimal design
VDS (V) at TJ max. 550 - Low area specific on-resistance
RDS(on) max. () at 25 °C VGS = 10 V 1.5 - Low input capacitance (Ciss)
Qg max. (nC) 20 - Reduced capacitive switching losses
Qgs (nC) 3 - High body diode ruggedness
Available
Qgd (nC) 5 - Avalanche energy rated (UIS)
Configuration Single • Optimal efficiency and operation
- Low cost
D - Simple gate drive circuitry
- Low figure-of-merit (FOM): Ron x Qg
DPAK - Fast switching
(TO-252) • Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
D
G
APPLICATIONS
S • Consumer electronics
G
- Displays (LCD or plasma TV)
S
• Server and telecom power supplies
N-Channel MOSFET - SMPS
• Industrial
- Welding
- Induction heating
- Motor drives
• Battery chargers

ORDERING INFORMATION
Package DPAK (TO-252)
Lead (Pb)-free SiHD5N50D-E3
SiHD5N50D-GE3
SiHD5N50DT1-GE3
Lead (Pb)-free and Halogen-free
SiHD5N50DT4-GE3
SiHD5N50DT5-GE3

ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)

PARAMETER SYMBOL LIMIT UNIT
Drain-Source Voltage VDS 500
Gate-Source Voltage ± 30 V
VGS
Gate-Source Voltage AC (f > 1 Hz) 30
TC = 25 °C 5.3
Continuous Drain Current (TJ = 150 °C) VGS at 10 V ID
TC = 100 °C 3.4 A
Pulsed Drain Current a IDM 10
Linear Derating Factor 0.83 W/°C
Single Pulse Avalanche Energy b EAS 28.8 mJ
Maximum Power Dissipation PD 104 W
Operating Junction and Storage Temperature Range TJ, Tstg -55 to +150 °C
Drain-Source Voltage Slope TJ = 125 °C 24
dV/dt V/ns
Reverse Diode dV/dt d 0.28
Soldering Recommendations (Peak temperature) c for 10 s 300 °C
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature.
b. VDD = 50 V, starting TJ = 25 °C, L = 2.3 mH, Rg = 25 , IAS = 5 A.
c. 1.6 mm from case.
d. ISD  ID, starting TJ = 25 °C.

S16-0109-Rev. C, 25-Jan-16 1 Document Number: 91499

For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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THERMAL RESISTANCE RATINGS

PARAMETER SYMBOL TYP. MAX. UNIT
Maximum Junction-to-Ambient RthJA - 62
°C/W
Maximum Junction-to-Case (Drain) RthJC - 1.2

SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)

PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
Static
Drain-Source Breakdown Voltage VDS VGS = 0 V, ID = 250 μA 500 - - V
VDS Temperature Coefficient VDS/TJ Reference to 25 °C, ID = 250 μA - 0.58 - V/°C
Gate-Source Threshold Voltage (N) VGS(th) VDS = VGS, ID = 250 μA 3 - 5 V
Gate-Source Leakage IGSS VGS = ± 30 V - - ± 100 nA
VDS = 500 V, VGS = 0 V - - 1
Zero Gate Voltage Drain Current IDSS μA
VDS = 400 V, VGS = 0 V, TJ = 125 °C - - 10
Drain-Source On-State Resistance RDS(on) VGS = 10 V ID = 2.5 A - 1.2 1.5 
Forward Transconductance a gfs VDS = 20 V, ID = 2.5 A - 1.8 - S
Dynamic
Input Capacitance Ciss VGS = 0 V, - 325 -
Output Capacitance Coss VDS = 100 V, - 34 -
Reverse Transfer Capacitance Crss f = 1 MHz - 6 -
Effective Output Capacitance, Energy pF
Co(er) - 31 -
Related b
VDS = 0 V to 400 V, VGS = 0 V
Effective Output Capacitance, Time
Co(tr) - 41 -
Related c
Total Gate Charge Qg - 10 20
Gate-Source Charge Qgs VGS = 10 V ID = 2.5 A, VDS = 400 V - 3 - nC
Gate-Drain Charge Qgd - 5 -
Turn-On Delay Time td(on) - 12 24
Rise Time tr VDD = 400 V, ID = 2.5 A - 11 22
ns
Turn-Off Delay Time td(off) Rg = 9.1 , VGS = 10 V - 14 28
Fall Time tf - 11 22
Gate Input Resistance Rg f = 1 MHz, open drain - 1.7 - 
Drain-Source Body Diode Characteristics

Continuous Source-Drain Diode Current IS MOSFET symbol D

- - 5
showing the  A
integral reverse G

Pulsed Diode Forward Current ISM P - N junction diode S

- - 20

Diode Forward Voltage VSD TJ = 25 °C, IS = 4 A, VGS = 0 V - - 1.2 V

Reverse Recovery Time trr - 320 - ns
TJ = 25 °C, IF = IS = 2.5 A,
Reverse Recovery Charge Qrr - 1.2 - μC
dI/dt = 100 A/μs, VR = 20 V
Reverse Recovery Current IRRM - 8 - A
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature.
b. Coss(er) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 % to 80 % VDSS.
c. Coss(tr) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 % to 80 % VDSS.

S16-0109-Rev. C, 25-Jan-16 2 Document Number: 91499

For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

12 3
TOP 15 V TJ = 25 °C ID = 2.5 A
ID, Drain-to-Source Current (A)

14 V

On Resistance (Normalized)
13 V 2.5

RDS(on), Drain-to-Source
12 V
9 11 V
10 V
9V 2

6 1.5

8V 1 VGS = 10 V
3
7V 0.5
6V
0 0
0 5 10 15 20 25 30 - 60 - 40 - 20 0 20 40 60 80 100 120 140 160
VDS, Drain-to-Source Voltage (V) TJ, Junction Temperature (°C)

Fig. 1 - Typical Output Characteristics Fig. 4 - Normalized On-Resistance vs. Temperature

8 1000
TOP 15 V
14 V TJ = 150 °C
ID, Drain-to-Source Current (A)

13 V Ciss
12 V
6 11 V
VGS = 0 V, f = 1 MHz
Capacitance (pF)

10 V
9.0 V 100 Ciss = Cgs + Cgd, Cds Shorted
8.0 V Crss = Cgd
7.0 V
6.0 V Coss = Cds + Cgd
4 Coss
5.0 V

10
Crss
2

0 1
0 5 10 15 20 25 30 0 100 200 300 400 500
VDS, Drain-to-Source Voltage (V)
VDS, Drain-to-Source Voltage (V)

Fig. 2 - Typical Output Characteristics Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage

12 24
VDS = 400 V
VGS, Gate-to-Source Voltage (V)
ID, Drain-to-Source Current (A)

VDS = 250 V
20 VDS = 100 V
9
16

6 12

8
TJ = 150 °C
3
4
TJ = 25 °C

0 0
0 5 10 15 20 25 0 3 6 9 12 15 18
VGS, Gate-to-Source Voltage (V) Qg, Total Gate Charge (nC)

Fig. 3 - Typical Transfer Characteristics Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage

S16-0109-Rev. C, 25-Jan-16 3 Document Number: 91499

For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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Vishay Siliconix

100 6
ISD, Reverse Drain Current (A)

ID, Drain Current (A)

TJ = 150 °C
10 4

3
TJ = 25 °C
1 2

1
VGS = 0 V
0.1 0
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 25 50 75 100 125 150
VSD, Source-Drain Voltage (V) TJ, Case Temperature (°C)

Fig. 7 - Typical Source-Drain Diode Forward Voltage Fig. 9 - Maximum Drain Current vs. Case Temperature

100 625
Operation in this area
limited by RDS(on)
600
Breakdown Voltage (V)
VDS, Drain-to-Source
10
ID, Drain Current (A)

100 μs 575

1 550
Limited by RDS(on)* 1 ms

525
0.1 10 ms
TC = 25 °C
TJ = 150 °C 500
Single Pulse BVDSS Limited
0.01 475
1 10 100 1000 - 60 - 40 - 20 0 20 40 60 80 100 120 140 160
VDS, Drain-to-Source Voltage (V)
TJ, Junction Temperature (°C)
* VGS > minimum VGS at which RDS(on) is specified

Fig. 8 - Maximum Safe Operating Area Fig. 10 - Typical Drain-to-Source Voltage vs. Temperature

1
Normalized Effective Transient

Duty Cycle = 0.5

Thermal Impedance

0.2

0.1

0.1 0.05

0.02

Single Pulse

0.01
0.0001 0.001 0.01 0.1 1
Pulse Time (s)

Fig. 11 - Normalized Thermal Transient Impedance, Junction-to-Case

S16-0109-Rev. C, 25-Jan-16 4 Document Number: 91499

For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
 SiHD5N50D
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Vishay Siliconix

RD
VDS
QG
VGS 10 V
D.U.T.
RG QGS QGD
+
- VDD

10 V VG
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %

Charge
Fig. 12 - Switching Time Test Circuit
Fig. 16 - Basic Gate Charge Waveform

Current regulator
VDS Same type as D.U.T.

90 %
50 kΩ

12 V 0.2 µF
0.3 µF

+
10 % VDS
D.U.T. -
VGS
td(on) tr td(off) tf VGS

3 mA

Fig. 13 - Switching Time Waveforms

IG ID
Current sampling resistors

Fig. 17 - Gate Charge Test Circuit

L
VDS
Vary tp to obtain
required IAS

RG D.U.T +
V DD
-
IAS
10 V
tp 0.01 Ω

Fig. 14 - Unclamped Inductive Test Circuit

VDS
tp
VDD

VDS

IAS

Fig. 15 - Unclamped Inductive Waveforms

S16-0109-Rev. C, 25-Jan-16 5 Document Number: 91499

For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
 SiHD5N50D
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Vishay Siliconix

Peak Diode Recovery dV/dt Test Circuit

+ Circuit layout considerations

D.U.T.
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
-

- +
-

Rg • dV/dt controlled by Rg +
• Driver same type as D.U.T. VDD
-
• ISD controlled by duty factor “D”
• D.U.T. - device under test

Driver gate drive

Period P.W.
D=
P.W. Period

VGS = 10 Va

D.U.T. lSD waveform

Reverse
recovery Body diode forward
current current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
VDD

Re-applied
voltage
Body diode forward drop
Inductor current

Ripple ≤ 5 % ISD

Note
a. VGS = 5 V for logic level devices

Fig. 18 - For N-Channel

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Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91499.

S16-0109-Rev. C, 25-Jan-16 6 Document Number: 91499

For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
 Package Information
www.vishay.com
Vishay Siliconix
TO-252AA Case Outline
E A MILLIMETERS INCHES
C2
b3
DIM. MIN. MAX. MIN. MAX.
A 2.18 2.38 0.086 0.094

L3
A1 - 0.127 - 0.005
b 0.64 0.88 0.025 0.035
b2 0.76 1.14 0.030 0.045
D

b3 4.95 5.46 0.195 0.215

H
C 0.46 0.61 0.018 0.024
C2 0.46 0.89 0.018 0.035
L4

D 5.97 6.22 0.235 0.245

L5

L
gage plane height (0.5 mm)

D1 4.10 - 0.161 -
E 6.35 6.73 0.250 0.265
E1 4.32 - 0.170 -
b b2 C
e H 9.40 10.41 0.370 0.410
A1
e1 e 2.28 BSC 0.090 BSC
e1 4.56 BSC 0.180 BSC
L 1.40 1.78 0.055 0.070
L3 0.89 1.27 0.035 0.050
D1

L4 - 1.02 - 0.040
L5 1.01 1.52 0.040 0.060
ECN: T16-0236-Rev. P, 16-May-16
DWG: 5347
E1
Notes
• Dimension L3 is for reference only.

Revision: 16-May-16 1 Document Number: 71197

For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
 Application Note 826
Vishay Siliconix

RECOMMENDED MINIMUM PADS FOR DPAK (TO-252)

0.224
(5.690)

(6.180)
0.243
(10.668)
0.420

(2.202)
0.087
(2.286)
0.090

0.180 0.055
(4.572) (1.397)

Recommended Minimum Pads

Dimensions in Inches/(mm)

Return to Index Return to Index

APPLICATION NOTE

Document Number: 72594 www.vishay.com

Revision: 21-Jan-08 3
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Revision: 08-Feb-17 1 Document Number: 91000

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