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Vishay Siliconix
E Series Power MOSFET
FEATURES
PRODUCT SUMMARY
• Low figure-of-merit (FOM): Ron x Qg
VDS (V) at TJ max. 650
RDS(on) max. () at 25 °C VGS = 10 V 0.099 • Low input capacitance (Ciss)
Qg max. (nC) 150 • Reduced switching and conduction losses
Qgs (nC) 24 • Ultra low gate charge (Qg)
Available
Qgd (nC) 42 • Avalanche energy rated (UIS)
Configuration Single • Material categorization: for definitions of compliance
D
please see www.vishay.com/doc?99912
TO-247AC APPLICATIONS
• Server and telecom power supplies
• Switch mode power supplies (SMPS)
G • Power factor correction power supplies (PFC)
• Lighting
S
D - High-intensity discharge (HID)
G S
- Fluorescent ballast lighting
N-Channel MOSFET
• Industrial
- Welding
- Induction heating
- Motor drives
- Battery chargers
- Renewable energy
- Solar (PV inverters)
ORDERING INFORMATION
Package TO-247AC
Lead (Pb)-free SiHG33N60E-E3
Lead (Pb)-free and Halogen-free SiHG33N60E-GE3
RDS(on) - On-Resistance
ID - Drain Current (A)
9.0 V 2.0
80 8.0 V
(Normalized)
7.0 V
BOTTOM 6.0 V
60 1.5
40 1.0
20 0.5
VGS = 10 V
5.0 V
0 0.0
Fig. 1 - Typical Output Characteristics, TC = 150 °C Fig. 4 - Normalized On-Resistance vs. Temperature
70 100 000
TOP 15 V VGS = 0 V, f = 1 MHz
14 V TJ = 150 °C Ciss = Cgs + Cgd x Cds shorted
13 V
60 Crss = Cgd
12 V
11 V 10 000 Ciss Coss = Cds + Cgd
ID - Drain Current (A)
10 V
C - Capacitance (pF)
50
9.0 V
8.0 V
1000
40 7.0 V
BOTTOM 6.0 V
Coss
30 100
20
10
10 Crss
5.0 V
1
0
0 5 10 15 20 25 30 0 100 200 300 400 500 600
VDS - Drain-to-Source Voltage (V) VDS - Drain-to-Source Voltage (V)
Fig. 2 - Typical Output Characteristics, TC = 150 °C Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
120 25
100 5000
20
ID, Drain-to-Source Current (A)
80
15
Coss (pF)
Eoss (μJ)
Coss Eoss
60
500
10
40
TJ = 150 °C
5
20
TJ = 25 °C
0 50 0
0 5 10 15 20 25 0 100 200 300 400 500 600
VGS, Gate-to-Source Voltage (V) VDS
Fig. 3 - Typical Transfer Characteristics Fig. 6 - COSS and EOSS vs. VDS
24 35
VDS = 300 V
20 30
VGS - Gate-to-Source Voltage (V)
VDS = 120 V
25
VDS = 480 V 20
12
15
8
10
4
5
0 0
0 40 80 120 160 200 25 50 75 100 125 150
Qg - Total Gate Charge (nC) TC - Temperature (°C)
Fig. 7 - Typical Gate Charge vs. Gate-to-Source Voltage Fig. 10 - Maximum Drain Current vs. Case Temperature
1000 750
ġ
10
Voltage (V)
675
TJ = 25 °C
ġ 650
1
625
0.1
600
ġ
VGS = 0 V
0.01 575
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 -60 -40 -20 0 20 40 60 80 100 120 140 160
VSD - Source-to-Drain Voltage (V) TJ,Temperature (°C)
Fig. 8 - Typical Source-Drain Diode Forward Voltage Fig. 11 - Typical Drain-to-Source Voltage vs. Temperature
1000
1 ms
1
TC = 25 °C 10 ms
TJ = 150 °C
Single Pulse
BVDSS Limited
0.1
1 10 100 1000
VDS - Drain-to-Source Voltage (V)
* VGS > minimum VGS at which RDS(on) is specified
Fig. 9 - Maximum Safe Operating Area
0.2
0.1 0.1
0.05
0.02
Single Pulse
0.01
0.0001 0.001 0.01 0.1 1
RD VDS
VDS
tp
VGS VDD
D.U.T.
RG
+
- VDD
VDS
10 V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
IAS
VDS
QG
90 % 10 V
QGS QGD
10 % VG
VGS
td(on) tr td(off) tf
Charge
Fig. 14 - Switching Time Waveforms Fig. 17 - Basic Gate Charge Waveform
Current regulator
Same type as D.U.T.
L
VDS
50 kΩ
Vary tp to obtain
required IAS 12 V 0.2 µF
0.3 µF
RG D.U.T + +
V DD VDS
D.U.T. -
-
IAS
VGS
10 V
tp 0.01 Ω 3 mA
IG ID
Current sampling resistors
Fig. 15 - Unclamped Inductive Test Circuit Fig. 18 - Gate Charge Test Circuit
- +
-
Rg • dV/dt controlled by Rg +
• Driver same type as D.U.T. VDD
-
• ISD controlled by duty factor “D”
• D.U.T. - device under test
VGS = 10 Va
Reverse
recovery Body diode forward
current current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
VDD
Re-applied
voltage
Body diode forward drop
Inductor current
Ripple ≤ 5 % ISD
Note
a. VGS = 5 V for logic level devices
4 4
2xR
D D1
(2)
1 2 3 D 4
Thermal pad
5 L1
C L 4
E1
See view B A
0.01 M D B M
2 x b2 C View A - A
2x e
3xb
b4 A1
0.10 M C A M
(b1, b3, b5)
Planting Base metal
Lead Assignments
1. Gate D DE E
2. Drain
3. Source (c) c1
C C
4. Drain
(b, b2, b4)
(4)
Section C - C, D - D, E - E
View B
MILLIMETERS INCHES MILLIMETERS INCHES
DIM. MIN. MAX. MIN. MAX. DIM. MIN. MAX. MIN. MAX.
A 4.58 5.31 0.180 0.209 D2 0.51 1.30 0.020 0.051
A1 2.21 2.59 0.087 0.102 E 15.29 15.87 0.602 0.625
A2 1.17 2.49 0.046 0.098 E1 13.72 - 0.540 -
b 0.99 1.40 0.039 0.055 e 5.46 BSC 0.215 BSC
b1 0.99 1.35 0.039 0.053 Øk 0.254 0.010
b2 1.53 2.39 0.060 0.094 L 14.20 16.25 0.559 0.640
b3 1.65 2.37 0.065 0.093 L1 3.71 4.29 0.146 0.169
b4 2.42 3.43 0.095 0.135 N 7.62 BSC 0.300 BSC
b5 2.59 3.38 0.102 0.133 ØP 3.51 3.66 0.138 0.144
c 0.38 0.86 0.015 0.034 Ø P1 - 7.39 - 0.291
c1 0.38 0.76 0.015 0.030 Q 5.31 5.69 0.209 0.224
D 19.71 20.82 0.776 0.820 R 4.52 5.49 0.178 0.216
D1 13.08 - 0.515 - S 5.51 BSC 0.217 BSC
ECN: X13-0103-Rev. D, 01-Jul-13
DWG: 5971
Notes
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Contour of slot optional.
3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at
the outermost extremes of the plastic body.
4. Thermal pad contour optional with dimensions D1 and E1.
5. Lead finish uncontrolled in L1.
6. Ø P to have a maximum draft angle of 1.5 to the top of the part with a maximum hole diameter of 3.91 mm (0.154").
7. Outline conforms to JEDEC outline TO-247 with exception of dimension c.
8. Xian and Mingxin actually photo.
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