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    Mutayyab Cheema
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    The document contains instructions for 3 Verilog assignments: 1) Write a 9-bit parity checker with a test bench using the registration number as input for 3 patterns, 2) Write a BCD to 7-segment decoder with a test bench using the registration number as input for 3 patterns, and 3) Write an 8-bit sign magnitude adder with a test bench using the registration number as input for both numbers for 3 patterns. Simulation waveforms are to be included for each.

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    The document contains instructions for 3 Verilog assignments: 1) Write a 9-bit parity checker with a test bench using the registration number as input for 3 patterns, 2) Write a BCD to 7-segment decoder with a test bench using the registration number as input for 3 patterns, and 3) Write an 8-bit sign magnitude adder with a test bench using the registration number as input for both numbers for 3 patterns. Simulation waveforms are to be included for each.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    4 views1 page

    Assign Men 1

    Uploaded by

    Mutayyab Cheema
    The document contains instructions for 3 Verilog assignments: 1) Write a 9-bit parity checker with a test bench using the registration number as input for 3 patterns, 2) Write a BCD to 7-segment decoder with a test bench using the registration number as input for 3 patterns, and 3) Write an 8-bit sign magnitude adder with a test bench using the registration number as input for both numbers for 3 patterns. Simulation waveforms are to be included for each.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 1

    Assignment #1(CLO-1)

    1. Write a Verilog-2001 code 9-bit parity checker.


     Also write its test bench and include Modelsim simulation waveforms.
     Use your registration number as input in test bench for input.For second input pattern,
    use (registration number + 5) while for third input pattern, use (registration number - 5)
    for input numbers

    2. Write a Verilog-2001for BCD to seven segment decoder:


     Also write its test bench and include Modelsim simulation waveforms.
     Use your registration number as input in test bench for input.For second input pattern,
    use (registration number + 5) while for third input pattern, use (registration number - 5)
    for input numbers

    3. Write a Verilog-2001 code for 8-bit sign magnitude adder using operators and procedural
    statements.
     Also write its test bench and include Modelsim simulation waveforms.
     Use your registration number as input in test bench for both numbers. For second input
    pattern, use (registration number + 5) for both input numbers. For third input pattern,
    use (registration number - 5) for both input numbers

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