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Scope wise:
SIGNAL has scope to whole architecture. It can be access from any place in
architecture of entity.
VARIABLE is local to procedure defined in the architecture.
Behaviour wise:
Variable assignment is evaluated and assigned in a single step:
1) Execution flow within the procedure is blocked until the Execution flow within the
procedure is blocked until the
assignment is completed.
Variable assignment is same as Blocking assignment in Verilog.
Synthesis wise:
SIGNAL infer a FLOP during synthesis.
VARIABLE infer just a WIRE during synthesis.
Example:
Signal assignment:
library IEEE;
use IEEE.std_logic_1164.all;
entity xor_sig is
port (
A, B, C: in STD_LOGIC;
X, Y: out STD_LOGIC
);
end xor_sig;
Variable assignment:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity xor_var is
port (
A, B, C: in STD_LOGIC;
X, Y: out STD_LOGIC
);
end xor_var;