Professional Documents
Culture Documents
Digital Systems
Vinod Prasad
Professor, Electrical Engineering Dept.
IIT Palakkad
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General Information
Prof. Vinod Prasad
Email: vinod@iitpkd.ac.in
Office: Transit campus (Placement building)
Phone: 04923226-419 / 513
Assessment
Test 1 - 20%
Test 2 - 20%
Final Exam - 60%
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General Information
Text Book:
Reference Book:
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Class timetable
SLOT SYSTEM – A for Semester IV courses
08.00-08.50 09.00-09.50 10.00-10.50 11.00-11.50 12.00-12.50 13.00-13.50 14.00-14.50 15.00-15.50 16.00-16.50 17.00-17.50
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We will follow:
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Course Contents
Introduction
Number systems and codes
Boolean algebra and logic gates
Gate-Level minimization
Combinational logic
Synchronous sequential logic
Registers and counters
Memory and programmable logic
Register transfer level (RTL)
Asynchronous sequential logic
State Machine Design
Memory and Programmable Logic Devices
Field Programmable Gate Arrays
6
1. Introduction
Analog systems Digital systems
Weighing
Machine
Blood
Pressure
Monitor
Ammeter
7
1. Introduction
Analog systems Digital systems
Process
control
systems
Radio
TV
8
Advantages of Digital Systems over Analog Systems
- Greater flexibility: Digital systems can be programmed and
reprogrammed (reconfigured) to perform a variety of functions,
without modifying the hardware – This is one of the biggest
advantages of Digital systems.
Digital Digital
Digital
signal signal
input System Output
12
Analog and Digital Signals
Analog signals:
continuous in time, continuous in amplitude
Discrete-time signals:
discrete in time, continuous in amplitude
Digital signals:
discrete in time, discrete in amplitude
14
Role of ADC and DAC in a typical Process Plant Control
15
Analog to Digital Conversion
One of the most desirable properties is that the analog
signal reconstructed from the digital signal should look the
same as the original analog signal.
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Signal Sampling
time
1 msec
Reconstructed signal frequency (Observed
frequency) = 1 KHz (OK)
Ratio: fS/fSIG = 6/1 = 6
Sampling of Signal (cont)
Example 2: (further reduced in samples per
cycle)
Frequency of signal fSIG = 2 KHz
• 2 cycles in 1 msec
Sampling frequency fS = 6 KHz
• 6 samples in 1 msec
time
1 msec
time
1 msec
time
1 msec
time
1 msec
Observed frequency = 3KHz i.e. correct freq
(Ratio: fS/fSIG = 6/3 = 2)
Minimum Sampling Frequency (cont)
Example 6:
Frequency of signal fSIG = 3 KHz (3 cycles in 1 msec)
Sampling frequency fS = 6 KHz (6 samples in 1 msec)
Ratio: fS/fSIG = 6/3 = 2
time
1 msec
time
1 msec
Observed frequency = 0Hz!
Ratio: fS/fSIG = 6/3 = 2
Nyquist-Shannon Sampling Theorem
Harry Nyquist (1889-1976, Engineer @ Bell Labs) and
Claude Shannon (1916-2001, Engineer @ Bell Labs)
Shannon’s Mouse ("Theseus“) - First Artificial
Intelligence Device (1950) !
Maze navigation: Magnetic mouse whose
movement controlled by electromechanical relay
circuit.
The mouse was designed to search through the
corridors until it found the target.
The mouse could be placed anywhere it had been
before, and because of its prior experience it
could go directly to the target.
If placed in unfamiliar territory, it was programmed
to search until it reached a known location and
then it would proceed to the target, adding the
new knowledge to its memory and learning new
behaviour.
Sampling Theorem
A bandlimited continuous-time signal, with highest
frequency (bandwidth) Fmax, can be uniquely
reconstructed from its samples provided that the
sampling rate Fs ≥ 2 Fmax.
Example:
A 3-bit Analog-to-Digital Converter
• input voltage range: 0 to 10V
• i.e. infinite values (in between 0V to10V range)
• output:
• possible output values: 0, 1, 2 ….. 7
• i.e. only 23 = 8 values
Quantizing and Encoding
• Approximates a continuous range of values and
replaces it with a binary number
• Error is introduced between input voltage and
output binary representation
• Error depends on the resolution of the ADC
Increase in resolution improves the accuracy of the conversion
101
100
011
010
001 Q = 1.25V
INPUT (Analog)
000
0V 1.25V 2.5V 3.75V 5.0V 6.25V 7.50 8.25V
10V
Quantization Step-Size (Quantum) Q
• the input voltage range for which its digital o/p value remains the
same
determines the uncertainty (error) in the actual input analog
value
• Q = FS/2n (where ‘FS’ is the full-scale value and ‘n’ is number of
bits).
Quantization Error
The quantization
error, eq, is bounded
by half of the step-
size, that is,
where Δ is the
quantization step-
size, or the ADC
resolution in volts
(also referred as
Vmin, minimum
detectable voltage)
or the LSB value of
the ADC.
Resolution of ADC
Can be expressed/described in terms of
• number of bits (n) of ADC
e.g. 8-bit, 10-bit
• actual Quantization step-size Q = FS/2n
where FS = Full Scale input
e.g. 1.25V (for a 0V-10V, 3-bit ADC)
2.44mV (for a ±5V, 12-bit ADC)
37
Binary valued digital signal
Binary signal ‐‐ only two possible values
Usually represented as logic values 0 and 1.
Logic value 0 0 volts (High)
Logic value 1 +5 volts (Low)
These voltages may differ, depending on the
hardware used to implement.
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Binary logic
Consists of binary variables (that take on two
discrete values, 0 or 1) and a set of logical
operations.
Logical
operations
listed in a
compact form
called Truth
Tables
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Binary logic
40
Components of digital systems
Logic gates, flip flops, latches, etc. Inputs
and outputs of these hardware components
are logic values 0 and 1. These components
consists of basic components such as
transistors, diodes, resistors, capacitors etc.