SOC Design Flow
Challenges of SoC Era
• Deign complexity
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– Validation & Verification
– Design space exploration
– Integration
– Timing & power
– Testing
– Packaging
• Time to market
• The cost
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From Requirement to Deliverables
Hierarchy Hierarchy
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Refinemenet Validaton
Customer Product
Needs System Vaildation "Pattern" Deliver
System Function System Function
Architecture Architecture
Verification
Behavioral Behavioral
RTL Test
Patern
Logical Netlist Logical Device
Layout
Wafer
Abstract Mask Real
Fab
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Five SoC Design Issues
• To manage the design complexity
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– Co-design
– IP modeling
– Timing closure
– Signal Integrity
– Interoperability
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How to Conquer the Complexity
• Use a known real entity
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– A pre-designed component (reuse)
– A platform
• Partition
– Based on functionality
– Hardware and software
• Modeling
– At different level
– Consistent and accurate
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SoC Design Flow
Specification
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High Level Algorithm Model
C/C++/COSSAP/VCC/MATLAB
System Level
Design
Hardware/Software Partition
N2C/VCC
Communication Refinement Hardware/Software Coverification
N2C/Port-C/VCC N2C/Seamless/"Q/Bridge"
RTOS Device Driver
Hardware
Software
Front End
Design
Design
WinCE/VxWorks Driveway
Back End Embedded
API
Software
Chip
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Physical Design Flow
• In VDSM Specification
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– Interconnect dominates delay System Level
Design
– Timing closure
High Level
– Signal integrity Design
Front
• Traditional design flow End
Functional
Verification
– Two-step process
Synthesis
– Physical design is performed
independently after logic design P&R
• New design flow Timing
Simulation
– Capture real technology behaviors
early in the design flow Back
LVS/DRC
End
– Break the iteration between physical
RC
design and logic design Extraction
Chip
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Making Sense of Interconnect
• At 0.35u, timing convergence started to become a problem.
• At 0.25u, it started to significantly impact the work of the
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designer.
• At 0.18u, if not accounted for, it actually causes designs to fail.
Percentage of Delay
Gate
Wire
1.0u 0.5u 0.25u 0.18u
Silicon Technology
Source: Avant! Source: Synopsys
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Interconnect Power Consumption in DSM
• DSM effects in energy dissipation:
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cross-coupling capacitances
Source: Y. Zorian, S. Dey, and M. Rodgers, “Test of Future System-on-Chips,” Proceeding of the 2000 International Conference on Computer-Aided Design, 392-398 8
Signal Integrity and Timing Closure
• Root causes of both Signal Integrity and Timing Closure
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– Inadequate interconnect modeling techniques
– No effective design methodology
• Synthesis timing does not correlate with physical timing
– Factors
• Coupling capacitance increases
• Interconnect resistance increases
• Device noise margins decrease
• Higher frequencies result in on-chip inductive effects
– Problems
• Signal electromigration
• Antenna effects
• Crosstalk delay
• Crosstalk noise
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Example - Crosstalk Delay
• Net-to-net coupling capacitance dominates as a
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percentage of total capacitance in VDSM.
• The coupling capacitance can be multiplied by the
Miller Effect
– Wire capacitance can be off by 2X if the adjacent wires
are switching in the opposite direction.
– The coupling capacitance can be much less than
expected if the wires are switching in the same
direction
• Both have to be considered during timing analysis
to fully account for setup and hold constraints.
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New Physical Design Flow Needed
Specification
• Bring physical information into the
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System Level
logical design Design
• Overview of solutions High Level
Design
– Single pass methodology Front
Functional
End
– Synthesis-driven layout Verification
– Layout-driven synthesis Synthesis
– All-Integrated (optimization, analysis
and layout) layout P&R
Timing
Synthesis Simulaton
Back
LVS/DRC
Back End
Sign-off
Annotated
Package RC
Delay
Extraction
P&R Chip
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HW/SW Cosimulation Through Emulation
• Emulation in “virtual silicon” 100M
CPS (Cycle/Second
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10M
ices
ls
– Complete functional simulation 1M Emulation
ode
erv
100K
IP M
nS
atio
10K
of the chip at close to real time
con
ific
1K
Sili
Acceleration
Ve r
100
Source: IKOS Systems Inc
– Run real software 10 Simulation
• Tools to enable simulation between EDAs and
emulators
– Cycle-based simulators
– Full-timing simulators
– Instruction set simulators
– E.g. Quickturn Q/Bridge
• Expensive, long learning curve and set-up time
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Embedded Software Architecture for SoC Design
Error Memory
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MMI/GUI
Host Handling Allocation
Diagnostics
Application Message Task State
Manager controller Machine
Application Program Interface
Display Alarm Event
Services Services Manager
Stack Kernel
Protocol File Data Services
Library
Manager I/O
Device Drivers
Hardware
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Software Development
• Porting software to a new processor and RTOS
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– Using a common RTOS abstraction layer
• The evolution of embedded system in the future
– An standard RTOS
Application Software Application Software
Optimized API New API Needed
RTOS New RTOS
Microprocessor New Microprocessor
Old New
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Software Performance Estimation
• Have to take the following into account
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– Instruction set
– Bus loading
– Memory fetching
– Register allocation
• Example: Cadence VCC technology
– CPU characterized as Virtual Processor Model
– Using a Virtual Machine Instruction Set
– SW estimation using annotation into C-Code
– Good for early system scheduling, processor load estimation
• Two orders of magnitude faster than ISS
• Greater than 80% accuracy
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Tester Partitioning
High bandwidth
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Source/ Source/
Logic Sink Logic
Sink Low bandwidth
Source/ Source/ Source/
Memory Sink Sink Memory
Sink
Source/ Source/
Sink PLL Sink PLL
External Tester Embedded Tester External Tester Embedded Tester
Source: Y. Zorian, S. Dey, and M. Rodgers, “Test of Future System-on-Chips,” Proceeding of the 2000 International Conference on Computer-Aided Design, 392-398 16
Self-Testing of Embedded Processor Cores
• Logic BIST
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– Based on the application of pseudo random test
patterns generated by on-chip test pattern generators
like LFSRs.
– Cannot always achieve very high fault coverage for
processor cores.
• Instruction-based self-test techniques
– Rely on generating and applying random instruction
sequences to processor cores.
– The approach determines the structural test needs of
processor components
– Advantage: programmability and flexibility
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Platform-based Design
Block Authoring VC Chip Integration SW
Delivery Development
Executable Specification
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Functional
Design
Digital & Mixed Signal
Dynamic Virtual System System Dynamic System
Verification Analysis Analysis Verification Analysis
Architecture
Block Chip RTOS/
Design
Specification Specification/ Application
IP Selection Selection
Formal IP Handoff
Testbenches
Testbenches
Block
Integration
Design
Design Planning Integration
Static Planning Module
Verification Development
Static
Verification
Physical
Design
Implementation Chip
Implementation
Supporting Manufacturing
Physical
Verification SW
Physical Distribution
Link
Verification
Technology
SW
Cell IP Portfolio Authoring Guide Integration Development RTOS/
IP Portfolio
Libraries Platform Links Applications
" Source: “Surviving the SOC Revolution - A Guide to Platform-Based Design” by Henry Chang et al, Kluwer Academic Publishers, 1999 18
Design Entry
Gate level
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Truth table
1K~10K
FSM
Waveform Manage Size and Run-Time
RTL level 10K~100k
System level modeling 100K~100M
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Hardware Platform-Based Design
It is a “meet-in-the-middle” approach.
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System Integrator Perspective Platform Provider Perspective
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System-Level Design
• Goal
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– To define the platform that satisfies the system
functions with performance/cost tradeoff
• Platform design
– Bus structure
– IP and their function design
Customized instructions
Parallelism
Command parameters
Configurable parameters
IP parameters
– Control scheme
– Data communication (bandwidth)
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Control Scheme Model
Interrupts
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Interrupt
Status Polling (timer)
Status
Command
Configuration
Data Receive Buffer
Data Transmit Buffer
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Some Helps in System-Level Design
• Cadence VCC (Virtual Component Codesign,
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from Cadence Berkely Labs)
– Performance simulation
– Communication refinement technology
• Vast Systems Technology
– VPM (Virtual Processor Model)
– HW/SW codesign
• CoWare N2C (Napkin-to-chip)
– Interface synthesis
• SystemC
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Cadence’s VCC
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Full System Specification
Block Level VCC Platform VCC Platform
Specification Function Architecture
IP Block System Integration
SPW VCC Functional
DSP Behavioral Specification System Integration
IP Block Authoring
SPW Floating Point VCC Performance Analysis and
Development
Development
Hardware
Software
Algorithm Analysis Platform Configuration
SPW Fixed Point VCC Communication Synthesis
Algorithm Analysis Communication Integration
VCC Hardware VCC Software
SPW HDS Block Implementation
Assembly Assembly
HW/SW Verifier - Verification Cockpit - NC-SIM
RTL Block Verification and HW-SW-Co-Verification
Synthesis / Place & Route etc.
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An Opportunity To Do It Right !
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SystemC Heritage
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SystemC Roadmap
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The Intent of Different Level of Model
• Design exploration at higher level
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– Import of top-level constraint and block architecture
– Hierarchical, complete system refinement
– Less time for validating system requirement
– More design space of algorithm and system
architecture
• Simple and efficient verification and simulation
– Functional verification
– Timing simulation/verification
– Separate internal and external (interface) verification
– Analysis: power and timing
• Verification support
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SystemC
• SystemC is a modeling platform
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– C++ extensions to add hardware modeling constructs
– a set C++ class library
– simulation kernel
– supports different levels of abstraction
Good Candidate for Task Level Mapping
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Level of abstraction in SystemC
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SystemC Design Flow
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Source: SystemC Users Forum, DAC, June 2000
Example
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Implementing Virtual Prototypes
• Functionality partition
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• Module specification
• Communication refinement
Func_A()
{
MC
IQ_IDCT()
...... MC
{
IQ(); Func_B() ......
......{ IQ(); FIFO
} ......
IDCT();
IDCT();
......
IQ-
......
} IDCT IQ-
}
IDCT
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Functionality Partition
• Separating communication and computation
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• Using hierarchy to group related functionality
• Choosing the granularity of the basic parts
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Module Specification (1/2)
Process A
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entry()
{
......
Z = func_B(X,Y);
......
}
func_B(X,Y)
{
Z = X+Y;
retuen Z;
2 }
Process B Process C
X
entry() entry()
{ {
...... Y X.read();
X.write(); Y.read();
Y.write(); Z = X+Y;
Z.read(); Z Z.write();
...... }
}
3
1. Pull out functionality into new created process
2. Replace function call with inter-process communcation.
3. Instantiate new process and define channels to connect them.
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Module Specification (2/2)
• Abstraction Levels
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– Untimed Functional Level
– Processes execute in zero time but in order
– Timed Functional Level
– Bus-Cycle Accurate Level
• Transaction on bus are modeled cycle accurate
• Cycle Accurate Level
– Behavior is clock cycle accurate
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Communication Refinement
Key
Guarantee consistency of communication during refinement
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Software Performance Estimation
• Have to take the following into account
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– Instruction set
– Bus loading
– Memory fetching
– Register allocation
• Example: Cadence VCC technology
– CPU characterized as Virtual Processor Model
– Using a Virtual Machine Instruction Set
– SW estimation using annotation into C-Code
– Good for early system scheduling, processor load estimation
• Two orders of magnitude faster than ISS
• Greater than 80% accuracy
38
Discussion: Commonality and Differentia
• Differentiae
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– Processor core (e.g., customized inst. set)
– IP parameterized
– IP add/move
• Design methodology of platform
– System-level
– Platform-level design methodology
• Design flow
• Models
• Tools (EDA venders, 3rd party or home-made)
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Summary
• Platform-based design
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– From board design to SoC design
– From executable spec., i.e., C/C++, to SystemC
• Modeling
– Performance evaluation
– Task mapping
– Communication refinement
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