Title: Sequential Multipier

Course: Digital System Design Lab

Course Code: ECP-404

Sequential multipler :
If we want to multiply two binary number (multiplicand X has n bits and multiplier
Y has m bits) using single n bit adder, we can built a sequential circuit that
processes a single partial product at a time and then cycle the circuit m times.
This type of circuit is called sequential multiplier.
Sequential multipliers are attractive for their low area requirement. In a
sequential multiplier, the multiplication process is divided into some sequential
steps. In each step some partial products will be generated, added to an
accumulated partial sum and partial sum will be shifted to align the accumulated
sum with partial product of next steps.
Therefore, each step of a sequential multiplication consists of three different
operations which are generating partial products, adding the generated partial
products to the accumulated partial sum and shifting the partial sum.

A sequential multiplier requires some additional signals for

synchronization purpose.
• Input clk: clock signal to synchronize the system.
• Input reset: asynchronous reset signal to initialize the system.
• Input start: synchronous signal that must be high to start a new
operation.
• Output done: synchronous signal that is set during 1 cycle by the
multiplier when the result of the operation is available.

RTL schematic:
VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity summ is
Port ( reset : in STD_LOGIC;
start : in STD_LOGIC;
clk : in STD_LOGIC;
state : out STD_LOGIC_VECTOR (1 downto 0));
end summ;

architecture Behavioral of summ is

shared variable C :integer;

signal M , A : std_logic_vector (8 downto 0);
signal Q : std_logic_vector (7 downto 0);
type state_type is (j,k,l,n);
signal mstate,next_state : state_type;
begin
state_register:process(clk,reset)
begin
if reset= '1' then
mstate <=j;
elsif clk'event and clk = '1' then
mstate<=next_state;
end if;
end process;
state_logic : process(mstate,A,Q,M)
begin
case mstate is when j=> if start='1'then
next_state <= k ;
end if;
when k=> A<="000000000";
-- carry<='0';
C := 8;
next_state<=l;
when l=> C := C - 1;
if Q(0)='1' then
A <=A+M;
end if;
next_state<=n;
when n=> A<= '0' & A( 8 downto 1);
Q<= A(0) & Q(7 downto 1);
if C = 0 then
next_state<=j;
else
next_state<=k;
end if;
end case;
end process;
end Behavioral;