Reg. No……………………………… Reg.

No………………………………
SSM INSTITUTE OF ENGINEERING AND TECHNOLOGY SSM INSTITUTE OF ENGINEERING AND TECHNOLOGY
Sindalagundu Post, Dindigul – 624 002 Sindalagundu Post, Dindigul – 624 002
Department of Electrical and Electronics Engineering Department of Electrical and Electronics Engineering
Internal Test - III Internal Test - III
EE8351 – Digital Logic Circuits EE8351 – Digital Logic Circuits
Class: II Year Max Marks: 50 Marks Class : II Year Max Marks: 50 Marks
Date : 10.10.19 Time: 11.00am to 12.30pm Date : 10.10.19 Time: 11.00am to 12.30pm
Part A (10 × 2 = 20 Marks) Part A (10 × 2 = 20 Marks)
Answer any 10 Questions Answer any 10 Questions
1.Define race in Asynchronous sequential Circuit? 1.Define race in Asynchronous sequential Circuit?
2.Compare Pulsed mode and fundamental model of asynchronous circuit 2.Compare Pulsed mode and fundamental model of asynchronous circuit
3.Convert T flip flop to D flip flop 3.Convert T flip flop to D flip flop
4.What are flow table and primitive flow table? 4.What are flow table and primitive flow table?
5.What is Presettable and ripple counters? 5.What is Presettable and ripple counters?
6.Define essential Hazard 6.Define essential Hazard
7.What is static Hazard and dynamic Hazard 7.What is static Hazard and dynamic Hazard
8.Compare PROM PLA and PAL? 8.Compare PROM PLA and PAL?
9.What is PROM? 9.What is PROM?
10.Draw the block diagram of PLA 10.Draw the block diagram of PLA
11.Compare FPGA and CPLD? 11.Compare FPGA and CPLD?
12. Write VHDL code for 2*1 Mux 12.Write VHDL code for 2*1 Mux
13. What is Package in VHDL 13.What is Package in VHDL
14. Write the behavioral model of D flipflop 14.Write the behavioral model of D flipflop
15. Give syntax for package declaration and package body in VHDL? 15.Give syntax for package declaration and package body in VHDL?
16.What are the languages that are combined together to get VHDL? 16.What are the languages that are combined together to get VHDL?
17.What is test bench and give its types 17.What is test bench and give its types
18. What are the various modeling techniques in HDL 18.What are the various modeling techniques in HDL
19. When can RTL be used to represent digital systems 19.When can RTL be used to represent digital systems
20. Write VHDL code for half adder in data flow model 20. Write VHDL code for half adder in data flow model
Part B Part B
Answer for 30 marks Answer for 30 marks
21a) Design mealy type sequence detector to detect the input sequence 101 (8) 21a)Design mealy type sequence detector to detect the input sequence 101 (8)
b)Realize SR flip flop from JK flip flop (7) b) Realize SR flip flop from JK flip flop (7)
22a) Write the various types of hazards in sequentail circuit and methods to 22a)Write the various types of hazards in sequentail circuit and methods to
eliminate them (7) eliminate them (7)
b) Implement the following Boolean function using PLA and PAL b)Implement the following Boolean function using PLA and PAL
F(x y z) =∑m (0,1,3,5,7) (8) F(x y z) =∑m (0,1,3,5,7) (8)
23a)Build reduced state table from the given table (8) 23a)Build reduced state table from the given table (8)
N.S Output N.S Output
P.S P.S
X=0 X=1 X=0 X=1 X=0 X=1 X=0 X=1
a f b 0 0 a f b 0 0
b d c 0 0 b d c 0 0
c f e 0 0 c f e 0 0
d g a 1 0 d g a 1 0
e d c 0 0 e d c 0 0
f f b 1 1 f f b 1 1
g g h 0 1 g g h 0 1
h g a 1 0 h g a 1 0
Starting from state ‘a’ and input sequence 01110010011 determine the output Starting from state ‘a’ and input sequence 01110010011, determine the output
sequence for state table and reduced table. sequence for reduced table.
b) Explain in detail about the FPGA with block diagram (7) b) Explain in detail about the FPGA with block diagram (7)
24a) Explain in detail the RTL design procedure (8) 24a)Explain in detail the RTL design procedure (8)
b)Explain the various types of operator supported by VHDL (7) b) Explain the various types of operator supported by VHDL (7)
25a)Write VHDL code to realize a full adder using structural model and (8) 25a)Write VHDL code to realize a full adder using structural model and (8)
behavioural modelling. behavioural modelling.
b)Write VHDL code for 4*1 Multiplexer (7) b)Write VHDL code for 4*1 Multiplexer (7)

Faculty Incharge HoD/EEE Faculty Incharge HoD/EEE