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1

ARITHMETIC OPERATIONS

Course Code: Program:

Course Title: Date Performed:

Section: Date Submitted:

Members: Instructor:

1. Objective(s):

The activity aims the students to create the simulation of arithmetic operations using VHDL

code.

2. Intended Learning Outcomes (ILOs):

The students shall be able to:

2.1 Create VHDL test bench of unsigned 8-bit adder, unsigned 8-bit adder with carry in, unsigned 8-bit

adder with carry out, unsigned 8-bit adder with carry in and carry out, simple signed 8-bit adder in

connection with VHDL module.

2.2 Simulate the unsigned 8-bit adder, unsigned 8-bit adder with carry in, unsigned 8-bit adder with

carry out, unsigned 8-bit adder with carry in and carry out, simple signed 8-bit adder using VHDL

codes.

2.3 Create schematic diagram of each arithmetic operations.

3. Discussion:

Arithmetic operations such as unsigned 8-bit adder, unsigned 8-bit adder with carry in, unsigned 8-bit adder

with carry out, unsigned 8-bit adder with carry in and carry out and simple signed 8-bit adder.

Unsigned 8-bit adder is like the logical addition process of switching circuits.

Unsigned 8-bit adder with carry in has additional input name CI which is also like the logical addition

process of switching circuits.

The pin description of unsigned 8-bit adder with carry in is shown in Table 1-2.

1

s

Unsigned 8-bit adder with carry out has additional output name CO which is also like the logical addition

process of switching circuits.

The pin description of unsigned 8-bit adder with carry out is shown in Table 1-3.

In VHDL, before writing a "+" operation with carry out, examine the arithmetic package you are going to

use. For example, "std_logic_unsigned" does not allow you to write "+" in the following form to obtain Carry

Out:

Res(9-bit) = A(8-bit) + B(8-bit)

The reason is that the size of the result for "+" in this package is equal to the size of the longest argument,

that is, 8 bits.

One solution, for the example, is to adjust the size of operands A and B to 9-bits using concatenation.

Res <= ("0" & A) + ("0" & B);

In this case, XST recognizes that this 9-bit adder can be implemented as an 8-bit adder with carry out.

Another solution is to convert A and B to integers and then convert the result back to the std_logic vector,

specifying the size of the vector equal to 9.

• std_logic_arith. This package contains the integer to std_logic conversion function, that is,

conv_std_logic_vector.

• std_logic_unsigned. This package contains the unsigned "+" operation.

Unsigned 8-bit adder with carry in and carry out is a combination of carry in and carry out.

The pin description of unsigned 8-bit adder with carry in and carry out is shown in Table 1-4.

Table 1-4. Unsigned 8-bit Adder with Carry In and Carry Out

2

Simple signed 8-bit adder is also like the logical addition process of switching circuits.

The pin description of simple signed 8-bit adder is shown in Table 1-5.

Unsigned 8-bit Subtractor is also like the logical subtraction process of switching circuits.

This section contains a VHDL description for an unsigned 8-bit greater or equal comparator.

The pin description of unsigned 8-bit greater or equal comparator is shown in Table 1-8.

3

Table 1-8. Unsigned 8-bit Greater or Equal Comparator

Xilinx software

Computer Unit

5. Procedure:

1. Using Xilinx Software make a project with a named unsigned_8bit_Adder. (Please refer to topic A

and follow steps 1-7 of the introduction part)

2. Create an HDL Source (Please refer to topic B and follow steps 1 to 5 of the introduction part).

3. Enter the following parameters in the “Define Module” dialog box

Port Name Direction Bus MSB LSB

A In √ 7 0

B In √ 7 0

SUM Out √ 7 0

4. Click next, then Finish

5. In the architectural behavioral body of the VHDL Module codes enter the following:

begin

SUM <= A + B;

end behavioral;

6. Compare the given codes below to the VHDL Module codes created.

--

-- Unsigned 8-bit Adder

--

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity unsigned_8bit_Adder is

port(A,B : in std_logic_vector(7 downto 0);

SUM : out std_logic_vector(7 downto 0));

end unsigned_8bit_Adder;

architecture behavioral of unsigned_8bit_Adder is

begin

SUM <= A + B;

end behavioral;

If it is not equal, what should be added to the edited VHDL Module code?

______________________________________________________________________________

4

______________________________________________________________________________

______________________________________________________________________________

7. Edit the VHDL module based on the given codes above.

What do you think is the importance of the missing codes that just added?

_______________________________________________________________________________

_______________________________________________________________________________

____________________________________________________________________________

8. Uncheck the Manual Compile if it is checked. (Please refer to topic B with Figure 7 about manual

compile within the introduction part)

9. Right click on the unsigned_8bit_Adder under the Hierarchy panel of the Design View. (Upper left

portion of the Xilinx window) and choose Implement Top Module.

Note: Make sure that the Implementation under the Hierarchy panel of the Design View radio

button is selected.

10. Click yes.

11. If there is no error, proceed to the next step. Else, what are the errors encountered and what did

you do in order to correct it?

_______________________________________________________________________________

_______________________________________________________________________________

____________________________________________________________________________

12. Right click the unsigned_8-bit_Adder and choose new source.

13. Choose VHDL test bench on the new source wizard dialog box.

14. Write unsigned_8-bit_Adder_tb in file name textbox, click next twice (make sure that the add to

project check box is selected) then click finish.

15. Click the Simulation radio button and click on the appeared VHDL test bench codes.

16. Edit the clock part of the VHDL test bench body. (Please refer to topic C and follow steps 4-6)

17. In the input stimulus comment part of the test bench body, write the following codes:

A<=”00000000”;

B<=”00000000”;

wait for 15 ns;

A<=”11111100”;

B<=”11100000”;

wait for 15ns;

18. View the timing diagram. (Please refer to topic D and follow steps 1-5)

Did you encounter any errors? List down the errors encountered.

_______________________________________________________________________________

_______________________________________________________________________________

____________________________________________________________________________

19. Click on the zoom full view and observe the output waveform of the appeared window. The output

SUM of the waveform should be equivalent to the table below.

A B SUM

00000000 00000000 00000000

11111100 11100000 11011100

20. Close the simulation window.

21. Copy the given input of A and B in table 1-9 and follow steps 17 to 18.

22. Write the output in table 1-9 based on the new simulated waveform.

What did you notice to the waveform created related to unsigned 8-bit adder?

5

_________________________________________________________________________

_________________________________________________________________________

_________________________________________________________________________

23. View the schematic diagram. (Please refer to topic E page 10)

24. Copy the appeared schematic diagram and simulated waveform in data and result.

25. Repeat steps 1 to 21 in creating unsigned 8-bit adder with carry in, unsigned 8-bit adder with carry

out, unsigned 8-bit adder with carry in and carry out, simple signed 8-bit adder and please refer to

the following codes below:

--

-- Unsigned 8-bit Adder with Carry In

--

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity adders_2 is

port(A,B : in std_logic_vector(7 downto 0);

CI : in std_logic;

SUM : out std_logic_vector(7 downto 0));

end adders_2;

architecture archi of adders_2 is

begin

SUM <= A + B + CI;

end archi;

--

-- Unsigned 8-bit Adder with Carry Out

--

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

entity adders_3 is

port(A,B : in std_logic_vector(7 downto 0);

SUM : out std_logic_vector(7 downto 0);

CO : out std_logic);

end adders_3;

architecture archi of adders_3 is

signal tmp: std_logic_vector(8 downto 0);

begin

tmp <= conv_std_logic_vector((conv_integer(A) +

conv_integer(B)),9);

SUM <= tmp(7 downto 0);

CO <= tmp(8);

end archi;

6

--

-- Unsigned 8-bit Adder with Carry In and Carry Out

--

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

entity adders_4 is

port(A,B : in std_logic_vector(7 downto 0);

CI : in std_logic;

SUM : out std_logic_vector(7 downto 0);

CO : out std_logic);

end adders_4;

architecture archi of adders_4 is

signal tmp: std_logic_vector(8 downto 0);

begin

tmp <= conv_std_logic_vector((conv_integer(A) + conv_integer(B) +

conv_integer(CI)),9);

SUM <= tmp(7 downto 0);

CO <= tmp(8);

end archi;

--

-- Signed 8-bit Adder

--

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_signed.all;

entity adders_5 is

port(A,B : in std_logic_vector(7 downto 0);

SUM : out std_logic_vector(7 downto 0));

end adders_5;

architecture archi of adders_5 is

begin

SUM <= A + B;

end archi;

26. Compare each arithmetic operation and write it as part of Data Analysis.

7

6. Data and Results:

1. Unsigned 8-bit Adder

8

5. Simple signed 8-bit Adder

9

8. Unsigned 8-bit Greater or Equal Comparator

1. Unsigned 8-bit Adder

A B SUM

0000 0000 0000 0000

0000 0000 0000 0001

0001 0000 0000 0000

0001 0000 0001 0000

10

A B CI SUM

0000 0000 0000 0000 0

0000 0000 0000 0001 1

0001 0000 0000 0000 0

0001 0000 0001 0000 1

A B SUM CO

0000 0000 0000 0000

0000 0000 0000 0001

0001 0000 0000 0000

0001 0000 0001 0000

Table 1-12. Unsigned 8-bit Adder with Carry In and Carry Out

A B CI SUM CO

0000 0000 0000 0000 0

0000 0000 0000 0001 1

0001 0000 0000 0000 0

0001 0000 0001 0000 1

A B SUM

0000 0000 0000 0000

0000 0000 0000 0001

0001 0000 0000 0000

0001 0000 0001 0000

11

A B RES

0000 0000 0000 0000

0000 0000 0000 0001

0001 0000 0000 0000

0001 0000 0001 0000

A B SUM CO

0000 0000 0000 0000

0000 0000 0000 0001

0001 0000 0000 0000

0001 0000 0001 0000

A B CMP

0000 0000 0000 0000

0000 0000 0000 0001

0001 0000 0000 0000

0001 0000 0001 0000

Supplemental Activity:

Create a VHDL code with test bench for the following:

1. Unsigned 8-bit Subtractor

2. Unsigned 8-bit Adder/Subtractor

3. Unsigned 8-bit Greater or Equal Comparator

7. Data Analysis

__________________________________________________________________________________

_____________________________________________________________________________________

_____________________________________________________________________________________

_____________________________________________________________________________________

_____________________________________________________________________________________

_____________________________________________________________________________________

_____________________________________________________________________________________

8. Assessment Rubric:

12

13

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