Experiment No.

Logical Shifter
Course Code: CPE 504 Program: BSCPE
Course Title: Computer Systems Architecture Date Performed: September 13, 2019
Section: CPE52FC1 Date Submitted: September 14, 2019
Members: Carlo B. Baja Instructor: Cris Paulo Hate

1. Objective(s):

The activity aims the students to create the simulation of logical shifter using VHDL code.

2. Intended Learning Outcomes (ILOs):

The students shall be able to:

2.1 Create VHDL test bench of logical shifter in connection with VHDL module.
2.2 Simulate the logical shifter using VHDL codes.
2.3 Create schematic diagram of a logical shifters.

3. Discussion:

Logical shifter is the shifting of the bits from selected digit values. It is used in some arithmetic operations
such as multiplication and division. The block diagram in Figure 2-1 includes the combinational circuit with 2
inputs (DI and SEL) and 1 output (SO). The first input, DI, serves as a data input that is being shifted; the
second input, SEL, is a selector to what particular binary value of the shift process while the output is the
result of the shift operation.

Figure 2-1 Logical Shifter Diagram

Table 2-1 Logical Shifter

IO Pins Number of Bits Description
DI 8 Data Input
SEL 2 Shift Distance
Selector
SO 8 Data Output

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In VHDL coding, the “with SEL select” syntax should be used for bits shifting operation. Sample code
using with SEL select syntax is shown below:

(output omitted)
with SEL select
SO <= DI when "00",
DI sll 1 when "01",
DI sll 2 when "10",
DI sll 3 when others;

Sample Output
Input Output
SEL DI SO
01 0000 0011 0000 0110
00 0000 0000 0000 0000
11 0000 1111 0111 1000
10 0001 0011 0100 1100

In writing the logical shifter codes, there are certain rules that should be considered:

• For VHDL, you can only use predefined shift (SLL, SRL, ROL, etc.) or concatenation operations.
• Use only one type of shift operation.
• The n value in the shift operation must be incremented or decremented only by 1 for each consequent
binary value of the selector.
• The n value can be only positive.
• All values of the selector must be presented.

A related constraint is SHIFT_EXTRACT

4. Materials and Equipment:

1. Computer Unit
2. Xilinx Software

5. Procedure:

1. Using Xilinx Software make a project with a named logicalshifters. (Please refer to topic A and
follow steps 1-7)
2. Create an HDL Source (Please refer to topic B and follow steps 1 to 5).
3. Enter the following parameters in the “Define Module” dialog box

Architectural name : Behavioral

Port Name Direction Bus MSB LSB
DI in √ 7 0
SEL in √ 1 0
SO out √ 7 0

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4. Click next, then Finish
5. In the architectural behavioral body of the VHDL Module codes enter the following:
begin
with SEL select
SO <= DI when "00",
DI sll 1 when "01",
DI sll 2 when "10",
DI sll 3 when others;
end behavioral;
6. Compare the given codes below to the VHDL Module codes created.
--
-- Following is the VHDL code for a logical shifter.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity logicalshifters is
port(DI : in unsigned(7 downto 0);
SEL : in unsigned(1 downto 0);
SO : out unsigned(7 downto 0));
end logicalshifters;
architecture behavioral of logicalshifters is
begin
with SEL select
SO <= DI when "00",
DI sll 1 when "01",
DI sll 2 when "10",
DI sll 3 when others;
end behavioral;
If it is not equal, what should be added to the edited VHDL Module code?
Nothing.
7. Edit the VHDL module based on the given codes above.
What do you think is the importance of the missing codes that just added?
To ensure that the logical shifter works as designed.
8. Uncheck the Manual Compile if it is checked. (Please refer to topic B and follow steps includes in
Figure 7)
9. Right click on the logicalshifters under the Hierarchy panel of the Design View. (Upper left portion
of the Xilinx window) and choose Implement Top Module.
Note: Make sure that the Implementation under the Hierarchy panel of the Design View radio
button is selected.

10. Click yes.

11. If there is no error, proceed to the next step. Else, what are the errors encountered and what did
you do in order to correct it?
No errors.
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 12. Right click the logicalshifters and choose new source.
13. Choose VHDL test bench on the new source wizard dialog box.
14. Write logicalshifters_tb in file name textbox, click next twice (make sure that the add to project
check box is selected)then click finish.
15. Click the Simulation radio button and click on the appeared VHDL test bench codes.
16. Edit the clock part of the VHDL test bench body. (Please refer to topic C and follow steps 4-6)
17. In the input stimulus comment part of the test bench body, write the following codes:
DI<=”0000000”;
SEL<=”00”;
wait for 100 ns;
DI<=”00001111”;
SEL<=”11”;
wait for 100 ns;
SEL<=”10”;
DI<=”00010011”;
wait for 100 ns;
DI<=”00000000”;
SEL<=”01”;
wait for 100 ns;
18. View the timing diagram. (Please refer to topic D and follow steps 1-5)
Did you encounter any errors? List down the errors encountered.
None.
19. Click on the zoom full view and observe the output waveform of the appeared window.
20. Close the simulation window.
21. Copy the given input of DI and SEL in table 2-2 and follow steps 17 to 18.
What did you notice to the waveform created related to logical shifters?
The waveform output indicates that toperator sll returns the bottom operand's value after
the R amount of time has been moved. It was using the logical function left by the
change.
22. Write the output in table 2-2 based on the new simulated waveform.
23. View the schematic diagram. (Please refer to topic E page 10)
24. Copy the appeared schematic diagram and simulated waveform in data and result.
25. What if you change the sll to srl code based from the given codes in step 6?
What happened to the output?
The performance is different now that srl has moved everything to the right.
26. What if you change the sll to rol code based from the given codes in step 6?
What happened to the output?
The output is also different since rol rotated/everything and returns the value of the L left
operand after it has been rotated to the left R times.

6. Data and Results:

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 1. Write the output from the given input in Table 2-2.

Table 2-2
Input Output
SEL DI SO
1.) 00 0111 0000 0111 0000
2.) 01 0101 1001 1011 0010
3.) 10 0110 0010 1000 1000
4.) 11 0011 1011 1101 1000
5.) 00 0101 0101 0101 0101
6.) 01 0011 1111 0111 1110
7.) 10 0011 1010 1110 1000
8.) 11 0010 1001 0100 1000
9.) 01 0101 1110 1011 1100
10.) 10 0110 1111 1100 1011

2. Simulated Waveform of the Logical Shifter

7. Data Analysis
The shift operators are described with the components of type BIT or BOOLEAN for the one-dimensional
array. The left operand L is an array for the shift operator and the right operand R is integer. The right
operand is the number of positions that should be shifted to the left operand. The value of the same type as
the left operand is returned as a result of the shift.

The sll, srl, and rol have been used in the operation. The operator sll returns the left operand's value after
the number of times R has been shifted. The operator srl returns the left operand L value after shifting it to
right R times. The operator rol returns the left operand's value after it is rotated to the left R times.

8. Supplemental Activity::

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Create a VHDL code with test bench of the following:
a. Logical Shifters using SRL

b. Logical Shifters using ROL

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Testbench

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 Waveform

Module
8. Assessment Rubric:

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