PCM

PCM, which is generally based on Ge2Sb2Te5 (GST) chalcogenide materials, enables data storage by
switching the GST film between amorphous (reset 0, i.e., high resistance) and crystalline (set 1, i.e., low
resistance) states. Phase change memory (PCM) changes the phase of the material between crystalline
and amorphous phase by using heat produced from Joule heating.

Problem

The accumulated effect of temperature rise can result in a retention failure by crystallizing the
amorphous region Other scalability and reliability issues that need to be overcome include
compositional instability of phase changing material .

Amit Dada’s Work

In this thesis work design a mushroom type phase change memory device founded for low power
switching application is researched. The Finite element approaches to designing a Titanium Nitride (TiN)
based double Phase change memory (PCM) requires a careful choice of the GST layer size, heater size
and suitable material for heater and insulator for fabrication purposes. Simulation has been performed
using COMSOL MULTIPHYSICS 5.2.
The proposed device and parameters he used are given below:

The mushroom-type devices, with doped-GST (d-GST) as phase-change material sandwiched between
the top and bottom electrodes completed of Titanium Nitride (TiN), are used in this modeling method.

Material properties they used for the simulation of the model is:
 Amit Dada’s Contributions

• Devised, developed and implemented the complete thermoelectric finite element- based model in the
COMSOL Multiphysics software.

• Performed extensive investigation and analysis to define the boundary conditions of the model and to
implement the interface thermoelectric effects.

• Field- and temperature-dependence of the material properties were thoroughly stud-id, and a
compact model was used to define the material properties so as to maintain the simplicity of the model.

Amit Dada’s Proposed structure

The simulation was done in Comsol Multiphysics 5.2 simulator. They analyze the performance by effect
of scaling on device performance of TiN heater based phase change memory having heater diameter

20 nm and GST layer thickness 100nm. The scaling with heater width was done from 25nm down to
single nanometer that shows proposed cross sectional structure of phase memory where heater

width into the GST layer is 25nm.

By adding, the reason for the increasing temperature for melting the active region above the heater
contact for the PCM cells is the additional area for heat distribution in the GST due to scaling down

heater width into the GST layer. This results in lower temperatures for larger cells, in the switching
volume for a given Reset voltage pulse.

They then,turned their attention to the scaling of the heater width into the GST layer of the cell and
observed that as the heater widths are scaled down to 1nm size of the device and subsequently
amorphized region also increases, all cases for heater widths down to 1 nm the cell was successfully
amorphized, i.e. a region above the heater was heated to above melting temperature. Surface
temperature increased at the end of the Reset process as cells are scaled down in size and for heater
widths into the GST layer down to 1nm.

The temperature distribution due to scaling effect where the temperature distribution during Reset
(using a 7 V, 1 ns RESET pulse) for a cell with a 25 nm heater width into the GST layer is shown; the
maximum temperature (976K) reached in the GST layer above than the melting temperature and as a
result melting and successful amorphization.
Fig : (a) Surface temperature distribution at the end of the Reset process for 25 nm heater

width into the GST layer.(b) For 5 nm(c) For 1 nm.

One obvious way is to increase the

maximum temperature reached in the GST layer is to increase the heating area in the GST layer as well
as increasing resistance. He turned down to single nanometer heater width into the GST layer ,where
maximum temperature was 1080K under the reset conditions. While heater width decreasing into the
GST layer , the effective area into the GST layer was increasing, which provided more and more internal
resistance into the GST layer. While heater width was decreasing into the GST layer , the heating
temperature into the GST layer was increasing. Maximum temperature increased down to single
nanometer heater width into the GST layer, at the same applied electric Potential.
 Our Work

1.We want to Scale down the heater width to 15 to 6 nm for reducing the cell size . By this work, We
will find that, cells with heater contact sizes as small as 6 nm will be successfully amorphized and
recrystallized (RESET and SET) using moderate excitation voltages. To enable the efficient formation of
amorphous domes during RESET in small cells (heater contact diameters of 10 nm or less), it will be
necessary to improve the thermal confinement of the cell to reduce heat loss via the electrodes. The
resistance window between the SET and RESET states will decrease as the cell size will reduce, but it will
be still more than an order of magnitude even for the smallest cells.

So, the RESET current will be reduce as the cells will get smaller; indeed, RESET current will scale

with the inverse of the heater contact diameter.

2.For example, if we will confirm by simulation that a 5 V, 40 ns RESET pulse successfully amorphizes
cells down to 6 nm heater sizes, it will undesirable since it significantly increases the RESET power,

which will be to reduce RESET power consumption.

3. Lu et al [24, 25] found that by stacking many very thin layers of two commonly used electrode
materials, TiN and W, together to create a super-lattice-like electrode structure, the thermal conductivity
can be reduced to below 1Wm−1 K−1 (see typically >10 and >100 for single layers of TiN and W alone)
and while retaining good electrical conductivity. Using such a multi-layered TiN/W super-lattice-

like top electrode Lu et al showed that significant reductions in RESET voltages and powers could be
achieved, although their work was confined to very large cell sizes (190 nm diameter heater contracts).

We want to use of a stacked top electrode that will be very effective in terms of heat confinement and
subsequent reduction of melting voltages.

In this work, the maximum temperature will reach in the GST layer during a 2.5 V/ 40 ns RESET pulse,
will apply to a cell having 10 nm heater contract width, for both a single layer TiN electrode of 50 nm
thickness and a multi-layer electrode (alsoof 50 nm total thickness) comprising alternating 5 nm layers

of TiN and W (thermal conductivity, K, of 0.42W m−1 K−1). It will be clear that the stacked TiN/W
electrode enables very significantly will increase temperatures (see the single layer TiN electrode) to be
reached for the same excitation conditions, with the maximum temperature will achieve in the stacked
electrode case of approximately 1000 K being well above the melting temperature of GST (compared to
only 640 K, well below the GST melting temperature, for the single layer TiN electrode). By using a
stacked top electrode we will be thus able to achieve successful amorphization in even the smallest cell
sizes.

Our Design will be

Our Materials will be

1.Top stacked electrode (TiN/W)

2.Bottom electrode (W)

3.Phase change material (GST)

4.Heater (TiN)

5.SiO2(used as insulating spacer between adjacent memory devices. The insulating medium is only
included in the thermal model and hence the electrical conductivity and the Seebeck coefficient are
undefined.