cache coherence protocols

BY SHAMBEL GONFA (18BCE2429) Prof ANURADHA G

School of Computer Science and School of Computer Science and

Engineering(SCOPE), Department of CSE. Engineering(SCOPE), Department of
Software System
shambelgonfa.garo2018@vitstudent.ac.in ganuradha@vit.ac.in

VIT, Vellore VIT, Vellore

CACHE COHERENCE PROTOCOLS

Abstract

In a shared memory multiprocessor with a separate cache memory for each processor ,
it is possible to have many copies of any one instruction operand : one copy in the main
memory and one in each cache memory. When one copy of an operand is changed
the other copies of the operand must be changed also. When clients in a system
maintain caches of a common memory resource, problems may arise with incoherent
data, which is particularly the case with CPUs in a multiprocessing system. The magnitude
of the potential performance difference between the various cache coherency
approaches indicates that the choice of coherence solution is very important in the
design of an efficient shared-bus multiprocessor, since it may limit the number of
processors in the system. Proposed multiprocessor designs often include a private cache for each processor in the
system, which gives rise to the cache coherence problem. Cache coherence is intended to manage such
conflicts by maintaining a coherent view of the data values in multiple caches. A distributed
algorithm is used to tackle the cache coherence problem known as cache coherence protocol [1]. In this paper we discuss
cache coherence problems and evaluate snoop based cache coherence.
INTRODUCTION
In the complex multilevel cache level architecture to bind the cache coherence
protocol complexity we need to track the coherence information across all the levels
but this leads implausible cost problem. To empower our future processors we need to
embed more number of cores per chip multiprocessor. But during this we must face the
off chip bandwidth wall, again to overcome this we can use a large on chip cache but
because of plain large capacities of hardware the fast access could not be achieved.
So commercially it is used three level cache architecture where two are used to
maintain private data being closer to processor and the last one shared among cores.
Have large number of cores might be helpful in some most of the cases but at the same
time it is unachievable to rely on broadcast-based coherence protocols [2]. There are
three distinct levels of cache coherence.
1. Every write operation appears to occur instantaneously.
2. All processes see exactly the same sequence of changes of values for each
separate operand.
3. Different processes may see an operand assume different sequences of values
which is considered as non coherent behavior.
Key Words

 MSI: Modified Shared Invalid

 MESI: Modified Excusive Shared Invalid
 MOSI: Modified Owned Shared Invalid
 MOESI: Modified Owned Shared Invalid
 Snoopy Protocols, Cache Coherence.

MSI Low complexity

MESI Reduce #Broadcasts; Medium Complexity.

MOSI Reduce #Write –Backs; Medium Complexity
MOESI Reduce #Broadcast and #Write-Back; High complexity.
 For any given pair of caches, the permitted states of a given cache line are as follows:

Fig 1. MSI and MESI State Interchange and State Machine

MSI Write-Back Invalidate Protocol
 Three states are there in this type of protocol.
1. Modified: Only this cache has a modified valid copy of the block.
2. Shared: Block is clean and may be cached in more than one cache, memory is
up to date.
3. Invalid: Block is invalid.
Four buses are involved
1. Bus Read (BusRd)- on a read miss
2. Bus Read Exclusive(BusRdX)- Obtain exclusive copy of cache block.
3. Bus Write-Back(BusWB)- On replacement.
4. Flush on BusRd and BusRdX.
MESI WRITE-BACK INVALIDATION PROTOCOL

 This type of protocol is used to reduce two types of unnecessary bus

transaction. It introduces the exclusive state which one can write the
copy without generating BusRdX.
 Modified: Only this cache has copy and modified. Main memory copy
is stale. The cache is required to write the data back to the main
memory at some time in the future ,before permitting any other read of
the main memory state.
 Excusive: Only this cache has copy which is not modified. Main memory
is up-to-date. It present only in the current cache. It matches the main
memory. It may changed to shared in response to a read request and
alternatively it may be changed to Modified state when writing to it.
 Shared: More than one cache may have copies which are not
modified. It matches the main memory. The line may discarded
(changed to the invalid state ) at any time.
 Invalid: Indicates that this cache line is invalid (unused).
Cache coherence problems

Shared-memory multiprocessors offer increased computational power

and the programmability of the shared-memory model. However,
sharing memory between processors leads to contention which delays
memory accesses. Adding a cache memory for each processor
reduces the average access time, but it creates the possibility of
inconsistency among cached copies. The cache coherence problem
is keeping all cached copies of the same memory location identical.
As multiple processors operate in parallel, and independently multiple
caches may possess different copies of the same memory block, this
creates cache coherence problem. Cache coherence schemes help
to avoid this problem by maintaining a uniform state for each cached
block of data
 Before update Write-through
Write-Back

Processor
P1 P2 P1 P2 P1 P2

Cache

X X X1 X X1 X
Bus

Shared
Memory

X X1 X
 From the above figure let X be an element of shared data which has been
referenced by two processors, P1 and P2. In the beginning, three copies of X are
consistent. If the processor P1 writes a new data X1 into the cache, by
using write-through policy, the same copy will be written immediately into the
shared memory. In this case, inconsistency occurs between cache memory and
the main memory. When a write-back policy is used, the main memory will be
updated when the modified data in the cache is replaced or invalidated.
 The sources of inconsistency may be:
√ Sharing of writable data
√ Process migration
√ I/O activity
SNOOPY PROTOCOLS

 This protocol is used in a not scalable bus-based SMP system as broadcast

medium where all the processor can observe all memory access by cache
controller and then either invalidate or update the local cache content [4].
The Snoopy cache protocol is used in bus-based multiprocessor system this is
because they must use a broadcast medium bus. The bus-based multi-processor
allows for all connected processors to observe every bus transactions that mean
that each cache will monitor every memory transactions [2]. In bus based
multiprocessor systems, appropriate coherence actions can be taken if coherence
is detected. These are called snoopy protocols. Snoopy protocols achieve data
consistency between the cache memory and the shared memory through a bus-
based memory system. Write-Invalidate and Write-Update policies are used for
maintaining cache consistency. Snoopy protocols require the use of a broadcast
medium in the machine and hence apply only to small-scale bus-based
multiprocessors. This type of protocol is most commonly used method in
commercial multiprocessor. Various snoopy protocols have been proposed.
CONCLUSION

 This paper has studied various issues related to the cache memory
by analysis of cache coherence protocols. Cache memory is a
main component of memory hierarchy which plays an important
role in the overall performance of the system and in the design of
multicores. Multicores with shared memory architecture are used to
satisfy increasing performance demands, which in turns are limited
by cache coherence problem. Thus this survey focuses on the
subject of the use of a protocol to solve the problem of data match
and improve this protocol.
REFERENCES
 [1] Samaher Al-Hothali, Safeeullah Soomro and Khurram Tanvir Ruchi Tuli
- Snoopy and Directory Based Cache Coherence Protocols: A Critical
Analysis
 [2] Comparative study on Cache Coherence Protocols Kaushik Roy,
Pavan Kumar S.R, Meenatchi S.
 [3] JOUR- An Evaluation of Snoop-Based Cache Coherence Protocols:
Bigelow, Linda,Narasiman, Veynu,Suleman, Aater,2009/08/24
 [4] Alberto, R. and Alexandra, J. 2015. A Dual-Consistency Cache
Coherence Protocol, IEEE 29th International Parallel and Distributed
Processing Symposium IPDPS, pp: 1119-1128, USA
 [5] Hashemi, B., "Simulation and Evaluation Snoopy Cache Coherence
Protocols with Update Strategy in Shared Memory Multiprocessor
Systems," Parallel and Distributed Processing with Applications
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