energies

Article
A New Hybrid Multilevel Inverter Topology with
Reduced Switch Count and dc Voltage Sources
Hussain Mohammad Bassi 1, * and Zainal Salam 2
1 Department of Electrical Engineering at Rabigh, King Abdulaziz University, Jeddah 25732, Saudi Arabia
2 Centre of Electrical Energy Systems, Department of Electrical Power Engineering, Universiti Teknologi
Malaysia, 81310 Johor Bahru, Malaysia; zainals@utm.my
* Correspondence: hmbassi@kau.edu.sa




Received: 22 January 2019; Accepted: 8 March 2019; Published: 13 March 2019


Abstract: In this paper, a new single-phase hybrid multilevel inverter (MLI) is proposed. Compared
to other existing MLI topologies, the proposed circuit is capable of producing a higher number of
output voltage levels using fewer power switches and dc sources. The levels are synthesized by
switching the dc voltage sources in series/parallel combinations. An auxiliary circuit is introduced to
double the number of levels by creating an intermediate step in between two levels. In addition, a zero
level is introduced to overcome the inherent absence of this level in the original circuit. To improve the
total harmonic distortion, a hybrid modulation technique is utilized. The operation and performance
of the circuit are analyzed and confirmed using MATLAB/Simulink simulation. To validate the
workability of the proposed idea, a 300 W, a thirteen level MLI (including the zero level) is designed
and constructed. The circuit is tested with a no-load, resistive load and resistive-inductive load.
The experimental results match very closely with the simulation and mathematical analysis.

Keywords: multilevel inverter; dc-ac power converter; PWM technique; power conversion

1. Introduction
The growing demand for electrical energy along with the environmental concerns has increased
the prospects of renewable energy (RE) resources. These RE resources, particularly solar, wind,
ocean thermal, wave and fuel cells, require a power electronics converter to be compatible with
different applications. Inverters, which perform the dc-ac conversion are crucial equipment in domestic,
as well as industrial power system. The conventional two-level inverter is inadequate for high
voltage/power applications due to several drawbacks, which include high voltage rating of power
semiconductor devices (switches and/or power diodes) and high amount of total harmonic distortion
(THD). In certain high fidelity applications, it requires bulky inductors and capacitors to filter the
harmonics at the output.
A multilevel inverter (MLI) appears to be a better option as it can synthesize higher output
voltage waveform using much lower rated switches. With a higher number of levels, the output
voltage waveform comes close to the sinusoidal waveform, thus improving its THD. Consequently,
the inverter reduces the filter requirements. In addition, MLI also offers some additional advantages
such as lower voltage stress across switches, improved efficiency, reduced dv/dt stress, and lower
electromagnetic interference [1–5].
The popular conventional MLI topologies include the neutral point clamped (NPC), flying
capacitor (FC), and cascade H-bridge (CHB). Theoretically, the NPC can achieve any number of
levels at the cost of switches and clamping diodes, while for the FC a large number of capacitor is
needed. As for the CHB, higher voltage level is determined by the number of isolated dc voltage
sources. To overcome these drawbacks, extensive research has been carried out to search for new MLI

Energies 2019, 12, 977; doi:10.3390/en12060977 www.mdpi.com/journal/energies

Energies 2019, 12, x FOR PEER REVIEW 2 of 15
Energies 2019, 12, x FOR PEER REVIEW 2 of 15

Energies
overcome 12, 977drawbacks, extensive research has been carried out to search for new MLI topologies
2019,these 2 of 15
overcome these drawbacks, extensive research has been carried out to search for new MLI topologies
that require lower number of switches and dc voltage sources to achieve a higher output voltage
that require lower number of switches and dc voltage sources to achieve a higher output voltage
level. With respect to this aspect, several topologies have been proposed with symmetrical and
topologies
level. Withthat require
respect to lower number
this aspect, of switches
several and dc
topologies havevoltage
beensources
proposed to achieve a higher output
with symmetrical and
asymmetrical configurations. For the former, all the dc sources have the same magnitude, while for
voltage level. With
asymmetrical respect to this
configurations. Foraspect, several
the former, alltopologies
the dc sourceshave been
have proposed
the same with symmetrical
magnitude, whileandfor
the latter they are different. The asymmetrical topology produces more levels by using the same
asymmetrical
the latter theyconfigurations.
are different. For Thethe former, all the
asymmetrical dc sources
topology have the
produces samelevels
more magnitude,
by usingwhile thefor the
same
number of dc sources and switches compared to the symmetrical configuration [6,7].
latter
number they of are different.
dc sources andThe asymmetrical
switches compared topology
to theproduces
symmetrical more levels by using
configuration the same number
[6,7].
Another class of MLI is the hybrid type. Typically, it comprises two parts. The first part, called
of dcAnother
sources and classswitches
of MLI is compared
the hybrid to the symmetrical
type. Typically, itconfiguration
comprises two [6,7].
parts. The first part, called
the level generation, synthesizes the staircase voltage in unidirectional polarity. This is done by
Another
the level class of MLI
generation, is the hybrid
synthesizes type. Typically,
the staircase voltage it comprises two parts.
in unidirectional The firstThis
polarity. part,iscalled
done theby
switching the dc sources in a certain combination such that different levels are produced. The second
level generation,
switching the dc synthesizes
sources in a the staircase
certain voltage in
combination unidirectional
such that different polarity.
levels areThisproduced.
is done byThe switching
second
part is the polarity changing; it produces both positive and negative voltage across the load.
the
partdcis sources in a certain
the polarity changing;combination
it produces suchboth
that positive
differentand levels are produced.
negative voltage The second
across part
the load.
Generally, an H-bridge inverter is used for this purpose. Figure 1 shows the single-phase hybrid MLI
is the polarity
Generally, changing;
an H-bridge it produces
inverter is used both
for positive
this purpose.and negative voltagethe
Figure 1 shows across the load.hybrid
single-phase Generally,
MLI
proposed by Hinago and Koizumi [8]. In this topology, the dc voltage sources can be connected in
an H-bridge
proposed byinverter
Hinago is used
and for this[8].
Koizumi purpose.
In thisFigure
topology, 1 shows
the dcthevoltage
single-phase
sourceshybrid
can beMLI proposed
connected in
series to produce all the additive combinations. Furthermore, they can also be connected in parallel,
by Hinago
series and Koizumi
to produce [8]. In this
all the additive topology, the
combinations. dc voltage they
Furthermore, sources
can canalsobebeconnected
connected in in series to
parallel,
which enhances the flexibility of voltage and current requirement at the output. Correspondingly, it
produce all the additive
which enhances combinations.
the flexibility of voltageFurthermore, they can also
and current requirement atbetheconnected in parallel, which
output. Correspondingly, it
is termed a switched series/parallel sources (SSPS) MLI. Another topology based on series connected
enhances the flexibility of voltage and current requirement at the output.
is termed a switched series/parallel sources (SSPS) MLI. Another topology based on series connectedCorrespondingly, it is termed
switched sources (SCSS) has been presented in [9]. As shown in Figure 2a, this topology does not
aswitched
switchedsources
series/parallel
(SCSS) has sources
been(SSPS) MLI.in
presented Another
[9]. Astopology
shown inbased Figure on2a,
series
thisconnected
topology switched
does not
have the feature of combining two voltage sources in parallel. Therefore, this topology does not
sources
have the(SCSS)
feature has
of been presented
combining twoinvoltage
[9]. Assources
shown in in parallel.
Figure 2a, this topology
Therefore, does not have
this topology the
does not
possess the load sharing capability. Furthermore, it generates a lesser number of levels compared to
feature
possess of thecombining
load sharing twocapability.
voltage sources in parallel.
Furthermore, Therefore,
it generates this topology
a lesser number of does notcompared
levels possess the to
the SSPS for the same number of dc sources. Another hybrid topology based on the SCSS is proposed
load sharing
the SSPS capability.
for the Furthermore,
same number it generates
of dc sources. Another a lesser
hybrid number
topologyof levels
basedcompared
on the SCSS to the SSPS for
is proposed
in [10]; it is shown in Figure 2b. This topology is based on the half-bridge which includes one dc
the sameitnumber
in [10]; is shown of in
dc Figure
sources. 2b.Another hybrid topology
This topology is based on based
theon the SCSS is
half-bridge proposed
which in [10];
includes oneitdcis
source and two switches. Several such half bridges can be connected to achieve more output voltage
shown in Figure
source and 2b. This topology
two switches. Several suchis based on the half-bridge
half bridges which includes
can be connected to achieve one dc source
more outputand two
voltage
levels.
switches.
levels. Several such half bridges can be connected to achieve more output voltage levels.

S3k-3 Vk
S3k-3 S3k-4 Vk
S3k-4

S3k-6 S3k-5
S3k-6 S3k-7Vk-1 S3k-5 H1 H3
S3k-7Vk-1 H1 H3
+ Vo -
S6 S3k-8 +LOAD
Vo -
S6 S5 Vk-2 S3k-8
S5 Vk-2 LOAD

H2 H4
S3 V2 S4 H2 H4
S3 S2 V2 S4
S2

V1 S1
V1 S1

Figure 1. The hybrid MLI proposed in [8].

Figure 1. The hybrid MLI proposed in [8].

S2k S2k
S2k S2k

S2k-1 Vk S2k-1
S2k-2 Vk S2k-1 Vk S2k-1
S2k-2 Vk
H1 H3 S2k-2 H1 H3
H1 H3 S2k-2 H1 H3
S2k-3
S4 Vk-1 S2k-3 + Vo - + Vo -
S4 Vk-1 +LOAD
Vo - Vk-1 S2k-3 +LOAD
Vo -
LOAD Vk-1 S2k-3 LOAD

S2 V2 S3
S2 V2 S3 H2 H4 S2
S2
H2 H4
H2 H4 H2 H4

V 1 S1 V1 S1
V 1 S1 V1 S1

(a) (b)
(a) (b)
Figure 2. The MLI topologies proposed in (a) [9] and (b) [10].
Figure 2. The MLI topologies proposed in (a) [9] and (b) [10].
Figure 2. The MLI topologies proposed in (a) [9] and (b) [10].
Other alternatives for hybrid MLI are shown in Figure 3a–d [11–14]. All these topologies require
Other alternatives
an additional for
dc sourcefor hybrid
prior MLI
to the are shown
H-bridge. in Figure
They 3a–d
directly [11–14].
connect All
the these
dcthese topologies
voltage require
sourcesrequire
to the
Other alternatives hybrid MLI are shown in Figure 3a–d [11–14]. All topologies
an additional
H-bridge dc
withoutsource prior
usingprior to the
any switch H-bridge. They
as shown They directly
in Figure connect
3a–c. the
In thisthe dc
type voltage sources to the H-
an additional dc source to the H-bridge. directly connect dc of arrangement,
voltage the
sources to thezero
H-
Energies 2019,
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bridge without using any switch as shown in Figure 3a–c. In this type of arrangement, the zero
voltage level is
is generated
generatedby byusing
usingtwo
twoswitches
switchesofofthetheH-bridge.
H-bridge.Due Dueto to
this, thethe
this, switches
switchesof the H-
of the
bridge dodo
H-bridge notnotoperate
operateatatthe
thefundamental
fundamentalswitching
switchingfrequency.
frequency. In In addition,
addition, thethe voltage
voltage source
connected just
justbefore
beforethe
theH-bridge
H-bridgeis is
highly
highlystressed as it
stressed asisitinvolved in allinvoltage
is involved levelslevels
all voltage exceptexcept
zero.
This problem
zero. is eliminated
This problem by making
is eliminated by makingthe the
voltage source
voltage source V11V11
a half
a halfbridge
bridgeby byadding
adding two
two more
switches as shown in Figure 3d [14]. Therefore, with this structure, the number of levels levels is doubled,
doubled,
available, one
as there are two connections available, one without
without dc dc voltage
voltage source
source V
V1111 and other with V11 11..

Sk+1

S2k V11
Vk
V11 Sk
S2k-1 H1 H3 H1 H3
S4 Vk
+ Vo -
+ Vo - Vk-1
LOAD
LOAD S2
S2 V2 S3
H2 H4
H2 H4 V1 S1
V1 S1

(a) (b)
S11

V11
S22
Sk+1 V11
Vk V3
Sk S3
H1 H3
H1 H3
+ Vo - V2
Vk-1
LOAD S4 S5 + Vo -
S2 S2 LOAD

H2 H4 V1
V1 H2 H4
S1 S1

(c) (d)

Figure 3. The hybrid MLI topologies proposed in (a) [11]; (b) [12]; (c) [13]; and (d) [14].
Figure 3. The hybrid MLI topologies proposed in (a) [11]; (b) [12]; (c) [13]; and (d) [14].
Several topologies have been proposed that are able to generate both polarities of the output
Several topologies have been proposed that are able to generate both polarities of the output
voltage without using any polarity changing circuit. One such MLI has been proposed in [15,16],
voltage without using any polarity changing circuit. One such MLI has been proposed in [15,16],
which is known as the packed U cell (PUC) MLI. However, the PUC requires a large variety of dc
which is known as the packed U cell (PUC) MLI. However, the PUC requires a large variety of dc
sources because the voltage levels are mainly generated by subtraction of two or more sources. Another
sources because the voltage levels are mainly generated by subtraction of two or more sources.
MLI topology based on cascaded bipolar switched cells (CBSC) has been proposed in [17]. In the CBSC
Another MLI topology based on cascaded bipolar switched cells (CBSC) has been proposed in [17].
MLI, all the switches need to be of bidirectional nature, which increases the complexity significantly.
In the CBSC MLI, all the switches need to be of bidirectional nature, which increases the complexity
In addition, the switches suffer from higher blocking voltages. Other similar topologies have been
significantly. In addition, the switches suffer from higher blocking voltages. Other similar topologies
discussed in [18–25].
have been discussed in [18–25].
This paper recommends a new hybrid MLI topology, which combines the merits of the hybrid
This paper recommends a new hybrid MLI topology, which combines the merits of the hybrid
topologies discussed above. The silent features of the proposed topology are:
topologies discussed above. The silent features of the proposed topology are:
a. The proposed MLI utilizes fewer switches to generate a higher number of levels.
a. The proposed MLI utilizes fewer switches to generate a higher number of levels.
b. It also allows for parallel operation of the different dc voltage sources, thus allowing load
b. It also allows for parallel operation of the different dc voltage sources, thus allowing load
sharing among different dc voltage sources. This results in equal loading stress across each dc
sharing among different dc voltage sources. This results in equal loading stress across each dc
voltage source
voltage source
c.
c. The Thehigher
highernumber
numberof oflevels
levelsisisachieved
achieved by
by incorporating
incorporating an
an auxiliary
auxiliary module
module between
betweenthe
thelevel
generation and polarity changing parts.
level generation and polarity changing parts.
d. The zero level is obtained by introducing a switching scheme at the polarity changing circuit.
Energies 2019, 12, 977 4 of 15

Energies 2019, 12, x FOR PEER REVIEW 4 of 15

d. The zero level is obtained by introducing a switching scheme at the polarity changing circuit.
e.
e. The
Theproposed
proposedtopology
topologyisiscapable
capableofofhandling
handlinginductive
inductiveloads.
loads.
This paper is
This paper is structured
structured asas follows.
follows. Section
Section 22 explains
explains the
the generalized
generalized arrangement
arrangement of the
of the
proposed topology along with the working principle. Selection of magnitude of dc
proposed topology along with the working principle. Selection of magnitude of dc voltage sources voltage sources
along
along with total standing
with total standing voltage
voltage calculation
calculation is also covered
is also covered in
in Section
Section 2.
2. A
A comparative
comparative study
study with
with
different MLI topologies has been presented in Section 3. Section 4 explains the hybrid
different MLI topologies has been presented in Section 3. Section 4 explains the hybrid modulation modulation
technique usedininthis
technique used thispaper.
paper. Section
Section 5 describes
5 describes the the simulation
simulation and and experimental
experimental results
results and
and the the
paper
paper is summarized
is summarized in Section
in Section 6. 6.

2.
2. The
The Proposed
Proposed Multilevel
Multilevel Inverter
Inverter

Topology
2.1. Generalized Structure of the Topology
The proposed
proposed hybrid
hybridmultilevel
multilevelinverter topology
inverter is shown
topology in Figure
is shown 4. It4.consists
in Figure of three
It consists parts
of three
i.e., the
parts i.e.,level generation
the level module
generation (LGM),
module the auxiliary
(LGM), module
the auxiliary (AM)(AM)
module and the
andpolarity changer
the polarity unit
changer
(PCU).
unit (PCU).

AM Sa1

Sa2Va
S3k Vdc
S3k-1

Vdc S3k-2 H1 H3

S6 + Vo -
S5
PCU LOAD

S3 Vdc S4
S2 H2 H4

Vdc S1

Figure 4.
Figure The generalized
4. The generalized structure
structure of
of the
the proposed
proposed multilevel
multilevel inverter
inverter topology.
topology.

2.1.1. The Level Generation Module (LGM)

2.1.1. The Level Generation Module (LGM)
The LGM is built based on the interconnection of k number of cells (k is an integer). Each cell
The LGM is built based on the interconnection of k number of cells (k is an integer). Each cell
comprises three unidirectional switches and one dc voltage source. The main function of the LGM
comprises three unidirectional switches and one dc voltage source. The main function of the LGM is
is to generate all the additive combinations of different dc sources of same magnitude; therefore,
to generate all the additive combinations of different dc sources of same magnitude; therefore, the
the staircase waveform is generated at its output. This is done by utilizing the switches such that the
staircase waveform is generated at its output. This is done by utilizing the switches such that the
voltage sources of two cells can be connected in series or parallel. For example, if switches S1 and
voltage sources of two cells can be connected in series or parallel. For example, if switches S1 and S3
S3 are turned ON, the two dc voltage sources will be connected in parallel in Vdc at the output of
are turned ON, the two dc voltage sources will be connected in parallel in Vdc at the output of LGM.
LGM. Thus, both cells share the load equally. If switch S2 is turned ON, two dc voltage sources will be
Thus, both cells share the load equally. If switch S2 is turned ON, two dc voltage sources will be
connected in series with additive polarity and 2V appears at the output of LGM.
connected in series with additive polarity and 2Vdc dc appears at the output of LGM.
Similarly, several dc voltage sources can be operated in series and parallel combinations to share
Similarly, several dc voltage sources can be operated in series and parallel combinations to share
the load with different voltage levels. The pair of switches (S , S ) and (S , S ) should be operated in
the load with different voltage levels. The pair of switches (S11, S22) and (S22, S33) should be operated in
complementary to avoid the short-circuiting of voltage source V . A similar operation is required for
complementary to avoid the short-circuiting of voltage source V11. A similar operation is required for
the kth cell. Moreover, all switches in the LGM operate at low frequency. However, it has to be noted
the kth cell. Moreover, all switches in the LGM operate at low frequency. However, it has to be noted
that the LGM cannot produce a zero level at the output because the parallel/series combination of
that the LGM cannot produce a zero level at the output because the parallel/series combination of the
dc sources will always result in a certain voltage at the output (unless the sources are set to zero,
which does not make any sense). Since there is no instant when the output is not connected to the
source, the zero level cannot exist at the output at any time.
Energies 2019, 12, 977 5 of 15

the dc sources will always result in a certain voltage at the output (unless the sources are set to zero,
which does not make any sense). Since there is no instant when the output is not connected to the
Energies 2019, 12, x FOR PEER REVIEW 5 of 15
source, the zero level cannot exist at the output at any time.
2.1.2.
2.1.2. The
The Auxiliary
Auxiliary Module
Module (AM)
(AM)
To generate higher
To generate higher number
number of
of levels
levels at
at the
the output,
output, an an auxiliary
auxiliary module
module (AM)
(AM) isis connected
connected after
after
the LGM. This module comprises one dc voltage source V a and two unidirectional switches Sa1 and
the LGM. This module comprises one dc voltage source Va and two unidirectional switches Sa1 and
S
Sa2 . Both switches need to be operated in a complementary mode to avoid short-circuiting of voltage
a2 . Both switches need to be operated in a complementary mode to avoid short-circuiting of voltage
source
source V Va.. When Sa2 is turned ON, the same voltage level generated by the LGM is connected at the
a When Sa2 is turned ON, the same voltage level generated by the LGM is connected at the
output.
output. WhenWhen SSa1a1isisturned
turnedON,ON,the
thevoltage
voltagesource
sourceVV a is added to the level generated by the LGM. If
a is added to the level generated by the LGM.
the magnitude of V a is selected to be half of the dc sources, an intermediate level is formed halfway
If the magnitude of Va is selected to be half of the dc sources, an intermediate level is formed halfway
in between two
in between two levels.
levels. OnOn the
the other
other hand,
hand, if
if V
Vaa equals
equals the the dc
dc sources,
sources, no
no additional
additional level
level is
is formed.
formed.
Other values of V a result in an unequal intermediate step, which is not desirable. The AM is also used
Other values of Va result in an unequal intermediate step, which is not desirable. The AM is also
to construct
used the PWM
to construct waveform.
the PWM Switches
waveform. Sa1 and
Switches Sa1Sa2
andareSmodulated similar to the conventional (two-
a2 are modulated similar to the conventional
level) inverter.
(two-level) inverter.

2.1.3.
2.1.3. Polarity
Polarity Changing
Changing Unit
Unit (PCU)
(PCU)
The
The combination
combination of ofthe
theLGM
LGMandandAM
AMgenerates
generates thethe
voltage levels
voltage in positive
levels polarity
in positive only.
polarity To
only.
achieve both positive and negative voltage levels at the output, a standard H-bridge is
To achieve both positive and negative voltage levels at the output, a standard H-bridge is used as used as a
polarity changing
a polarity changingunit. Another
unit. function
Another of the
function ofPCU is to generate
the PCU the zero
is to generate thevoltage level at level
zero voltage the output.
at the
This is achieved by simultaneously holding the H and H ON for a certain amount of time.
output. This is achieved by simultaneously holding the H2 and H4 ON for a certain amount of time.
2 4

2.2. Working Principles

The operating
operating principle
principleofofthe
theproposed
proposedMLIMLIis isexplained
explainedwith two
with cells
two (k =(k2)=in2)the
cells in LGM. For
the LGM.
the
For twothe twocells,cells,
the the topology usesuses
topology 12 switches andand
12 switches fourfour
dc sources, as shown
dc sources, as shown in Figure
in Figure 5. In
5. order to
In order
achieve
to achieve parallel
parallel operation of different
operation dc dc
of different voltage
voltage sources
sourcesconnected
connectedto the LGM,
to the LGM, thethe
magnitudes
magnitudes of
V
of1,VV1 ,2,Vand
2 , V
and 3 must
V 3 be
must equal.
be Furthermore,
equal. Furthermore,the pair
the of
pair switches
of of
switches each
of eachcell should
cell should operate
operatein a
in
complementary
a complementarymode modetotoavoid
avoidshort-circuiting
short-circuitingof ofthe
thedcdcsources.
sources.The
Theswitch
switch pairs
pairs of
of the
the cell include
(S11,, S22)) and
and (S(S22,, SS33).).The
Theswitching
switchingsequences
sequencesof of the
the parallel
parallel operation
operation and
and complementary
complementary pairs are
given in Table 1. 1.

AM Sa1

Sa2Va
S6 Vdc
S5 H1 H3
+ Vo -
S3 Vdc S4 PCU
LOAD
S2
H2 H4
Vdc S1

Figure 5.
Figure The proposed
5. The proposed MLI
MLI topology
topology with
with two
two cells.
cells.

Table 1. Switching table with two cells.

S1/S3 S2 S4/S6 S5 Sa1 Sa2 H1 H2 H3 H4 Vo

0 0 0 0 0 0 0 1 0 1 0
1 0 1 0 0 1 1 0 0 1 Vdc
1 0 1 0 1 0 1 0 0 1 Vdc+ Va
0 1 1 0 0 1 1 0 0 1 2Vdc
0 1 1 0 1 0 1 0 0 1 2Vdc + Va
0 1 0 1 0 1 1 0 0 1 3Vdc
0 1 0 1 1 0 1 0 0 1 3Vdc + Va
Energies 2019, 12, 977 6 of 15

Table 1. Switching table with two cells.

S1 /S3 S2 S4 /S6 S5 Sa1 Sa2 H1 H2 H3 H4 Vo

0 0 0 0 0 0 0 1 0 1 0
1 0 1 0 0 1 1 0 0 1 Vdc
1 0 1 0 1 0 1 0 0 1 Vdc + Va
0 1 1 0 0 1 1 0 0 1 2Vdc
0 1 1 0 1 0 1 0 0 1 2Vdc + Va
0 1 0 1 0 1 1 0 0 1 3Vdc
0 1 0 1 1 0 1 0 0 1 3Vdc + Va
0 0 0 0 0 0 1 0 1 0 0
1 0 1 0 0 1 0 1 1 0 −Vdc
1 0 1 0 1 0 0 1 1 0 −(Vdc + Va )
0 1 1 0 0 1 0 1 1 0 −2Vdc
0 1 1 0 1 0 0 1 1 0 −(2Vdc + Va )
0 1 0 1 0 1 0 1 1 0 −3Vdc
0 1 0 1 1 0 0 1 1 0 −(3Vdc + Va )

2.3. Selection of dc Source Magnitudes

The number of levels at the output is decided by the magnitude of dc voltage sources connected in
LGM and AM. For the parallel operation of the proposed MLI, the magnitude of dc sources connected
in LGM must be the same. If the magnitude is not equal, the anti-parallel diode connected to an IGBT
will conduct, which leads to the short-circuiting of different voltage sources. The MLI can operate in
two modes. The magnitude of voltage sources of the AM, i.e., Va determines these modes.

2.3.1. Mode I
Mode I can be considered symmetrical configuration. In this mode, the magnitude of each dc
source, including the dc source in the AM, is selected as Vdc . Therefore,

Va = Vdc (1)

The number of levels (N) at the output is given as

N = 2(k + 1) (2)

2.3.2. Mode II
A higher number of levels can be realized at the output by changing the magnitude of Va (inside
the AM) to Vdc /2. The dc sources connected in LGM remain as before, i.e., each voltage source has
a magnitude of Vdc . Using these dc voltages, the number of levels increases to

N = 4(k + 1) (3)

If the zero level generator is activated, N increases by one more step, i.e.,

N = 4(k + 1) + 1 (4)

The number of switches used in the proposed topology is given by

NIGBT = 3(k + 2) (5)

Since all switches are unidirectional, the same number of the driver circuit is required.
Energies 2019, 12, 977 7 of 15

2.4. Total Standing Voltage Calculation

The voltage stresses across the switches play an important role in the selection of the power
devices. Total standing voltage (TSV) is defined as the sum of maximum voltage stress across all
power semiconductor devices considering all voltage levels. The TSV of the proposed topology can be
written as
TSV = TSVLGM + TSVAM + TSVPCU (6)

where TSVLGM , TSVAM and TSVPCU represent the TSV of the LGM, AM, and PCU, respectively.
The maximum voltage stress across each switch connected in LGM is equal to the magnitude of voltage
sources. Therefore
TSVLGM = 3 × k × Vdc for Mode I and II (7)

The voltage stresses across Sa1 and Sa2 are fixed by the magnitude of voltage source Va . Therefore,

TSVAM = 2 × Vdc for Mode I (8)

and
TSVAM = 2 × 0.5Vdc for Mode II (9)

The maximum voltage stress across switches connected in PCU is the sum of all the dc voltage
sources connected in the topology. Hence, the TSV of PCU is given by

TSVPCU = 4(k + 2) × Vdc for Mode I (10)

and
TSVPCU = 4(k + 1.5) × Vdc for Mode II (11)

The TSV of the overall proposed topology is calculated by adding the TSV of all there parts for
both modes of operation. From (7)–(11),

TSV = (7k + 10) × Vdc for Mode I (12)

and
TSV = 7(k + 1) × Vdc for Mode II (13)

Hence, for mode I,

7
TSV = (N + 3) × Vdc (14)
2
and, for Mode II,
7
TSV = N × Vdc (15)
4

3. Comparative Study
A comparison is made regarding the number of switches, number of dc voltage sources, TSV and
variety of dc voltage sources in terms of number of levels. Four similar topologies, i.e., the SSPC, SCSS,
PUC, and CBSC MLI, are considered. Figure 6a shows the comparison of the number of switches with
respect to the number of levels at the output. From this figure, it is clear that the proposed topology
in Mode II requires the least number of switches (for up to 20 levels) compared to other topologies.
Furthermore, the proposed topology in Mode I requires fewer switches than CBSC and SSPS topologies.
Figure 6b compares the number of dc voltage sources against the number of levels. The proposed
topology in Mode II requires a lower number of dc voltage sources, except for PUC. Figure 6c displays
the comparison of TSV with respect to the number of levels. When operated in Mode II, the proposed
topology has lower TSV than PUC, CBSC and SCSS MLI. In addition, Figure 6d shows the variation
of dc voltage sources requires for number of levels at the output. The proposed topology in Mode I
Energies 2019, 12, 977 8 of 15

requires one variety of the dc voltage source (i.e., one value for all dc sources). In Mode II, it requires
two varieties because the Va2 is set to half of Vdc . This is much lower than the variety of dc voltage
sources required for the PUC MLI. Overall, the reduced number of switches and dc voltage sources
along with
Energies lower
2019, TSVPEER
12, x FOR are REVIEW
the main advantages of the proposed topology. 8 of 15

120 SSPS 30
SSPS
Number of Switches

SCSS

Number of Sources
25 SCSS
PUC PUC
80 CBSC 20 CBSC
MODE I MODE I
MODE II 15
MODE II
40 10
5
0 0
0 10 20 30 40 50 0 10 20 30 40 50
Number of Levels Number of Levels
(a) (b)

1000 20
SSPC PUC
750 SCSS Variety of Sources MODE I, SSPC, SCSS, & CBSC
TSV (×Vdc)

PUC
CBSC Mode II
500 10
MODE I
250 MODE II

0 0
0 10 20 30 40 50 0 10 20 30 40 50
Number of Levels Number of Levels
(c) (d)

Figure 6. Comparing the proposed MLI with others in literature (a) number of switches; (b) number
Figure 6. Comparing the proposed MLI with others in literature (a) number of switches; (b) number
of dc sources; (c) total standing voltage (TSV) and (d) variety of dc voltage sources with respect to
of dc sources; (c) total standing voltage (TSV) and (d) variety of dc voltage sources with respect to
number of levels.
number of levels.
4. Modulation Technique
4. Modulation Technique
In this paper, the hybrid modulation technique is utilized [8,26]. To illustrate the technique,
In this
a six-level MLIpaper, the hybrid
is used. modulation
The modulation is technique
divided into is utilized [8,26].
two parts. To the
First, illustrate the technique,
large pulses to drive a
the LGM switches. This is shown in Figure 7a. It comprises three square waves, each havingdrive
six-level MLI is used. The modulation is divided into two parts. First, the large pulses to a peakthe
LGM switches.
magnitude of (1/3.5)Thispu.is The
shown in Figure
negative portion 7a. has
It comprises
a magnitude three(−square
1/3.5) pu.waves,
Theseeach having
square waves a peak
are
magnitude of (1/3.5) pu. The negative portion has a magnitude (−1/3.5) pu.
used to establish the essential part of the sinusoidal reference signal in the positive and negative half These square waves are
used to establish the essential part of the sinusoidal reference signal in the
cycles. For the positive half cycle, the lower square wave is placed between 0 and tπ . In the negative positive and negative half
cycles.
half For
cycle, thethe positive
similar squarehalfwave
cycle,isthe lowerbetween
located square wavetπ andistplaced between 0 and t . In the negative
2π . In Figure 7a, the AM circuit is meant
half cycle, the similar square wave is located between
to modulate the area in blue. Therefore, the control circuit subtracts. the t and t In Figure
sinusoidal7a, the AM circuit
reference waveis
meant to modulate the area in blue. Therefore, the control circuit subtracts
from the black and grey blocks. The result of this subtraction can be shown in Figure 7b as a blue curve the sinusoidal reference
wave
that fromfrom
ranges the black
−1.14and greyThis
to 1.14. blocks.
curve The is result
modulatedof this subtraction
with can be
two carriers, theshown in Figure
green and the red7bone.
as a
blue curve that ranges from −1.14 to 1.14. This curve is modulated with
The comparison of the lower square wave and sinusoidal reference signal gives the gate pulses for two carriers, the green and
the red one.
switches S1 and TheS2comparison
of the LGM.ofInthe thelower
same square
way, the wave and sinusoidal
comparison of otherreference
square wavessignalgenerates
gives the the
gate
pulses for switches S
gate pulses for other LGM switches.
1 and S 2 of the LGM. In the same way, the comparison of other square waves
generates
For thethe gate pulses
generation for other
of gate pulsesLGM
of AM, switches.
a differentiated reference signal is created and is shown
For 7b.
in Figure the The
generation of gate reference
differentiated pulses of AM, single a differentiated reference
is created by locating signal
the area is created
which andcommon
is not is shown
in Figure 7b. The differentiated reference single is created by locating
between sinusoidal reference single and square waves. Each such portion of the sinusoidal signal the area which is not common is
between sinusoidal reference single and square waves. Each such portion
placed between (1/3.5) pu and (−1/3.5) pu. This differentiated reference signal is then compared of the sinusoidal signal
withis
a placed
carrier between
signal to(1/3.5)
generate pu and
gate(−1/3.5)
pulses for pu. switches
This differentiated
of AM. The reference signal
overall gate is thengenerated
signals comparedfrom with
a carrier signal to generate gate pulses for switches of AM. The overall
this modulation scheme are summarized in Figure 8. These signal labels are consistent with the circuit gate signals generated from
this modulation
shown in Figure 5.scheme are summarized in Figure 8. These signal labels are consistent with the circuit
shown in Figure 5.
Energies 2019, 12, 977 9 of 15
Energies 2019, 12, x FOR PEER REVIEW 9 of 15
Energies 2019, 12, x FOR PEER REVIEW 9 of 15

Figure 7. (a) The hybrid modulation technique and (b) differentiated gate signals with carrier signals.
Figure7.7.(a)
Figure (a)The
Thehybrid
hybridmodulation
modulation technique
technique and (b) differentiated gate signals
signals with
with carrier
carriersignals.
signals.

(a) (e)
(a) (e)

(b) (f)
(b) (f)

(c) (g)
(c) (g)

(d) (h)
(d) (h)
Time (s) Time (s)

8. 8.(a) Time (s) Time (s) pulses for S , (LGM);

Figure
Figure (a)gate
gatepulses
pulses for (LGM);(b)
for S11 (LGM); (b)gate
gatepulses
pulses
forfor S2 (LGM);
S2 (LGM); (c)
(c) gate gate
pulses for S4, (LGM);
4 (d)
(d) gatepulses
gate
Figure 8.pulses forSpulses
for
(a) gate 5S(LGM);
5 (LGM);
for(e)S(e) gate
gate pulses
pulses for for
Sa1 S
1 (LGM); (b) gate pulses a1 (AM);
(AM); (f) (f)
forgate gate pulses
pulses
S2 (LGM); for for
(c) Sgate Spulses
a2 (AM);
a2 (AM); (g)for(g)
gate , gate
S4pulses pulses
(LGM);for(d)
H
for H (PCU);
11 (PCU); andand(h) gate
(h) pulses
gate pulsesfor H
for3 (PCU)
H (PCU).
.
gate pulses for S5 (LGM); (e) gate pulses for Sa1 (AM); (f) gate pulses for Sa2 (AM); (g) gate pulses for
3

H1 (PCU); and (h) gate pulses for H3 (PCU).

5. Results and
5. Results andDiscussion
Discussion
5. Results
5.1. and Discussion
Simulation
5.1. SimulationResults
Results
TheTheperformance
5.1. Simulation Results ofof proposed
performance proposed MLI MLI and and its its modulation
modulation strategy strategy isis simulated
simulatedusing using
Matlab/Simulink. cells are used (i.e., k
Matlab/Simulink. Two cells are used (i.e., k = 2) for the simulation results. Therefore, three dc voltage dc
Two = 2) for the simulation results. Therefore, three
voltageThesources
performance
are connected of proposed MLI and its modulation strategy is(Modes
simulated using
sources are connected to LGMto LGMahaving
having magnitude a magnitude
of 30 V. Both of 30modesV. Both modes
(Modes I and I and II)
II) are simulated are
Matlab/Simulink.
simulated Two
at a modulation
at a modulation
cells
index of 1.14.
are
index used
Forof
(i.e., k =
1.14.I, For
Mode
2) for
Va = Mode
the
Vdc = 30I,V,
simulation
Vawhile
= Vdc results.
for=Mode
30 V, II,Therefore,
while for Mode
it is half
three dc voltage
II, it15isV.
of Vdc, i.e., half
sources
of The are 15
i.e., connected
Vdc ,simulation V. The to LGMwith
is performed
simulation having a magnitude
is aperformed
carrier withof
frequency aof30 V.kHz.
7.5
carrier Both modes
The
frequency (Modes
square wave
of 7.5 Ipulses
kHz.andThe II)for
are simulated
the
square LGMwave
at and
a modulation
pulses PWM
for thefor LGM index
theand AM ofPWM
1.14.generated
are Forthe
for Mode AM I,are
usingVa =theVdcmodulation
= 30 V,
generated while
using formodulation
technique
the Mode II, it technique
described is half of Vdescribed
in Section dc, i.e., 15 V.
4. For in
The simulation
convenience,
Section is performed
the simulation
4. For convenience, with
the is a carrier
done under
simulation frequency
a no-load
is done of 7.5 kHz.
under condition The
a no-load because square
condition wave
ofbecause pulses
the emphasis for the
on the
of the emphasis LGM
and PWM
oncorrectness for
the correctness the AM
of theofgeneratedare generated
the generated waveforms. using
waveforms. the modulation
The performance
The performance technique
with loadwith(R described
and(RRL)
load and will in Section
RL)bewill
dealtbein 4.
theFor
dealt in
convenience,
experimental the simulation
section.
the experimental section. is done under a no-load condition because of the emphasis on the
correctness
TheThe of the
output
output generated
voltage
voltage ofofthewaveforms.
the MLIin
MLI inMode
Mode TheII is
performance
is shown
shown in with 9a.
in Figure
Figure load
9a.As As(R and RL)the
expected,
expected, will
the be dealt
output
output in the
voltage
voltage
experimental
waveform issection.
of the staircase type as the switches of LGM operate
waveform is of the staircase type as the switches of LGM operate at the fundamental frequency. As at the fundamental frequency. Ascan
canThe
be observed
output from Figure 9a, thein number of
I islevels is 6,inwhich is consistent with Equation (2). Since
be observed fromvoltage
Figure of 9a,the
theMLInumber Mode
of levels shown
is 6, which Figure 9a. As expected,
is consistent with Equation the output voltage
(2). Since the
the dc source
waveform is of is
the30staircase
V, the generated
type as levels
the are 30, 60
switches of and
LGM 90operate
V. Furthermore,
at the the output voltage
fundamental frequency. doesAs
dc source is 30 V, the generated levels are 30, 60 and 90 V. Furthermore, the output voltage does not
cannot
beahave a zero level,Figure
observed which9a, is inherent to the topology is 6,when operated in Mode I. Figure 9b (2).
shows
have zero level,from which is inherent the number of levels
to the topology when which
operated is consistent
in Modewith Equation
I. Figure 9b shows Since
the
the harmonics
the dc source spectrum
is 30 V,without without
the generated filtering.
levels The computed THD is 15.5%.
harmonics spectrum filtering. The are 30, 60 and
computed THD 90isV.15.5%.
Furthermore, the output voltage does
not have a zero level, which is inherent to the topology when operated in Mode I. Figure 9b shows
the harmonics spectrum without filtering. The computed THD is 15.5%.
Energies 2019, 12, x FOR PEER REVIEW 10 of 15

Energies 2019, 12, x FOR PEER REVIEW 10 of 15

Energies 2019, 12, x FOR PEER REVIEW 10 of 15
Energies 2019, 12, 977 100
10 of 15
100

50 80
(V)

(V) Mag (V)

100 100
0 60
100
(V)Voltage

agVoltage
100
50 80
(V)

-50 40
80
50
60

(V)
0
Voltage

Voltage
MagM
-100 20
60
0
Voltage

Voltage
-50 40
0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04 0
40
-50 0 Time (s) 20
0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000
-100 Frequency (Hz)
-100 20
0 (a)0.02 0.025 0.03 0.035 0.04
0.005 0.01 0.015 0
0
(b)
1000 2000 3000 4000 5000 6000 7000 8000 9000 10000
Time 0.025
(s) 0.03 0.035 0.04 0 Frequency
0 0.005 0.01 0.015 0.02 0 1000 2000 3000 4000 5000 (Hz)
6000 7000 8000 9000 10000
Time (s) Frequency (Hz)
Figure 9. Output(a)of the MLI in Mode I under no-load condition (a)(b) Voltage waveform (b) its
(a)
corresponding harmonics spectra. THD is 15.5%.
(b)
Figure 9. Output
Figure 9. Output ofof the
the MLI
MLI inin Mode
Mode II under
under no-load
no-load condition
condition (a)
(a) Voltage
Voltage waveform
waveform (b)
(b) its
its
Figure 9. Output of the spectra.
MLI in THDModeisI15.5%.
under no-load condition (a) Voltage waveform (b) its
When the AMharmonics
corresponding
corresponding is enabled,
harmonics i.e., Mode
spectra. THD II, additional levels are created. This is shown in Figure 10a.
is 15.5%.
corresponding harmonics spectra. THD is 15.5%.
According to Equation (3), the number of levels is increased to twelve. Since Va = 0.5 Vdc, the new
levelsWhen
When the
the AM
are located AMatis enabled,
is45, 75 andi.e.,
enabled, 105Mode
i.e., Mode II,
II, additional
additional
V. Furthermore, levels
theare
levels
since are
zerocreated.
created. This
This is
level generators isshown
shown in
inFigure
are not Figure 10a.
10a.
activated,
When
According the AM is enabled, i.e., Mode II, additional levels are created. This is shown in Figure 10a.
this level isto
According to Equation
Equation
absent (3),
from(3), the
thethe number of
number
waveform. of levels
Modelevels is increased
is
II with increased
the zeroto to twelve.
twelve.
level Sincein
Since
is shown VaaFigure
V = 0.5
= 0.5 VV dc,, the
11a.
dc the new
new
Figures
According
levels are to Equation
located at 45, (3),
75 the 105
and number
V. of levels is since
Furthermore, increased
the to twelve.
zero level Since Va =are
generators 0.5not
Vdcactivated,
,activated,
the new
10b and 11b show the harmonic spectrum with and without the zero voltage level generation,
levels are located at 45, 75 and 105 V. Furthermore, since the zero level generators are not
levels
this areis
level located
is absentat 45, 75
from and 105 V. Furthermore, since the zero level generators are not activated,
respectively.
this level The THD
absent from ofthe
the thewaveform.
waveform. Mode
former isMode
12.5%. II II with
With
with thethe
the zero
zero level
introduction
level is is shown
of the
shown in Figure
zero
in Figure level,
11a.11a.
the Figures
THD10b
Figures is
this
10b level
and is
11b absent
show from
the the waveform.
harmonic Mode
spectrum II
with with
and the zero
without level
the is shown
zero in
voltage Figure
level 11a. Figures
generation,
reduced to 9.5%. Note that these are THD values are without filtering.
and 11b show the harmonic spectrum with and without the zero voltage level generation, respectively.
10b and 11b
respectively.
The THD of theshow
The THD
formerthe is
harmonic
of the former
12.5%. spectrum
With is 12.5%.
the withWith
introduction and the without
of the zerothe
introduction zero
level,ofthevoltage
the level
zeroislevel,
THD generation,
the
reduced THD is
to 9.5%.
respectively.
reduced
Note100thattotheseThe
9.5%.areTHD
Note
THD of
that the former
theseare
values is 12.5%.
arewithout
THD values With the introduction
are without filtering.
filtering. of the zero level, the THD is
100
reduced to 9.5%. Note that these are THD values are without filtering.
50 80
(V)

(V) Mag (V)

100 100
0 60
(V)Voltage

100 100
agVoltage

50 80
40
(V)

-50
50 80
60
(V)

0
Voltage

Voltage

20
MagM

-100
0 60
Voltage

Voltage

40
-50 0
0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04 40
-50 0 20 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000
-100 Time (s) Frequency (Hz)
20
-100 0
0 (a)0.02 0.025 0.03 0.035 0.04
0.005 0.01 0.015 0 1000 2000 3000 4000(b)
5000 6000 7000 8000 9000 10000
Time 0.025
(s) 0
0 0.005 0.01 0.015 0.02 0.03 0.035 0.04 0 Frequency
1000 2000 3000 4000 5000 (Hz)
6000 7000 8000 9000 10000
Time (s) Frequency (Hz)
Figure 10. Output(a) of the MLI in Mode II without the introduction of(b) the zero level (a) Voltage
waveform (b) its
(a)
corresponding harmonics spectra. THD is 12.5%.
(b)
Figure 10. Output of the MLI in Mode II without the introduction of the zero level (a) Voltage waveform
Figure 10. Output of the MLI in Mode II without the introduction of the zero level (a) Voltage
(b) its corresponding
Figure 10. (b)
Output ofharmonics spectra.
the MLI in ModeTHD is 12.5%.
IIspectra.
without the is
introduction of the zero level (a) Voltage
waveform its corresponding harmonics THD 12.5%.
waveform (b) its corresponding harmonics spectra. THD is 12.5%.
100 100

50 80
(V)

(V) Mag (V)

100 100
0 60
(V)Voltage

100
agVoltage

100
50 80
40
(V)

-50
50 80
60
(V)

0
Voltage

Voltage
MagM

-100 20
60
0
Voltage

Voltage

-50 40
0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04 0
-50 0 Time (s)
40
20
0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000
-100 Frequency (Hz)
20
-100
0 (a)0.02 0.025 0.03 0.035 0.04
0.005 0.01 0.015 0
0 (b)
1000 2000 3000 4000 5000 6000 7000 8000 9000 10000
Time 0.025
(s) 0 Frequency
0 0.005 0.01 0.015 0.02 0.03 0.035 0.04 0 1000 2000 3000 4000 5000 (Hz)
6000 7000 8000 9000 10000
Figure
Figure 11.
11. Output
Output of the
the MLI
ofTime (s) in
MLI in Mode
Mode IIII with
with the
the introduction
introduction of
of the
the zero
zero level
level
Frequency(a)
(a) Voltage
Voltage waveform
(Hz) waveform
(a) (b)
(b) its corresponding
(b) its corresponding harmonics spectra.
(a) harmonics spectra. THD
THD is
is 9.5%.
9.5%. (b)
Figure 11. Output of the MLI in Mode II with the introduction of the zero level (a) Voltage waveform
Figure 11. Output
5.2. Experimental of the
Verification
(b) its corresponding MLI in Mode
harmonics II with
spectra. THDthe introduction of the zero level (a) Voltage waveform
is 9.5%.
(b) its corresponding harmonics spectra. THD is 9.5%.
5.2.1. Experimental Setup
To prove the workability of the proposed idea, a 300 W, thirteen level MLI is designed and
constructed. Three dc sources are used in LGM (i.e., k = 2); the voltage of each dc source is set to 30 V
with one dc voltage source for AM (total of four dc voltage sources are used). The power circuit is
based on the IKB20N60H3 IGBT (600 V/20 A). The switching frequency of the PWM waveform for
the auxiliary circuit is 7.5 kHz. To implement the modulation, the XE 166 Infineon microcontroller is
5.2.1. Experimental
5.2.1. Experimental Setup
Setup
To prove
To prove thethe workability
workability of of the
the proposed
proposed idea,idea, aa 300
300 W,W, thirteen
thirteen level
level MLI
MLI isis designed
designed and and
constructed. Three dc sources are used in LGM (i.e., k = 2); the voltage of each
constructed. Three dc sources are used in LGM (i.e., k = 2); the voltage of each dc source is set to 30 V dc source is set to 30 V
with one
with one dc voltage
dc12,voltage source for AM (total of four dc voltage sources are used).
source for AM (total of four dc voltage sources are used). The power circuit The power circuit is
is
Energies 2019, 977 11 of 15
based on
based on the
the IKB20N60H3
IKB20N60H3 IGBT IGBT (600(600 V/20
V/20 A).
A). The
The switching
switching frequency
frequency of of the
the PWM
PWM waveform
waveform for for
the auxiliary circuit is 7.5 kHz. To implement the modulation, the XE 166
the auxiliary circuit is 7.5 kHz. To implement the modulation, the XE 166 Infineon microcontroller isInfineon microcontroller is
used. The
used. Thegate
The gatepulses
gate pulsesfrom
pulses from
from the
thethe microcontroller
microcontroller
microcontroller are
are are
made made
made suitable
suitable
suitable forswitches
for
for the the switches
the switches using
using using
the gatethe
the gate
gate
driver
driver circuits. A dead time of 0.5 μs is added to protect the bridge from
driver circuits. A dead time of 0.5 μs is added to protect the bridge from shoot-through fault. The
circuits. A dead time of 0.5 µs is added to protect the bridge from shoot-through shoot-through
fault. The fault.
photograph The
photograph
photograph
of of the MLI arrangement
of the MLI arrangement
the MLI arrangement with the dc with with
sourcesthe dc
the and sources
dc sources and measurement
and measurement
measurement instrument
instrumentinstrument is shown
is shown inis Figure
shown 12. in
in
Figurethe
Figure
Since 12.inverter
12. Since the
Since the inverter is
inverter is bidirectional,
is bidirectional, bidirectional, it is
it
it is tested using is tested
tested
the using and
using
resistive the inductive
the resistive and
resistive and inductive
inductive
loads. loads.
loads.
Furthermore,
Furthermore,
the auxiliary the
moduleauxiliary
can bemodule
turned can
off be
at turned off
convenience; at convenience;
thus, comparisonthus,
Furthermore, the auxiliary module can be turned off at convenience; thus, comparison can be readily comparison
can be readily can
madebe readily
for the
made
made for
circuit for
with the
theandcircuit
circuit with
withthe
without and without
andauxiliary. the auxiliary.
without the auxiliary.

Oscilloscope
Oscilloscope

Microcontroller
Microcontroller
dc Voltage Source
dc Voltage Source

MLI Topology
MLI Topology
Gate Driver
Gate Driver
Circuits
Circuits

Figure 12.
Figure
Figure 12. The
12. The photograph
The photograph of
photograph of the
of the prototype
the prototype MLI
prototype MLI circuit.
MLI circuit.
circuit.

5.2.2. Experimental
5.2.2.
5.2.2. Experimental Results
Experimental Results
Results

No Load
No
No Load Condition:
Load Condition: Mode
Condition: Mode III and
Mode and II
and II
II
Figure 13
Figure
Figure 13 shows
13 shows the
shows the experimental
the experimental output
experimental output voltage
output voltage of
voltage of the
of the MLI
the MLI in
MLI in Mode
in Mode I,
Mode I,I, under
under the
under the no-load
the no-load
no-load
condition.
condition. The
The modulation
modulation index
index isisset
set to
tobe bethe
thesame
same as simulation,
as simulation, i.e., 1.14.
i.e., As
1.14.
condition. The modulation index is set to be the same as simulation, i.e., 1.14. As can be observed, the can
As be
can observed,
be observed,the
waveform is
the waveform
waveform is very
very similar
is similar to
very to the
similar the simulation
to simulation shown
the simulation shown in in Figure
shown Figure 9a.
in 9a. This
Figure This confirms
9a. confirms the
This the workability
confirms workability of
the workability of the
the
of
LGM and
the
LGM
LGMand the
the PCU.
and PCU. The
the The output
PCU. output voltage
The outputvoltage with
voltage with the
with the AM
theAM in
AM in Mode
inMode II
Mode II is
IIis depicted
isdepicted in
depicted in Figure
in Figure 13.
Figure 13. The
13. The first
The first
first
waveform,
waveform, i.e.,
i.e., Figure
Figure 14a
14a is
is without
without the
the zero
zero level.
level. As
As expected,
expected, the
the number
number
waveform, i.e., Figure 14a is without the zero level. As expected, the number of levels is increased of
of levels
levels is
is increased
increased
from six
from
from six to
six to twelve.
to twelve. The
twelve. The second
The second waveform,
second waveform,
waveform, i.e., i.e., Figure
i.e., Figure 14b
Figure 14b is
14b is obtained
is obtained
obtained when
when the
when the
the zero
zero level
zero level
level is
is generated.
generated.
is generated.
Again, the
Again,
Again, the experimental
the experimental waveform
experimental waveform is
waveform is in
is in very
in very close
very close agreement
close agreement with
agreement with the
with the simulation,
the simulation, shown
simulation, shown by
shown by Figures
by Figures
Figures
10a
10a and
and 11a,
11a, respectively.
respectively.
10a and 11a, respectively.

Figure 13.
Figure
Figure 13. The
13. Theexperimental
The experimentaloutput
experimental outputvoltage
output voltage(top
voltage (toptrace)
(top trace)
trace) in
inin Mode
Mode
Mode I:I: no
I: no no load
load condition.
condition.
load (Scale:
(Scale:
condition. vertical:
vertical:
(Scale: 50
vertical:
50 V/div,
V/div, horizontal:
horizontal: 4.04.0 ms/div).
ms/div).
50 V/div, horizontal: 4.0 ms/div).
Energies 2019, 12,
Energies 2019, 12, 977
x FOR PEER REVIEW 12
12 of
of 15
15
Energies 2019, 12, x FOR PEER REVIEW 12 of 15

(a) (b)
(a) (b)
Figure 14.
Figure 14. The
The experimental
experimental output
output voltage
voltage in
in Mode
Mode II:
II: no
no load
load condition
condition (a)
(a) without
without zero
zero level
level (b)
(b)
Figure
with 14.level
zero The experimental
Scale for (a): output voltage
vertical: 50 inhorizontal:
V/div, Mode II: no load
4.0 condition
ms/div). Scale (a)
for without
(b): zero50
vertical: level (b)
V/div,
with zero level Scale for (a): vertical: 50 V/div, horizontal: 4.0 ms/div). Scale for (b): vertical: 50 V/div,
with zero level
horizontal: 5.0 Scale for (a): vertical: 50 V/div, horizontal: 4.0 ms/div). Scale for (b): vertical: 50 V/div,
horizontal: 5.0 ms/div).
ms/div).
horizontal: 5.0 ms/div).
Mode II with Resistive Load
Mode II with Resistive Load
Figure 15a,b
Figure 15a,bshow
showthe the experimental
experimental andand simulated
simulated output output
whenwhen
the MLI theisMLI is connected
connected to a
to a resistive
load Figure
(50 Ω)
resistive load 15a,b show the
(50 Ω)II.inInMode
in Mode experimental
II. Inthe
this case, thiszero and
case, simulated
theiszero
level output when
level is not
not activated. the
Asactivated. MLI
expected, As is connected
for expected, fortothe
the experimental a
resistive
case, load case,
experimental
the current(50follows
Ω)
theincurrent
Mode II. In this
follows
the voltage, case,
i.e.,the
in the zero
voltage,
phase. i.e., level
However, is not
in phase.
the activated.of
However,
waveshape As
the expected,
waveshape
the for
of the
former deviates the
experimental
former deviates
slightly, case,
where the the
slightly,current
where are
PWM pulses follows
the being the
PWMrounded voltage,
pulses are i.e.,
at being in phase.
rounded
their edges. However,
Thisatistheir the
due edges. waveshape
This is due
to the inductive of
to the
effectthe
of
former
inductive
wire deviates
wound effect slightly,
usedwhere
of wire
resistor as the the
wound PWM
Notepulses
resistor
load. used asarerounded
that the being
the load. rounded
Note are
edges atnot
that their
the edges.
rounded
observed This is simulation
edges
in the dueare
to not
the
inductive
observed
as an idealineffect of load
wire iswound
the simulation
resistive as anin
used resistor
ideal used load
the resistive
model. as the load.inNote
is used that the rounded edges are not
the model.
observed in the simulation as an ideal resistive load is used in the model.

(a) (b)
(a) (b)
Figure 15. The output voltage (top trace) and current (bottom trace) waveforms with resistive load (50
Figure 15. The output voltage (top trace) and current (bottom trace) waveforms with resistive load
Ω) without
Figure the auxiliary
15. The output module.
voltage (a)trace)
(top experimental (b) simulation
and current (bottom result.waveforms
trace) Experimental
withscale (50 V/div,
resistive
(50 Ω) without the auxiliary module. (a) experimental (b) simulation result. Experimental scaleload
(50
1(50
A/div, 4.0 ms/div).
Ω) 1without thems/div).
auxiliary module. (a) experimental (b) simulation result. Experimental scale (50
V/div, A/div, 4.0
V/div, 1 A/div, 4.0 ms/div).
Figure 16a,b depict the MLI output when the zero level generator is activated. Clearly, the voltage
Figureimproves
waveform 16a,b depict
due tothethe
MLI output when
introduction of anthe zero level
additional generator
level at the zero is activated. Clearly,
crossing point. Forthe
all
Figure
voltage 16a,b depict
waveform improvesthe due
MLItooutput
the when the of
introduction zero
an level generator
additional level is the
at activated.
zero Clearly,
crossing the
point.
cases, it can be observed that the experimental results are in close agreement with the simulation.
voltage
For all waveform
cases, it can improves due to that
be observed the introduction of an additional
the experimental results arelevel at theagreement
in close zero crossingwithpoint.
the
For all
simulation.
Mode cases, it can be observed
II with Resistive-Inductive Load that the experimental results are in close agreement with the
simulation.
Figure 17a demonstrates the experimental waveforms of the MLI in Mode II when connected to
Mode II with Resistive-Inductive Load
Mode II withload
an inductive (R = 10 Ω, L = 250
Resistive-Inductive Load mH). Figure 17b shows its corresponding simulation waveforms.
Figure 17a demonstrates the experimental
As can be seen, the current lags the voltage by 83 waveforms
degrees, of the MLI
which in Mode with
is consistent II whentheconnected
values usedto
an Figure 17a
inductive loaddemonstrates
(R = 10 Ω, L the
= 250experimental
mH). Figure waveforms
17b shows of
its the MLI in Mode
corresponding II when connected
simulation waveforms. to
in the experiment. Furthermore, it is interesting to note that, a small current distortion occurs at the
an
As inductive
can load
be seen, (Rcurrent
the = 10 Ω, lags
L = 250
themH). Figure83
voltage 17b shows its corresponding simulation waveforms.
zero crossing point. The most likely reason by degrees,
for the which
distortion is consistent
is the dead-timewith theasvalues
effect, used
suggested
As
in can
the be seen,
experiment. the current lags
Furthermore, the
it is voltage by
interesting 83
todegrees,
note which
that, a is
small consistent
current with
distortionthe values
occurs used
at the
by [27]. This fact can be confirmed with the simulated current waveform shown in Figure 17b. As can
in the
zero experiment.
crossing Furthermore,
point. The it is interesting to note that, a small current distortion occurs at the
be seen, the distortion is most likely reason
not present; this isfor the distortion
because the deadistimethe dead-time
is not included effect,inasthe
suggested by
simulation.
zero
[27]. crossing
This point.
can beThe
factdemonstrate most likely
confirmed withreason for the distortion
theofsimulated current is the dead-time
waveform showneffect, as suggested
in Figure 17b. by
As can
Figure 17a,b the waveforms the output voltage and the current, respectively, when the
[27]. Thisthe
be seen, fact can be confirmed
distortion with this
is not present; the simulated
is because current
the deadwaveform
time is not shown
includedin Figure
in the 17b. As can
simulation.
be seen, the distortion is not present; this is because the dead time is not included in the simulation.
Energies 2019, 12, x FOR PEER REVIEW 13 of 15

Energies2019,
Figure
Energies 17a,b 12,
2019,12, x FOR PEER REVIEW
demonstrate
977 the waveforms of the output voltage and the current, respectively, 13 13ofof15
when 15

the zero crossing generator is connected. There is a slight improvement in the experimental current
Figure 17a,b demonstrate the waveforms of the output voltage and the current, respectively, when
waveshape. By taking the FFT of the experimental current waveform, the THD without the auxiliary
the zero
zero crossing
crossing generator
generator is connected.
is connected. There
There is ais slight
a slight improvementininthe
improvement theexperimental
experimentalcurrent
current
module is 7.6%. For the case with the auxiliary, the THD is reduced to 6.2%. For the simulated current
waveshape.By
waveshape. Bytaking
takingthe theFFT
FFTofofthe
theexperimental
experimentalcurrent
currentwaveform,
waveform,thetheTHD
THDwithout
withoutthe
theauxiliary
auxiliary
waveforms, the THD is 3.1% and 2.5%, respectively. These results prove that the dead time
moduleisis7.6%.
module 7.6%.ForForthe
thecase
casewith
withthe
theauxiliary,
auxiliary,the
theTHDTHDisisreduced
reducedto
to6.2%.
6.2%.For
Forthe
thesimulated
simulatedcurrent
current
contributes to more than half of the THD values.
waveforms,the
waveforms, the
THDTHD is 3.1%
is 3.1% and 2.5%,
and 2.5%, respectively.
respectively. Theseprove
These results results
thatprove thattime
the dead the contributes
dead time
contributes
to more thanto more
half than
of the halfvalues.
THD of the THD values.

Voltage (V)
Voltage (V)
Current (A)
Current (A)
Time (s)

(a) (b)
Time (s)

Figure 16. The output(a)voltage (top trace) and current (bottom trace) waveforms (b) with resistive load
(50 Ω) with
Figure the output
16. The auxiliary module.
voltage (top(a) experimental
trace) (b)(bottom
and current simulation result.
trace) Experimental
waveforms scale (50load
with resistive V/div,
(50
Figure 16. The output voltage (top trace) and current (bottom trace) waveforms with resistive load
1Ω)A/div, 5.00 ms/div).
with the auxiliary module. (a) experimental (b) simulation result. Experimental scale (50 V/div, 1
(50 Ω) with the auxiliary module. (a) experimental (b) simulation result. Experimental scale (50 V/div,
A/div, 5.00 ms/div).
1 A/div, 5.00 ms/div).

(a) (b)
Figure 17. The output
Figure 17. The output (a)voltage (b) with
voltage (top trace) and current (bottom trace) waveforms
(top trace) and current (bottom trace) waveforms
with resistive load
resistive load
(50 Ω) in Mode II without the zero level. (a) experimental (b) simulation result. Experimental (50 V/div,
(50 Ω) in Mode II without the zero level. (a) experimental (b) simulation result. Experimental (50
1Figure
A/div,17.
4.00The output voltage (top trace) and current (bottom trace) waveforms with resistive load
ms/div).
V/div, 1 A/div, 4.00 ms/div).
(50 Ω) in Mode II without the zero level. (a) experimental (b) simulation result. Experimental (50
6. Conclusions
V/div, 1 A/div, 4.00 ms/div).
6. Conclusions
In this paper, a new MLI topology with a reduced number of switches and dc voltage sources
In this paper, The
is6.recommended.
Conclusions a new MLI topology
proposed with
topology a reduced
provides number
enough of switches
flexibility and dcvoltage
for higher voltageandsources
poweris
recommended.
requirement with The proposed
series topology
and parallel provides
operation enoughdcflexibility
of different for higher
voltage sources. Thevoltage
notable and power
importance
In this paper, a new MLI topology with a reduced number of switches and dc voltage sources is
requirement with series and parallel operation of different dc voltage sources.
is the sharing of load current among different dc voltage sources. A hybrid modulation technique is The notable
recommended. The proposed topology provides enough flexibility for higher voltage and power
importance
used to operateis the sharingswitches.
different of load current among different
This modulation schemedc voltagethe
provides sources. A hybrid
high-voltage modulation
low-frequency
requirement with series and parallel operation of different dc voltage sources. The notable
technique is used high-frequency
and low-voltage to operate different switches.
operation This reduces
which modulationthe scheme
switching provides
losses.theThe
high-voltage
proposed
importance is the sharing of load current among different dc voltage sources. A hybrid modulation
low-frequency
topology is compared with several other similar topologies which indicate the reduction of The
and low-voltage high-frequency operation which reduces the switching losses. the
technique is used to operate different switches. This modulation scheme provides the high-voltage
proposed
number oftopology
switchesisand
compared with sources.
dc voltage several other similar
Finally, the topologies
performance which indicate
of the the reduction
proposed topology of is
low-frequency and low-voltage high-frequency operation which reduces the switching losses. The
the numberby
examined ofgenerating
switches and 13 dc voltage
levels sources.
at the outputFinally, the performance of the
using MATLAB/Simulink andproposed topology
is verified throughis
proposed topology is compared with several other similar topologies which indicate the reduction of
examined
experimental by results.
generating 13 levels at the output using MATLAB/Simulink and is verified through
the number of switches and dc voltage sources. Finally, the performance of the proposed topology is
experimental results.
examined
Author by generating
Contributions: 13 levels
Theoretical at the output
observation, using
simulation, MATLAB/Simulink
experimental and is verified
tests, and preparing through
of the article were
experimental
done by H.M.B.;results.
Z.S. performed experimental tests and prepared the article.
Energies 2019, 12, 977 14 of 15

Funding: The authors would like to acknowledge the financial support received from the Deanship of Scientific
Research (DSR) King Abdulaziz University, Jeddah, under grant No (D-086-829-1437).
Conflicts of Interest: The authors proclaim no conflict of interest.

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