Interconnect PDF

ELE-863 VLSI Circuits and Systems for Data
Communications
Interconnects
Fei Yuan, Ph.D, P.Eng.

Department of Electrical & Computer Engineering
Ryerson University
Copyright c Fei Yuan
Copyright (c) F. Yuan (1)

Preface
⊲ This chapter covers the essentials of the design of on-chip and
on-board interconnects. An emphasis is given to the transmission
line effect of interconnects, termination schemes, and impedance
matching networks.
⊲ The materials covered in this chapter are an essential part of the

4th-year elective course ELE-863 VLSI Circuits and Systems for
Data Communications offered by the Department of Electrical and
Computer Engineering at Ryerson University, Toronto, Ontario,
Canada. The materials of this chapter are drawn from various
published texts and research papers. Some of the major references
are listed at the end of the chapter. Students are strongly
encouraged to read the cited references in the chapter to gain
further knowledge of the subjects covered in this chapter.
⊲ The materials of this chapter can be freely distributed for

educational purposes only. Please report any error of this lecture
note to Professor Fei Yuan via email at fyuan@ryerson.ca.

Chapter Outline
• Introduction
• Thickness of Interconnects
• Minimum Width of Interconnects
• Resistance of Interconnects
• Capacitance of Interconnects
• Inductance of Interconnects
• Modeling of Interconnects
• Transmission Line Effect
• Termination Schemes
• Impedance-Matching Networks
• References

Introduction
• Interconnects in ICs
⊲ Typical interconnects encountered in ICs include metal layers,

silicidated poly layers, silicided n+ and p+ diffusion layers, vias
connecting different metal layers, contacts connecting metal layers
and diffusion regions, and contacts connecting metal and poly
layers.
⊲ The scaling of MOS devices has been more aggressive than the
scaling of the height of interconnects −→ the performance of ICs, in
particular, the propagation delay, is largely affected by
interconnects.
Table 1: Scaling of interconnects.

Parameters CMOS-0.35 CMOS-0.25 CMOS-0.18 CMOS-0.13
VDD 3.3V 2.5V 1.8V 1.2V
(24% drop) (28% drop) (33% drop)
Lmin 0.35µm 0.25µm 0.18µm 0.13µm
(29% drop) (28% drop) (38% drop)
Min. width 0.5µm 0.32µm 0.23µm 0.16µm
of metal-1 (36% drop) (28% drop) (30% drop)
Min. width 0.35µm 0.25µm 0.22µm 0.12µm
of poly (29% drop) (12% drop) (45% drop)
VIA12 0.5µm 0.36µm 0.26µm 0.20µm
(28% drop) (28% drop) (23% drop)
Contact 0.4µm 0.3µm 0.22µm 0.16µm
(25% drop) (27% drop) (27% drop)
Min. height 6700A 5700A 5300A
of metal-1 (15% drop) (7% drop)
Number of 3 metal 5 metal 6 metal 8 metal
metal layers layers layers layers layers

Introduction (cont’d)
⊲ The number of metal layers has been increased significantly to
combat the increased complexity of systems −→ interconnects
constitute a very significant portion of ICs −→ placement and
routing of interconnects that minimize the propagation delay of and
interference among interconnects have become a major research
area in design of VLSI systems.

Thickness of Interconnects
⊲ The thickness (height) of interconnects is set by process technology
and can not be changed by designers.
⊲ Thickness of interconnects has been scaled down moderately, mainly

due to the resultant increase in the resistance of interconnects,
especially global interconnects.
⊲ The top metal layer has the largest thickness. It has the highest
current rating per unit width and the lowest capacitance per unit
area to the substrate. This layer should only be used for global
signals (VDD , VSS , and clock), spiral inductors, and bonding pads.
⊲ All other metal layers typically have the same thickness. They are
usually used for local wiring, stacked spiral inductors, and
multi-layer bonding pads.

The Min. Width of Interconnects
⊲ The min. width of metal layers has been scaled down aggressively
to reduce the silicon area for routing interconnects.
⊲ The top metal layer has the largest min. width −→ lower resistance
per unit width.
⊲ The contact size and the via size have been scaled down
aggressively, in consistency with the scaling of the minimum width
of interconnects.
⊲ The min. width of poly has also been scaled down aggressively.

Resistance of Interconnects
• Sheet Resistance
⊲ Definition of sheet resistance
L ρ L L
R=ρ = = R2 , (1)
WH HW W
ρ
where R2 = is the sheet resistance with unit Ω, L=interconnect
H
length, W =interconnect width, H=interconnect height, and
ρ=resistivity of interconnects. Note that sheet resistance is a
process-dependent parameter and can not be changed by designers.
⊲ n-well layers have a large sheet resistance (approximately

500Ω-1kΩ). It is normally used as resistors and should not be used
for interconnects.
⊲ n+ layers without silicidation has a moderate sheet resistance

(approximately 50Ω − 100Ω). It should not be used for
interconnects.
⊲ n+ and p+ layers with silicidation have a low sheet resistance

(typically less than 10Ω). It can be used for local interconnects. For
digitally oriented CMOS technologies, often only n+ /p+-layers with
silicidation are available. Note that the sheet resistances of n+ and
p+ layers with silicidation are comparable as they are largely
determined by the resistance of the silicide layer.
⊲ Poly layers in standard digital CMOS processes are silicided.

Typical sheet resistance of silicided poly layers is R2 ≈8Ω. They can
be used for local interconnects.

Resistance of Interconnects (cont’d)
⊲ Contact resistance - the resistance between (i) contact-n+ diffusion,
(ii) contact-p+ diffusion, (iii) contact-ploy. The contact resistance is
usually below 10Ω per contact. To reduce contact-induced parasitic
resistance, multiple contacts should be used.
⊲ Via resistance - for 3-metal CMOS technologies, Via12 (between

Metal-1 and Metal-2) and Via23 (between Metal-2 and Metal-3)
exist. Via resistance is typically smaller than contact resistance,
and is usually less than 8Ω per Via (Vias connecting the top metal
layer have a lower resistance. For example, for a 0.13µm CMOS
technology, the resistance of vias is : V ia1−5 = 1.5Ω and
V ia6,7 = 0.6Ω.) To reduce via-induced parasitic resistance, multiple
vias should be used.
⊲ The sheet resistance of metal layers at low frequencies is small, and

is in the range of 0.05Ω. Note that for global interconnects, since
the length of these interconnects is usually large, the DC voltage
drop across global interconnects must be accounted for in design of
these interconnects.
⊲ The preceding values of the resistances of interconnects are in the

DC steady state. At high frequencies, due to skin effect, currents
flow only in the region close to the surface of the interconnect. The
reduction of the effective conducting area significantly increases the
resistance of interconnects, as to be detailed in the following section.

• Skin Effect
⊲ When an AC current flows through a conductor, a magnetic field is
created. The resultant magnetic field will impact a force, called
Lorezen force, on moving electronics. Lorezen force forces electrons
to move to the surface of the conductor −→ higher resistance at
center and lower resistance near the surface −→ the effective
conducting area is measured by skin depth δ
1
δ=√ , (2)
πµσf
where µ = µr µo is permittivity of the conductor, σ=conductivity of

the conductor, f =frequency of the current.
I
H d
vn r
Lorezen force
Figure 1: Skin effect of interconnects.
⊲ The effective conducting area
A = πr2 − π(r − δ)2 = πr2 − π(r2 − 2rδ + δ 2 )

≈ 2πrδ. (3)
where we have neglected the 2nd-order term.

• Skin Effect (cont’d)
⊲ Skin-effect induced resistance
R(f ) ρ AL r
= L = , (4)
Rdc ρ πr2 2δ
we have
! s
r L µq
R(f ) = Rdc = f. (5)
2δ 2r πσ
Skin-induced resistance is proportional to the square-root of

frequency.
⊲ Skin depth of typical interconnects
Table 2: Skin depth of interconnects at 100 MHz.
Interconnect Resistivity Skin depth 100MHz Skin depth 5GHz

(10−9 Ωm) (µm) (µm)
Silver 16.3 6.4 0.905
Copper 17.3 6.6 0.933
Gold 22.7 7.6 1.07
Aluminum 27.3 8.3 1.17
Silicon 100-300 15.9-27.6 2.25-3.9

• Scaling of Interconnects
⊲ Uniform Scaling - both the width W and height H of

interconnects are scaled down by the same scaling factor.
⊲ SW = SH = S, where SW =scaling factor of width, SH =scaling

factor of height, S=uniform scaling factor.
⊲ SL 6=S, the scaling factor of length SL differs from the scaling factor
of width and height.
⊲ When L−→ SLL , W −→ W H

S , and H−→ S , we have
L
SL S2
R̂ = pW W = R, (6)
S H
SL
where R and R̂ are the resistance of interconnects before and after

uniform scaling.

⊲ For local interconnects, we have SL = S. As a result
R̂ = SR. (7)
The resistance of local interconnects grows linearly with the scaling

factor.
⊲ For global interconnects, we have L̂ = SL (L grows in proportion to

the die size),
R̂ = S 3 R. (8)
The resistance of global interconnects rises cubically with the

scaling factor.
⊲ Uniform scaling has not be adopted due to the rapid increase in the
resistance of global interconnects.

⊲ Selective Scaling - W and L are scaled down by the same
scaling factor but H is kept approximately constant.
Height reduction 15% Height reduction 7%

Width reduction 36% Width reduction 28%
6700A 5700A 5300A
0.5u 0.32u 0.23u
Figure 2: Selective scaling of interconnects (metal-1 of 0.35, 0.25, 0.18µm technologies).
⊲ SW = SL = S, SH ≈1.
L
S
R̂ = ρW S = SR. (9)
S 1
⊲ For local interconnects : R̂ = SR.
⊲ For global interconnects : R̂ = SR.
⊲ The resistance of interconnects, both local and global, increases

linearly with the scaling factor.
⊲ Selective scaling scheme has been adopted in VLSI scaling.

Capacitance of Interconnects
• Area Capacitances
E Ca
Substrate
Figure 3: Area capacitance of interconnects.
⊲ Area capacitance Ca of an interconnect is the capacitance between

the bottom of the interconnect and the substrate.
⊲ Area capacitance deceases with technology, mainly due to the

down-scaling of the width of interconnects.

Capacitance of Interconnects (cont’d)
• Fringe Capacitances
Cf Cf
Substrate
Figure 4: Fringe capacitance of interconnects.
⊲ Fringe capacitance Cf is the capacitance between the side walls and

the substrate.
⊲ Fringe capacitance increases with technology, as compared with

area capacitance, mainly due to the increase of H/W (H is kept
approximately constant whereas W is reduced).
⊲ For deep sub-micron CMOS technologies, Ca and Cf are

comparable. Both must be considered when estimating the
capacitance of interconnects.

• Other Capacitances
⊲ Bond pad capacitances
⊲ Bond pads are on-chip metal rectangles large enough to be soldered

to the leads. Typical 70x70 µm2 - 100x100 µm2 .
⊲ Each pad is typically formed by the two top-most metal layers

connected to each other by many vias on the perimeter in order to
avoid the lift-off of the top metal layer during bonding.
⊲ Most CMOS processes require that all metal layers to be connected

together for bond pads. Because the top metal layer has a smaller
capacitance to the substrate as compared with the bottom metal
layer, connecting all bond-pad metal layers together increases the
capacitance of the pad to the substrate.
64u
64u
m3
T2
m2
T1 H3
m1 H2
T1 H1
Substrate
Figure 5: Capacitance of multi-layer bond pads.

⊲ Capacitance of Stubs
⊲ A stub is a transmission line segment that branches from the main

line.
metal-2
metal-1
Min.enclosure requirement gives rise to

an open line that behaves as a capacitor
Figure 6: Capacitance of stubs.
⊲ The stub shown in the figure is a transmission line with open-circuit

termination. It behaves as a capacitor with the capacitance
determined by the length of the line. To minimize this capacitance,
the minimum enclosure rules should be followed.

Inductance of Interconnects
⊲ Self-inductance of a round bond wire
Figure 7: Self-inductance of a round wire.
" #
2H
⊲ L≈0.2ln where R=radius and H distance from the conductive
R
substrate.
⊲ Self-Inductance of a Rectangular Trace
Figure 8: Self-inductance of a rectangular trace.
" #
1.6 H H
⊲ L≈ , where Kf ≈0.72( W ) + 1 (fringe factor), W =width of the
Kf W
trace and H=distance from the trace to the conductive substrate.

Inductance of Interconnects (cont’d)
⊲ Mutual Inductance of two round wires
Figure 9: Mutual-inductance of two round wires.
" #
2H 2
⊲ L≈0.1ln 1 + ( ) .
d

Modeling of Interconnects
⊲ This section deals with the modeling of interconnects. Depending
upon the frequency of signals traveling through the interconnects
and the physical dimensions, in particular, the length of the
interconnects, the behavior of the interconnects can be
characterized at various levels of abstraction, from the simplest
lumped RC model to full transmission-line models.

Modeling of Interconnects (cont’d)
• Lumped RC Model
• Distributed RC Model
• Elmore Model
• Transmission-line Model

Lumped RC Model of Interconnects
⊲ When the physical dimension of an interconnect is much smaller
than the wave length of the signal passing through the interconnect,
the interconnect can be treated as a lumped element and
represented by a low-pass RC network as shown in Fig.10 with
L
R = R2 W and C = Ca (W L) + Cf L, where Ca and Cf are the area
capacitance per unit area and fringe capacitance per unit length,
respectively.
L Vout
W
H
R
V V out
Vin in
C
C
Substrate
Figure 10: Lumped RC model of interconnects.
⊲ The output voltage to a step voltage input of amplitude Vm is given

by
vo (t) = Vm [1 − e−t/τ ], (10)

1
where τ = RC .
⊲ Propagation delay (tp ) - the time delay from vo = 0 to vo (tp ) = 21 Vm .

From
0.5 = 1 − e−tp /τ , (11)
we arrive at tp = 0.69τ .

Distributed RC Model of Interconnects
⊲ When the physical dimension of an interconnect is comparable to
the wave length of the signal passing through the interconnect, the
interconnect can not be treated as a lumper element. Instead, it
must be treated as a distributed element, as shown in Fig.11 where
R is the resistance per unit length and C is the capacitance per unit
length. Note that the number of distributed elements N should be
L
such that ∆L = is sufficiently small as compared with the
N
wavelength of the signal.
L
Vout
DL
DL i-1 i i+1
R (DL) R(DL) R(DL) R(DL) Vout
Vin V
in C(DL) C(DL) C(DL) C(DL)
C
Substrate
DL DL DL DL
Figure 11: Distributed RC model of interconnects.
⊲ KCL at node i
vi − vi−1 vi − vi+1 dvi

+ + C(∆L) = 0, (12)
R(∆L) R(∆L) dt
from which we obtain
dvi (vi+1 − vi) − (vi − vi−1)

RC = . (13)
dt (∆L)2

Distributed RC Model of Interconnects
(cont’d)
⊲ Let ∆vi+1 = vi+1 − vi, ∆vi = vi − vi−1, and take the limit ∆L−→0,
we arrive at the diffusion equation of the distributed RC model of
interconnects
∂vi ∂ 2 vi
RC = . (14)
∂t ∂x2
⊲ Diffusion equation (14) reveals that the voltage of an interconnect

at a given time t and location x is a function of both the time t and
the location x. Note that in the lumped RC model, the voltage of
interconnects is a function of time t only.

Elmore Model of Interconnects [1]
i-1 i i+1
R1 R i-1 Ri RN Vout
V
in C1 C i-1 Ci CN
DL DL DL DL
1 i-1 i N
V
in
VDD
0 t
V
out
VDD
0.5VDD
0 t
tN
Figure 12: Elmore model of interconnects.
⊲ For non-branched RC networks
τ1 = R1 C1 ,
τ2 = R1 (C1 + C2 ) + R2 C2 ,
τ3 = R1 (C1 + C2 + C3) + R2 (C2 + C3) + R3 C3,
(15)
...
τN = R1 (C
| 1
+ . {z
. . + CN}) + R2(C
| 2
+ . {z
. . + CN}) + . . . + RN CN .
N N −1

Elmore Model of Interconnects (cont’d)
⊲ Interconnects are represented by distributed RC networks, where R
and C are resistance and capacitance per unit length, respectively.
i-1 i i+1
R (DL) R (DL) R (DL) R (DL) Vout
V
in C (DL) C (DL) C (DL) C (DL)
DL DL DL DL
1 i i+1 N
Figure 13: Elmore model for distributed interconnects.
τN = R1(C
| 1
+ C2 +
{z
... + CN}) + R2 (C
| 2
+ ...
{z
+ CN}) + . . . + RN CN
N N −1
= R(∆L)[C(∆L) + C(∆L) + . . . + C(∆L)]
| {z }
N
+ R(∆L)[C(∆L) + C(∆L) + ... + C(∆L)] + . . . + R(∆L)C(∆L)
| {z }
N −1
= RC(∆L)2(1 + 2 + ... + N )
N (N + 1)
= RC(∆L)2 . (16)
2
L
⊲ Because ∆L = N, we have
1 1
τN = RCL2(1 + ). (17)
2 N
⊲ In the limit N →∞,
1
τN = RCL2. (18)
2

• Comparison of lumped RC model and Elmore model
Elmore model
Vm
0.9Vm
Lumped RC model
0.5Vm
0.1Vm
0.35RC
0.69RC
0.9RC
2.2RC
Figure 14: Comparison of Elmore and lumped RC models.
⊲ Consider an interconnect of length L. Let the resistance and

capacitance of the interconnect per unit length be R and C,
respectively.
⊲ Delay from lumped RC model
τ = Rtotal Ctotal = RCL2. (19)
⊲ Delay from Elmore model
1
τ = RCL2. (20)
2

• Comparison of lumped RC model and Elmore model
(cont’d)
⊲ The delay of the lumped RC model is twice that of the delay of

Elmore model.
⊲ The propagation delay of lumped RC model = 0.69RC.
⊲ The propagation delay of Elmore model = 0.35RC.
⊲ The rise time from the lumped RC model = 0.9RC.
⊲ The rise time from the Elmore model = 2.2RC.

• Examples
L=1mm Vout
W=1u
H
Vin
Ca Cf
Substrate
Figure 15: Example.
⊲ Consider the interconnect shown. Let the area capacitance per unit
are and the fringe capacitance per unit length be
Ca = 0.058f F/µm2 and Cf = 0.043f F/µm, respectively. Let the
sheet resistance R2 = 10Ω. Estimate the propagation delay.
L
⊲ Total resistance R = R2 W = 10kΩ.
⊲ Total capacitance per unit length C = Ca A + Cf L = 0.101 pF.
⊲ Propagation delay τp = 0.38RC = 0.38 ns.

Transmission Line Model of Interconnects
• Transmission line equations
• Characteristic line impedance
• Reflection coefficient
• Input impedance

Transmission Line Equations
⊲ An infinitesimal section of a transmission line is represented by a
lumped network shown in Fig.16, where R=series resistance per
unit length, L=self-inductance per unit length, G=shunt
conductance between the interconnect and substrate per unit length
(mainly due to dielectric loss of Si O2 ), C=shunt capacitance
between the interconnect and substrate per unit length.
z z+D z
Dz
V(z,t)
Substrate
L(D z)
I(z) R(D z) I(z+ D z)
V(z) G (D z) C (D z) V(z+ D z)
Figure 16: lumped network model of an infinitesimal section of transmission lines.
⊲ In the AC steady-state, write KVL in the phasor domain
" #
V (z + ∆z) − V (z) = − R(∆z) + jωL(∆z) I(z). (21)
In the limit ∆z→0, we have
dV (z)
= −(R + jωL)I(z). (22)
dz

Transmission Line Equations (cont’d)
⊲ Similarly, write KCL
" #
I(z + ∆z) − I(z) = − G(∆z) + jωC(∆z) V (z + ∆z). (23)
In the limit ∆z→0, we have
dI(z)
= −(G + jωC)V (z). (24)
dz
⊲ Differentiate (22) with respect to z and substitute (24) into the

resultant equation yield
d2V (z)
2
− γ 2V (z) = 0. (25)
dz
q
where γ = (G + jωC)(R + jωL) = α + jβ is the complex
propagation constant, α is the attenuation constant quantifying the
attenuation of the amplitude of the voltage (current), and β is the
phase constant depicting the variation of the phase of the voltage
(current). Note that both α and β are REAL constants.

⊲ In a similar manner, one can show that
d2 I(z)
2
− γ 2I(z) = 0. (26)
dz
Eqs.(25) and (26) are called transmission line equations.
⊲ Transmission line equations are 2nd-order O.D.Es. They have the

following general solution
V (z) = V + e−γz + V − eγz ,

(27)
I(z) = I + e−γz + I −eγz ,
where V +, V − , I + , and I − are independent of z. Note that the

above equations depict the voltage and current of the transmission
lines in the frequency domain.
⊲ Evaluating V (z) and I(z) at z = 0 gives
V (0) = V + + V −,
(28)
I(0) = I + + I − .
The voltage and current at z = 0 are the sum of the voltage

(current) of the incident wave and that of the reflected wave at
z = 0.

⊲ Because
V +e−γz = V +e−(α+jβ)z
= V +e−αz [cos(βz) − jsin(βz)], (29)
and
V −eγz = V − e(α+jβ)z
= V − eαz [cos(βz) + jsin(βz)]
= V − e−α(−z) {cos[β(−z)] − jsin(β(−z)]}. (30)
we conclude that (29) depicts the propagation of the voltage in

z-direction (the voltage of the incident wave), whereas (30)
characterizes the propagation of the voltage in −z direction (the
voltage of the reflected wave).
⊲ If α = 0, the amplitude of the voltage of the wave in both z and −z

directions remains unchanged along the transmission lines (lossless
lines).
⊲ For practical transmission lines, α > 0, the voltage of both the

incident and reflected waves is attenuated along the transmission
lines (lossy lines).

Characteristic Line Impedance
⊲ The current of the transmission lines is obtained from
1 dV (z)
I(z) = −
R + jωL dz
1 d
= − (V +e−γz + V −eγz )
R + jωL dz
1
= (V +e−γz − V − eγz ). (31)
Zo
where
v
u R + jωL
R + jωL u
Zo = =t (32)
γ G + jωC
is called the characteristic impedance of the line.
⊲ The characteristic impedance is independent of either the voltage or

the current of the line. It is a function of the physical
characteristics of the line that are quantified by R,L,C,and G only.
⊲ For lossless lines, i.e. no ohmic loss, R = 0 and G = 0, we have
v
u
uL
Zo = t
. (33)
C
The characteristic impedance of lossless lines is a REAL constant.

For coaxial cables, typically Zo = 50Ω and for PCB traces,
Zo = 75Ω.

Characteristic Line Impedance (cont’d)
⊲ Comparing the following two equations
I(z) = Z1o (V +e−γz − V −eγz ),

(34)
I(z) = I + e−γz + I − eγz ,
we have
V + = Zo I + ,
(35)
V − = −Zo I −
For lossless lines, since Zo is real, V + and I + are in phase while V −

and I − are out of phase.

Reflection Coefficient
IL
V
VL ZL
V
z=0
Figure 17: Terminated lines.
⊲ At the load whose location is specified by z = 0, the voltage across

the load is obtained from VL (0) = V + + V − , where V + and V − are
the amplitude of the voltage of the incident and reflected waves,
respectively.
⊲ At the load (z = 0), we have
VL (0) V++V−
ZL = = 1 + − V −)
. (36)
IL (0) Zo (V
The above equation can be written as
" #
− ZL − Zo +
V = V . (37)
ZL + Zo

Reflection Coefficient (cont’d)
⊲ Voltage reflection coefficient at the load (z = 0) is defined as
V− ZL − Zo
ΓV (0) = + = . (38)
V ZL + Zo
Note that reflection coefficient is a function of location. The above

definition is valid at z = 0 only because ZL is evaluated at z = 0.
⊲ Current reflection coefficient at the load is obtained form
I− V −/Zo
ΓI (0) = + = − + = −ΓV (0). (39)
I I /Zo

Reflection Coefficient (cont’d)
• Reflection coefficient of open lines
⊲ Open lines : ZL = ∞.
⊲ Γ(0) = 1. As a result, V + = V − −→ a maximum reflection occurs at

the load. The reflected wave is in phase with the incident wave −→
VL (0) = V + + V −, voltage doubles at the far end of an open line !
⊲ Because ΓI (0) = −ΓV (0) = −1, we have IL(0) = I + + I − = 0. The

current at the far end of an open line vanishes.
• Reflection coefficient of shorted lines
⊲ Shorted lines : ZL = 0.
⊲ ΓV (0) = −1, As a result, V + = −V − −→ a maximum reflection

occurs at the load. The reflected wave is out of phase with the
incident wave −→ VL (0) = V + + V − = 0, voltage vanishes at the far
end of an shorted line.
⊲ Because ΓI (0) = −ΓV (0) = 1, we have IL(0) = I + + I − . The current

at the far end of a shorted line doubles.

Input Impedance
I(z) Zo IL
V
V(z) V(0) ZL
Z in (z) V
z z=0
Figure 18: Input impedance of transmission lines.
⊲ The input impedance of a terminated transmission line at an

arbitrary location z
V (z)
Zin (z) =
I(z)
V + e−γz + V − eγz
=
I + e−γz + I − eγz
+ VV + eγz
" −γz − #
e
= Zo −γz V − γz
e − V+e
" −γz
+ ΓV (0)eγz
#
e
= Zo −γz
e − ΓV (0)eγz
1 + ΓV (0)e2γz
" #
= Zo . (40)
1 − ΓV (0)e2γz

Input Impedance (cont’d)
⊲ Eq.(40) reveals that once the voltage reflection coefficient at the
load z = 0 is known, the input impedance at any location z of the
line can be determined.
⊲ For lossless lines we have α = 0 and γ = jβ. Because
ZL − Zo
ΓV (0) = , (41)
ZL + Zo
we have
" #
ZL + jZo tan(βz)
Zin (z) = Zo . (42)
Zo + jZL tan(βz)
This equation allows us to compute Zin (z) at any location z of

lossless lines.

• Input impedance of terminated lossless lines
⊲ Terminated lossless lines : ZL = Zo .
⊲ Zin (z) = Zo and ΓV (z) = 0
1. No reflection at any point of a lossless line once the line

is terminated with its characteristic impedance.
2. The input impedance is the same anywhere along the

line and in is the characteristic impedance of the line.

• Input impedance of open-circuit terminated lossless
lines
⊲ Open-circuit terminated lossless line : (ZL = ∞).
Zo
⊲ Zin (z) = .
jtan(βz)
⊲ A lossless line with an open-circuit termination exhibits a capacitive

characteristic ! The capacitance depends upon the length of the line
and the frequency of the signal traveling on the line.

⊲ The following configurations introduce unwanted capacitive loads,
arising from the stubs and the minimum enclosure space
requirement of design rules.
Stub
Stub
(A) - multiple drops

Figure 19: Unwanted capacitive loads.

Min. enclosure space required by design rules
VIA12
m2
Stub Stub m1
Min. enclosure space required by design rules
(B) - multiple layers of interconnects
Figure 20: Unwanted capacitive loads.
⊲ The followings should be considered to minimize the unwanted

capacitances
(1) In multiple-drop cases, the length of stubs should be minimized.
(2) In multiple layer interconnect case, the space between the via
and the edge of metal layers should be minimized.

• Input impedance of short-circuit terminated lossless
lines
⊲ Short-circuit terminated lossless lines : ZL = 0.
⊲ Zin (z) = jZo tan(βz).
⊲ A lossless line with a short-circuit termination exhibits an inductive

characteristic !

• Input Impedance (cont’d)
⊲ Quarter-Wave Transformer
l/4
IL
V
Zo V(0) ZL
Z in(z) V
z z=0
Figure 21: Quarter wave transformer.
⊲
" #
−λ ZL + jZo tan(βz)
Zin ( ) = Zo
4 ZL + jZL tan(βz) z= −λ
4
Zo2
= . (43)
ZL
or in the following form
v
u
u λ
Zo = t
ZLZin (− ). (44)
4

⊲ Application of Quarter-Wave Transformer
⊲ If ZL and Zo are known, this relationship allows us to choose a
transmission line segment of length λ/4 whose impedance is given
by Zin (− λ4 ), as shown in Fig.22, to eliminate the reflection at the far
end of the transmission line.
Long interconnect
Strong reflection
Zo
ZL
Very small distance

Strong reflection
Zero reflection l/4
Zo
Zo Zo ZL
Impedance matching
network
Figure 22: Quarter wave transformer as an impedance-matching network.
⊲ Note that reflection still exists between the added impedance

matching network and the load. However, since the distance
between them is so small, the effect of ringing (multiple reflections
between the matching network and the load) is negligible.
⊲ Because the length of the quarter-wave transformer is determined
by the wavelength of the signal, impedance matching using a
quarter-wave transformer is only effective at a given frequency −→
quarter-wave transformer can only be used for narrow-band
impedance matching.

Transmission Line Effects
⊲ In this section, we investigate the voltage and current of
interconnects (i)without termination at both the near and far ends
of the interconnects, (ii) with termination at the near end but no
termination at the far end, and (iii) with termination at both the
near and far ends. These studies will reveal an important
characteristics of long interconnects, called ringing, which gives rise
to inter-symbol interference and limits the rate of data transmission.

Transmission Line Effects (cont’d)
⊲ No Termination
⊲ Consider a step voltage of Vs = 5V applied to a lossless transmission

line. Let the source impedance be Zs = 5Zo , where Zo is the
characteristic line impedance. Let the propagation delay of the line
be τ . We derive the waveform of v1(t) and v2(t).
Zs=5Zo 1 Zo 2
ZL= infinity
5V
Z1
Figure 23: No termination.
⊲ To simplify analysis, we assume Z1 = Zo . Note that this assumption

is not true in reality because a lossless line terminated with an
open-circuit is a capacitor with impedance
Zo
Z1 = . (45)
jtan(βz)
⊲ When the wave arrives at node 1 for the very first time, the voltage
and current at node 1 are computed from
Zo
V1 = V
Zo +5Zo s
= 56 ×5 = 0.83V,
(46)
Vs 5
I1 = Zo +5Zo = 6Zo .

+
of the incident wave is given by V2,1 = 0.83V, where the first
subscript identifies the node and the second subscript identifies that
this is the first time the wave arises at the node.
⊲ The voltage and current reflection coefficients of node 2 are

computed from

ZL −Zo
ΓV 2 =
ZL +Zo = 1,
ZL =∞ (47)
ΓI2 = −ΓV 2 = −1,
from which we obtain the voltage and current of the reflected wave
at node 2
− +
V2,1 = ΓV 2 V2,1 = 0.83V,
(48)
− +
I2,1 = ΓI2 I2,1 = − 6Z5 o .
⊲ The total voltage and current at nod 2, after the first reflection, are
obtained from
+ −
V2,1 = V2,1 + V2,1 = 0.83V + 0.83V = 1.66V,
(49)
+ − 5 5
I2,1 = I2,1 + I2,1 = 6Zo − 6Zo = 0.

⊲ When the reflected wave arrives at node 1 for the very first time, we
+ +
have V1,1 = 0.83V and I1,1 = − 6Z5 o . The voltage and current
reflection coefficients at node 1 are obtained from

ZL −Zo
ΓV 1 =
ZL +Zo = 23 .
ZL =5Zo
(50)
ΓI1 = −ΓV 1 = − 32 .
⊲ The voltage and current of the reflected wave at node 1 are

computed from
− +
V1,1 = ΓV 1V1,1 = 32 ×0.83V = 0.5533V,
(51)
− +
I1,1 = ΓI1 I1,1 = (− 23 )(− 6Z5 o ) = 5
9Zo .
⊲ The total voltage and current at node 1, after the first reflection,
are given by
+ −
V1,1 = V1,1 + V1,1 + 0.83V = 0.83V + 0.5533V + 0.83V = 2.2133V,
(52)
+ − 5 5 5 5 5
I1,1 = I1,1 + I1,1 + 6Zo = − 6Zo + 9Zo + 6Zo = 9Zo .

⊲ When the wave arrives at node 2 for the second time
+
V2,2 = 0.5533V,
− +
V2,2 = ΓV 2V2,2 = 0.5533V.
(53)
+ 5
I2,2 = 9Zo
− +
I2,2 = ΓI2 I2,2 = − 9Z5 o .
⊲ The resultant voltage and current at node 1 are obtained from
+ −
V2,2 = V2,2 + V2,2 = 0.5533 + 0.5533 = 1.12V,
(54)
+ −
I2,2 = I2,2 + I2,2 = − 9Z5 o + 5
9Zo = 0.
⊲ When the reflected wave arrives at node 1 for the second time
+
V1,2 = 0.5533V,
− +
V1,2 = ΓV 1V1,2 = 32 ×0.5533V = 0.3687V,
+ −
V1,2 = V1,2 + V1,2 = 0.5533 + 0.3687 = 0.93V,
(55)
+
I1,2 = − 9Z5 o ,
− + + −
I1,2 = ΓI1 I1,2 = (− 23 )(− 9Z5 o ) = 10
27Zo .I1,2 = I1,2 + I1,2 = − 9Z5 o + 10
27Zo
10
= − 27Z o
.

⊲ The total voltage and current at node 1 after the 2nd reflection
become
V1 = 2.22 + 0.93 = 3.15V,

(56)
5
I1 = 9Z5 o − 27Z o
5
= 27Z o
.
⊲ When the wave arrives at node 2 for the third time
+
V2,3 = 0.3687V
− +
V2,3 = ΓV 2 V2,3 = 0.3687V.
+ −
V2,3 = V2,3 + V2,3 = 0.7374V,
(57)
+ 10
I2,3 = 27Zo ,
− + 10
I2,3 = ΓI2I2,3 = − 27Z o
.
+ −
I2,3 = I2,3 + I2,3 = 0.
⊲ When the wave arrives at node 1 for the third time
+
V1,3 = 0.3687V
− +
V1,3 = ΓV 1 V1,3 = 32 ×0.3687V = 0.2458V.
+ −
V1,3 = V1,3 + V1,3 = 0.3687 + 0.2458 = 0.6145V,
(58)
+ 10
I1,3 = − 27Z o
,
− +
I1,3 = ΓI1 I1,3 10
= − 32 ×(− 27Z o
10
) = 81Z o
,
+ − 10 10 20
I1,3 = I1,3 + I1,3 = − 27Zo + 81Zo = − 81Z o
.

⊲ The total voltage and current
V1 = 3.15 + 0.6145 = 3.745V,

5 20 5 (59)
I1 = 27Z o
− 81Z o
= 81Z o
.
⊲ When the wave arrives at node 2 for the fourth time
+
V2,4 = 0.2458V
− + (60)
V2,4 = ΓV 2V2,4 = 0.2458V.
⊲ When the wave arrives at node 1 for the fourth time
+
V1,4 = 0.2458V
− + (61)
V1,4 = ΓV 1 V1,4 = 32 ×0.2458V = 0.1639V.

Current
Voltage
5/6Zo
6
5/9Zo
5
4.36V
5/27Zo 4.02V 4.19V
4 3.52V
3.77V
3.15V
3 2.78V 5/81Zo
2.22V Current
2 V2
1.66V
1 0.83V
V1
0 t 2t 3t 4t 5t 6t 7t 8t 9t 10t Time
Figure 24: Transmission line effect.
⊲ Ringing exists due to the multiple reflection at both the near and
far ends of the transmission line, arising from impedance mismatch
at both the near and far ends of the line.
⊲ The duration of the ringing depends upon the delay τ of the line.
The smaller the τ , the shorter the ringing −→ the fast the
voltage at the far end of the transmission line reaches its
steady-state value (5V).

Zs=5Zo 1 Zo 2
ZL= infty
5V
Z1
V1
0.83V
0.83V
0.83V
V2
1.66V 1.66V
0.83V
1.39V 0.56V
2.22V
1.12V 2.78V
0.56V
3.15V 0.93V 0.37V
0.74V 3.52V
0.37V
0.62V
3.77V
0.25V
4.02V
Figure 25: Multiple reflections.

Very small distance Very small distance
Strong reflection Strong reflection
Zero reflection
Zo
Long interconnect
Zo Zout Zo Zo Zo Zo Zin Zo
Impedance matching Impedance matching
network network
Figure 26: Impedance matching.
⊲ For long interconnects, impedance-matching networks are required

at both the near and far ends of the interconnects to minimize the
reflection at the near and far ends of the interconnects −→
minimize the ringing of the signals on the interconnects.
⊲ Strong reflection, however, does exist at the interface between the

driver and the impedance-matching network at the near end and
between the load and the impedance-matching network at the far
end. Because the impedance-matching networks are very close to
the driver/load, the amount of time that the voltage needs to climb
up to its steady-state value is much smaller −→ the ringing effect
becomes negligible −→ Impedance-matching networks should be
placed as close as possible to the driver and the load !
⊲ Although, ideally, only the impedance-matching network at the far

end of the interconnect is needed to eliminate the ringing. In
reality, a perfect impedance matching is difficult to achieved. Some
waveform will be reflected at the far end of the interconnect. The
termination at the near end will therefore further eliminate the
reflection. Most high-speed interconnects require double
termination.

⊲ Terminated at the Near End
Zs=Zo 1 Zo 2
ZL= infinity
5V
Z1
Figure 27: Terminated at the near end.

line. Let the source impedance be Zs = Zo , where Zo is the line
characteristic impedance. Let the delay of the line be τ . We derive
the waveform of v1(t) and v2(t).
⊲ To simplify analysis, we assume Z1 = Zo . When the wave arrives at

node 1 for the very first time, the voltage at node 1 is computed
from
Zo 1
V1 = Vs = ×5 = 2.5V (62)
Zo + Zo 2

+
of the incident wave is given by V2,1 = 2.5V.
⊲ The reflection coefficient of node 2 is computed from

ZL − Zo
ΓV 2 = = 1, (63)
ZL + Zo ZL=∞
from which we obtain the voltage of the reflected wave
− +
V2,1 = ΓV 2 V2,1 = 2.5V (64)
⊲ The voltage at nod 2, after the first reflection, is obtained from
+ −
V2,1 = V2,1 + V2,1 = 5V (65)

⊲ When the reflected wave from node 2 arrives at node 1, we have
+
V1,1 = 2.5V. The reflection coefficient at node 1 is obtained from

ZL − Zo
ΓV 1 = = 0. (66)
ZL + Zo ZL =Zo
⊲ The reflected wave at node 1 is computed from
− +
V1,1 = ΓV 1 V1,1 = 0. (67)
No wave is reflected at node 1.
+ −
V1,1 = V1,1 + V1,1 = 2.5V. (68)
⊲ The total voltage at node 1 is obtained from
V1 = V1,1 + 2.5 = 5V. (69)
⊲ Although V2 = 5V after the delay τ , due to the existence of the

reflected wave traveling towards node 1, the second data can not be
sent to the line until the reflected wave from node 2 is fully
1
absorbed at node 1 −→ the max. data rate = .
2τ

⊲ Double Termination

line. Let the source impedance be Zs = Zo and the load impedance
be ZL = Zo , where Zo is the line characteristic impedance. Let the
delay of the line be τ . We derive the waveform of v1(t) and v2(t).
Zs=Zo 1 Zo 2
5V Zo
Z1
Figure 28: Double termination.
⊲ The line is terminated with its characteristic impedance

−→Z1 = Zo .
⊲ When the wave arrives at node 1 for the first time, the voltage and
current of node 1 are computed from
Zo
V1 = V
Zo +Zo s
= 21 ×5 = 2.5V,
(70)
5−2.5 2.5
I1 = Zo Vs = Zo .

+
and current of the incident wave are given by V2,1 = 2.5V and
+ 2.5
I2,1 = Zo , respectively.
⊲ The voltage and current reflection coefficients of node 2 are

computed from

ZL −Zo
ΓV 2 =
ZL +Zo
= 0,
ZL =∞ (71)
ΓI2 = −ΓV 2 = 0.
from which we obtain the voltage and current of the reflected wave
− +
V2,1 = ΓV 2 V2,1 = 0,
− + (72)
I2,1 = ΓI2 I2,1 = 0.
−→ No reflection at node 2.
⊲ The voltage and current at nod 2 are obtained from
+ −
V2,1 = V2,1 + V2,1 = 2.5V,
+ − (73)
I2,1 = I2,1 + I2,1 = 2.5
Zo .

⊲ The total voltage at node 1 is 2.5V.
⊲ The total propagation time of the wave on the transmission line is τ .
⊲ Note that although ideally a perfect impedance matching at the far

end will eliminate refection, in reality a perfect impedance matching
is difficult to achieve. Some reflection is enviable. For this reason,
double terminations are needed to minimize multiple reflections.
⊲ When double termination is employed, V2 = V2s −→ 50% signal

(voltage) loss at the far end of the line. Also, DC power
consumption exists. These are the prices paid for the elimination of
reflection.

Termination Schemes
⊲ This section deals with termination schemes of interconnects. The
pros and cons of various termination schemes, namely series
termination, parallel termination, AC parallel termination, and
Thevenin termination, are investigated in detail.

Termination Schemes (cont’d)
• No Termination
• Series Termination
• Parallel Termination
• AC Parallel Termination
• Thevenin Termination

No Termination
1 Zo=50 Ohms 2
Vin
Z L1 Z L,2
Figure 29: Inverter drivers without termination.
ZL2 − Zo
⊲ Because ZL,2 is very large, Γ2 = ≈1. Strong reflection at
ZL2 + Zo
the far end of the line. Voltage doubles at node 2.
⊲ ZL1 is the output impedance of the driving inverter. It varies with

the output voltage of the inverter in the following ways





Rn , when Vout is low
ZL1 =  Rp , when Vout is high (74)


 Ro,n ||Ro,p , when Vout is in transition
where Rn and Rp are the channel resistance of nMOS and pMOS

transistors when in triode, respectively, and Ro,n and Ro,p are the
output resistance of nMOS and pMOS transistors when in
saturation, respectively. Note that we have neglected the regions
when one of the transistors of the inverters in triode and the other
is in saturation.
⊲ The variation of ZL1 gives rise to reflection at the near end of the
transmission line.

No Termination (cont’d)
⊲ Also note reflection also exists even if the signal is of low
frequencies. Sharp transitions contain high-frequency components.
These high-frequency components are subject to transmission line
effect because their wave length is comparable to the length of the
line.
Time Domain Frequency Domain
T/2 w 2w 3w 4w w
s s s s
Figure 30: Signal sharp transitions contain high-frequency components.
⊲ Fourier series expansion of the periodic signal shown
∞
X
x(t) = Cn ejnωs t , (75)
n=−∞
2π 1 Z T
where ωs = and Cn = x(t)e−jnωst dt.
T T 0

Series Termination
Rs 1 Zo=50 Ohms 2
Vin
Z L1 Z L2
Figure 31: Inverter driver with series termination.
ZL2 − Zo
⊲ Because ZL,2 is very large, Γ2 = ≈1. Strong reflection at
ZL2 + Zo
the far end of the transmission line −→ The voltage at the far end
equals to the applied voltage.
⊲ ZL1 is the output impedance of the driving inverter. It varies with

the output voltage of the inverter. An explicit termination resistor
Rs is inserted to ensure ZL1 = Zo −→ no reflection at the near end.
The min. delay is the time for an around trip.
⊲ Drawbacks - Although Rs can ensure that ZL1 = Zo for a given

output voltage, the variation of the output impedance of the
inverter driver gives rise to ZL1 <> Zo for other output voltage,
resulting in reflection at the near end of the transmission line −→ a
perfect impedance matching at the near end is difficult to achieve.

Parallel Termination
1 Zo=50 Ohms 2
Vin
Zo
Z L1 Z L2
Figure 32: Inverter driver with parallel termination.
⊲ Interconnects are terminated with the characteristic impedance at

the far end.
⊲ Drawbacks - the termination resistor consumes significant amount

of DC power when the output of the driver is at Logic-1.

AC Parallel Termination
1 Zo=50 Ohms 2
Vin
CT
Z L1 Z L2 RT
Figure 33: Inverter driver with parallel termination.
⊲ During state transitions, CT behaves as a short circuit −→

ZL2 = RT = 50Ω −→ perfect impedance matching.
⊲ During Logic-0 and Logic-1, CT behaves as an open-circuit −→ zero

DC power consumption of driver due to termination.
1
⊲ Design difficulties : ZT = RT + jωC T
varies with frequency. The
rising and falling edges of square waves contains a large number of
frequency components −→ a perfect impedance matching can only
be achieved for a specific frequency.
⊲ Deficiencies - When the transmitter is in an idle state

(high-impedance state), the line is very sensitive to noise because
the far end of the interconnect is floating.

Thevenin Termination
R1
1 Zo=50 Ohms
2
Vin
R2
Z L1 Z L2
Figure 34: Thevenin termination.
⊲ Floating input node of parallel termination in the idle states is

eliminated.
⊲ ZT = R1 ||R2 .
⊲ Drawbacks - DC power consumption exists regardless of the state of

the driver.

Impedance-Matching Networks
⊲ This section investigates the pros and cons of off-chip and on-chip
passive impedance-matching networks. In addition, it examines the
design of on-chip active impedance-matching networks. The
difficulties encountered in realization of off-chip and on-chip
termination resistors are studied. Various on-chip active
impedance-matching networks are investigated.

Impedance-Matching Networks (cont’d)
⊲ Difficulties encountered in realization of on-chip termination
resistors
⊲ 50Ω termination resistors can be realized using poly resistors due to
their low resistance and high accuracy (as compared to n-well
diffusion resistors).
⊲ Poly in standard digital CMOS processes is silicided to reduce sheet

resistance. Typical sheet resistance of poly of 0.18µm CMOS
processes : R2 ≈8Ω with ±30% errors.
⊲ A care should be taken for parasitic resistance of metal wires and

contacts (Typical 0.18µm CMOS processes : 0.07Ω for Metal layers.
8Ω/contact, and 2.5Ω/Via).
L Metal-1
Poly Contact
Figure 35: Poly resistors as impedance-matching networks.
RC RC L L
R= + + R2 = 8+8 . (76)
2 2 W W
⊲ The resistance of poly resistors can not be tuned to match the
characteristic impedance of interconnects.

⊲ Difficulties encountered in off-chip passive termination
⊲ The resistance of passive resistors has a large error.
Lead
PCB trace
Resistor
VIA hole
Figure 36: Passive resistor termination.
⊲ The leads of passive resistors, the PCB trances and vias (if not
surface-mounted resistors) introduce unwanted parasitic
capacitances and inductances that drive the impedance of the
resistors away from 50Ω −→ a perfect impedance matching using
passive resistors is difficult to achieve.

⊲ On-chip Active Termination
Vc Vc Vc Vc
V V V
I I I
I
Triode Symmetrical load Transmission gate (TG)
DN D2 D1 D0 V
MN M2 M1 M0
Digital trimming
Figure 37: Termination networks.

⊲ Triode - pMOS should be biased in deep triode to achieve better
linearity −→ small operation voltage range (i.e. Vsd must be small)
Pich-off
I
Vdd
Better linearity
Vc in this region Vdd-Vc
V
called
I deep triode
Triode
V
The slope (conductance) varies with Vc
Figure 38: Termination network realized using pMOS biased in deep triode.

⊲ Symmetrical load [7] - provide a large voltage range. The resistance
is approximately constant at both low and high operation voltage V .
Symmetric load
I
Vdd
M2 Pich-off M1
Vc DI
V
M1
I
M2
Symmetric load
DI
Vsat Vt V
Figure 39: Termination network using symmetric load.

⊲ Digital trimming [8]
The width of each transistor = 2N Wref , where Wref is the width of

the least significant bit transistor and N is the location of the bit.
Width range : All transistors are OFF, Wtotal = 0; All transistors

are ON, Wtotal = (1 + 2 + 22 + . . . + 2N −1)Wref .
All transistors , when ON, are biased in deep triode.
Table 3: Impedance matching using digital trimming
D2 D1 D0 Width Resistance
0 0 0 0 ∞
0 0 1 1Wref Rref
0 1 0 2Wref Rref /2
0 1 1 3Wref Rref /3
1 0 0 4Wref Rref /4
1 0 1 5Wref Rref /5
1 1 0 6Wref Rref /6
1 1 1 7Wref Rref /7

⊲ Low-Power Active Termination [9]
1 Zo 2
Figure 40: Low-power termination.
⊲ Both nMOS and pMOS are sized such that they provide 50Ω
resistance when biased in deep triode.
⊲ When V2 = VDD , pMOS is ON (triode) and nMOS is OFF. No DC

current flows through pMOS.
⊲ When V2 = 0, nMOS is ON (triode) and pMOS is OFF. No DC

current flows through nMOS.
⊲ Design difficulties : the propagation delay of the inverter must be

sufficiently small, as compared with the propagation delay of the
transmission line.

⊲ On-Chip Termination [6]
⊲ nMOS and pMOS transistors when biased in triode are

voltage-controlled resistors. The resistance, however, is highly
nonlinear unless biased in deep triode.
⊲ When biased in deep triode, the voltage swing of the variable

resistor is rather small.
⊲ Both nMOS and pMOS are biased in triode and connected in

parallel to provide a matching impedance for both HIGH and LOW
output stages of the driver.
Vc1
1 Zo 2
Vc2
Figure 41: Large-swing termination.

⊲ Self-Regulated Series Termination [10]
⊲ In series termination scheme, the voltage at the far end (node 2)

equals to the source voltage Vin due to Γf arend = 1 and the voltage
at the near end (node 1) equals to half of the source voltage when a
perfect impedance matching at th near end exists. When Zs <> Zo ,
reflection at the near end exists and V1 <> V2in .
⊲ V1 = V2in can be used as the criterion of whether a perfect impedance

matching exists at the near end, as shown in Fig.??. The
termination resistance is adjusted by controlling the supply voltage
of he pre-driver, which in turn controls Vgs (Vsg ) of the driver.
VC VRef
Comparator
VDD
Vin
Figure 42: Self-regulated series termination.

References
References
[1] E. Elmore, “The transient response of damped linear network with particular
regard to wide-band amplifiers,” J. Applied Physics, vol. 19, No. 1, pp. 55-63,
Jan. 1948.
[2] R. Poon, Computer circuits electrical design, Prentice-Hall, 1995.
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ELE-863 VLSI Circuits and Systems for Data

Fei Yuan, Ph.D, P.Eng.

Copyright (c) F. Yuan (1)

⊲ The materials covered in this chapter are an essential part of the

⊲ The materials of this chapter can be freely distributed for

Copyright (c) F. Yuan (2)

• Minimum Width of Interconnects

• Transmission Line Effect

Copyright (c) F. Yuan (3)

⊲ Typical interconnects encountered in ICs include metal layers,

Table 1: Scaling of interconnects.

Copyright (c) F. Yuan (4)

Copyright (c) F. Yuan (5)

⊲ Thickness of interconnects has been scaled down moderately, mainly

Copyright (c) F. Yuan (6)

Copyright (c) F. Yuan (7)

⊲ Definition of sheet resistance

⊲ n-well layers have a large sheet resistance (approximately

⊲ n+ layers without silicidation has a moderate sheet resistance

⊲ n+ and p+ layers with silicidation have a low sheet resistance

⊲ Poly layers in standard digital CMOS processes are silicided.

Copyright (c) F. Yuan (8)

⊲ Via resistance - for 3-metal CMOS technologies, Via12 (between

⊲ The sheet resistance of metal layers at low frequencies is small, and

⊲ The preceding values of the resistances of interconnects are in the

Copyright (c) F. Yuan (9)

where µ = µr µo is permittivity of the conductor, σ=conductivity of

Figure 1: Skin effect of interconnects.

⊲ The effective conducting area

A = πr2 − π(r − δ)2 = πr2 − π(r2 − 2rδ + δ 2 )

where we have neglected the 2nd-order term.

Copyright (c) F. Yuan (10)

⊲ Skin-effect induced resistance

Skin-induced resistance is proportional to the square-root of

⊲ Skin depth of typical interconnects

Table 2: Skin depth of interconnects at 100 MHz.

Interconnect Resistivity Skin depth 100MHz Skin depth 5GHz

Copyright (c) F. Yuan (11)

⊲ Uniform Scaling - both the width W and height H of

⊲ SW = SH = S, where SW =scaling factor of width, SH =scaling

⊲ When L−→ SLL , W −→ W H

where R and R̂ are the resistance of interconnects before and after

Copyright (c) F. Yuan (12)

The resistance of local interconnects grows linearly with the scaling

⊲ For global interconnects, we have L̂ = SL (L grows in proportion to

The resistance of global interconnects rises cubically with the

Copyright (c) F. Yuan (13)

Height reduction 15% Height reduction 7%

6700A 5700A 5300A

0.5u 0.32u 0.23u

Figure 2: Selective scaling of interconnects (metal-1 of 0.35, 0.25, 0.18µm technologies).

⊲ For local interconnects : R̂ = SR.

⊲ For global interconnects : R̂ = SR.

⊲ The resistance of interconnects, both local and global, increases

⊲ Selective scaling scheme has been adopted in VLSI scaling.

Copyright (c) F. Yuan (14)

Figure 3: Area capacitance of interconnects.

⊲ Area capacitance Ca of an interconnect is the capacitance between

⊲ Area capacitance deceases with technology, mainly due to the

Copyright (c) F. Yuan (15)

Figure 4: Fringe capacitance of interconnects.

⊲ Fringe capacitance Cf is the capacitance between the side walls and

⊲ Fringe capacitance increases with technology, as compared with