Chapter 3 The Metal Layers

CMOS
Circuit Design, Layout, and Simulation
Third Edition
R. Jacob Baker
 Introduction
The metal layers in a CMOS integrated circuit connect circuit elements (MOSFETs,
capacitors, and resistors).
In the following discussion we'll discuss a generic CMOS process with two layers of metal.
These levels of metal are named metal 1 and metal2. The metal in a CMOS process is either
aluminum or copper. In this chapter we look at the layout of the bonding pad, capacitances
associated with the metal layers, crosstalk, sheet resistance, and electromigration.

• 3.1 The Bonding Pad

The bonding pad is at the interface
between the die and the package or
the outside world. One side of a wire
is soldered to the pad, while the other
side of the wire is connected to a lead
frame, as was seen in Fig. 1.3. Figure 3.1
shows a close up of a bonding pad and wire.
In this chapter we will not concern ourselves with electrostatic discharge (ESD)
protection, which is an important design consideration when designing the pad.
• 3.1.1 Laying Out the Pad I
• The basic size of the bonding pad specified by MOSIS (Metal Oxide
Semiconductor Implementation Service) is a square 100 um x 100 um
(actual size). For a probe pad, used to probe the circuit with a microprobe
station, the size should be greater than 6 um x 6 um.
• Capacitance of Metal-to-Substrate
Before proceeding any further, we might ask the question, "What is the
capacitance from the metal2 box (pad) in Fig. 3.2 to the substrate?" The
substrate is at ground potential and so, for all intents and purposes, it can be
thought of as an equipotential plane.
• Example 3.1
Estimate the parasitic capacitance associated with the pad in Fig. 3.2. The
capacitance associated with this pad is the sum of the plate (or bottom)
capacitance and the fringe (or edge) capacitance. We can write

• The area of the pad is 100 um2 square (100 um by 100 um), while the
perimeter of the pad is 400 um. Using the typical values of capacitance
for metal2 to substrate in Table 3.1 gives
• Table 3.1 Typical parasitic capacitances in a CMOS process. Note that while
the physical distance between the layers decreases, as process technology
scales downwards, the dielectric constant used in between the layers can
be decreased to keep the parasitic capacitances from becoming too
significant. The values are representative of the parasitic in both long- and
short-channel CMOS processes.
• 3.2.1 Metal1 and Via1
Metal1 is a layer of metal found directly below metal2. Figure 3.4 shows an
example layout and cross-sectional view.
The via1 layer connects metal1 and metal2. The via layer specifies that the
insulator be removed in the location indicated. Then, for example, a tungsten
"plug" is fabricated in the insulator's opening.
When the metal2 is laid down, the plug provides a connection between the
two metals. Note that if we were to use more than two layers of metal, then
via2 would connect metal2 to metal 3, via3 would connect metal3 to metal4,
etc.
• An Example Layout
• Figure 3.5 shows an example layout using the n-well, metal1, via1, and
metal2 layers. It’s important that, before proceeding, this layout and the
associated cross-sectional view are understood.
• For example, how would our cross-sectional view change if we moved the
cross-sectional line used in Fig. 3.5 down slightly so that it only intersects
the n-well and the metal2 layers?
• Answer: the cross-sectional view would be the same as seen in Fig. 3.5
except that the metal1 and via1 layers wouldn't be present.
• 3.2.2 Parasitics Associated with the Metal Layers
Associated with the metal layers are parasitic capacitances (see Table 3.1) and resistance.
Like the n-well, the metal layers are characterized by a sheet resistance.
However, the sheet resistance of the metal layers is considerably lower than the sheet
resistance of the n-well. For the sake of examples in this book, we'll use metal sheet
resistances of 0.1 Ω/square. Also, there is a finite contact resistance of the via. The
following examples illustrate some of the unwanted parasitics associated with these layers.

Example 3.3
Estimate the resistance of a piece of metal 1 1 mm long and 200 nm wide. What is the
drawn size of this metal line if the scale factor is 50 nm? Also estimate the delay through
this piece of metal, treating the metal line as an RC transmission line. Verify your answer
with a SPICE simulation.
The drawn size of the metal line is 1 mm/50 nm (= 20,000) by 200/50 (= 4).
Figure 3.6 shows the layout of the metal wire (not to scale). The line consists of
1,000/0.2 = 20,000/4 = 5,000 squares of metall.

• Figure 3.6 Layout and cross-sectional view with parasitics for the metal line in Ex.
3.3.
To calculate the resistance of the metal line, we use Eq. (2.3)
To calculate the capacitance, we use the information in Table 3.1 and either Eq.
(3.1) or (3.2)
or the capacitance for each 200 nm by 200 nm square (4 by 4) of metal 1 is

The delay through the metal line is, using Eqs. (2.32) or (2.33)

Or
The delay of a metal 1 line (with nothing connected to it) is 28 ps/mm when the
parasitic capacitance and resistance are the limiting factors. The SPICE simulation
results are seen in Fig. 3.7. _
• 3.3 Crosstalk and Ground Bounce
Crosstalk is a term used to describe an unwanted interference from one
conductor to another. Between two conductors there exists mutual capacitance
and inductance, which give rise to signal feedthrough. Ground bounce (and VDD
droop) are terms describing local variations in the power and ground supplies at a
circuit. While crosstalk is only a problem for time-varying signals in a circuit, ground
bounce can be problematic for both time varying and DC signals.
• 3.3.1 Crosstalk
• Consider the two metal wires shown in Fig. 3.16. A signal voltage propagating on
one of the conductors couples current onto the conductor. This current can be
estimated using

• where Cm is the mutual capacitance, Im is the coupled current, and VA is the

signal voltage on the source conductor.
• The voltage on the other conductor is measured. The mutual inductance is
determined using

• where IA is the injected

(time-varying) current
(the input signal), Vm is the
induced voltage (the output
signal), and Lm is the mutual
inductance.

• Crosstalk can be reduced by

increasing the distance between adjacent
conductors.
• 3.3.2 Ground Bounce
DC Problems, AC Problems
Ground bounce (and VDD droop)
are terms describing local
variations in the power and
ground supplies at a circuit.

Ground bounce, whether at

the IC, PC board, or system
level is a transient voltage
difference between the ground
reference points in two parts of
a circuit. In all
• 3.2.3 Current-Carrying Limitations
• Now that we have some familiarity with the metal layers, we need to answer
the question, "How much current can we carry on a given width or length of
metal?" The factors that limit the amount of current on a metal wire or bus
are metal electromigration and the maximum voltage drop across the wire or
bus due to the resistance of the metal layer.

• A conductor carrying too much current causes metal electromigration. This

effect is similar to the erosion that occurs when a river carries too much
water. The result is a change in the conductor dimensions, causing spots of
higher resistance and eventually failure. If the current density is kept below
the metal migration threshold current density, JAl, metal electromigration will
not occur. Typically, for aluminum, the current threshold for migration
• MOSIS
• MOSIS (Metal Oxide Semiconductor Implementation Service) provides chip design tools and related
services that enable universities, government agencies, research institutes and businesses to prototype
chips efficiently and cost-effectively.
• Operated by the University of Southern California's Information Sciences Institute (ISI), MOSIS combines
customers' orders onto shared multi-project wafers that speed production and reduce costs compared
with underutilized single-project wafers. Customers are able to debug and adjust designs, or to
commission small-volume runs, without making major production investments. Fabrication costs are also
shared by combining multiple designs from a single customer onto one "mask set," or wafer template.
According to MOSIS, the service has delivered more than 60,000 integrated circuit designs. [1]
• MOSIS was created in 1981 by ISI's Danny Cohen, an Internet pioneer who also developed Voice over
Internet Protocol and Video over Internet Protocol.[2] One of the first e-commerce providers, MOSIS also
launched the "fabless foundry" industry, in which vendors outsource chip orders rather than relying on
their own factories.[3] Thousands of students also have learned chip design in MOSIS-associate programs.
[4]

• Many early MOSIS users were students trying IC layout techniques from the seminal book Introduction to
VLSI Design (ISBN 0-201-04358-0) published in 1980 by Caltech professors Carver Mead[5] and
Lynn Conway.[6] Some early reduced instruction set computing (RISC) processors such as MIPS (1984) and
SPARC (1987) were run through MOSIS during their early design and testing phases.
• Passivation:
• Because an insulator is covering the pad (the piece of metal2) in Fig. 3.2, we
can't bond (connect a wire) to it. The top layer insulator on the chip is also
called passivation. The passivation helps protect the chip from
contamination. Openings for bonding pads are called cuts in the passivation.