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Chapter 2
The Well
CMOS
Circuit Design, Layout, and Simulation
Third Edition
R. Jacob Baker
• 2.4.3 Storage or Diffusion Capacitance
• Consider the charge distribution of the forward-biased diode shown in Fig.
2.16. When the diode becomes forward biased, electrons from the n-type
side of the junction are attracted to the p-type side (and vice versa for the
holes).
• We can characterize the storage capacitance, Cs, in terms of the minority
carrier lifetime. Under DC operating conditions, the storage capacitance
is given by
Figure 2.20 (a) Parasitic resistance and capacitance of the n-well and (b) schematic
symbol.
• Distributed RC Delay
• The n-well resistor seen in Fig. 2.20 is an example of a distributed RC circuit
(not a single, RC like the one seen in Fig. 2.21). In order to estimate the
delay through a distributed RC, consider the circuit seen in Fig. 2.22. The
delay to node A is estimated using
O. Lossy Transmission Line
Symbol Name: LTLIN
Syntax: Oxxx N1 N2 N3 N4 <model>
This is a single-conductor lossy transmission line. N1 and N2 are the nodes at
port 1. N3 and N4 are the nodes at port 2.
• Example:
O1 in 0 out 0 MyLossyTline
.model MyLossyTline LTRA(Len=1 R=10 L=1u C=10n)
• Model parameters for Lossy Transmission Lines
Name Description Units/Type Default