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ABSTRACT
Filtering data in real time requires dedicated Hardware to meet demanding time
requirements. If the statistics of the signal are not known, then Adaptive filtering
important feature of signal processing is coping with noise. To be able to achieve the
required output signal for a wide range of input signals and noise, it is desirable to be
able to adjust both the filter characteristics and the type of filter. In this way the
highlight a challenge within Evolvable hardware for Adaptive designs and that is to
find efficient ways in which sufficient genetic material will be available for the
Evolution process.
in which hardware is built on reconfigurable devices such as PLDs and FPGAs whose
as Genetic Algorithms, to adapt to the new environment. Present EHW researches are
all based on gate level evolution but here we go in for functional level implementation
be changed any number of times by downloading in to the device a software bit string
called the configuration bits. Field Programmable Gate Array (FPGA) and
devices.
represented as binary bit strings. This set is referred to as a population, and each
evaluated and a fitness score is assigned to each of them, the fitness score is some
predefined criterion. New individuals are created using genetic operators such as
no
To produce an adaptive filter with functional level EHW, we use the FPGA
model shown in Fig 3. The FPGA model is comprised of 6 columns, each containing
5 Programmable Function Units (PFUs). Each PFU can implement one of the
by the PFU is determined by the chromosome genes given to the PFU. Constant
generators are also included in a PFU. Columns in the architecture are interconnected
Adaptive filters learn the statistics of their operating environment and continually
filter. The adaptive filter provides a good case study for Adaptive design due to its
solution where the genetic algorithm and the evolving filter design itself are
signals occupying the same band of frequency. If the statistics of the noise are not
known a priori, or change over time, the co-efficients of the filter cannot be specified
representing the filter characteristics and the filter type to produce the filter response
required for the specification given, in addition, we test out the effect of noise on the
input signal and the filter’s ability to filter out the noise and still retain the required
response.
meet changing conditions in the input signal – in our case a generic algorithm is used.
The generator uses a reference signal which specifies the desired filter output. i.e the
IMPLEMENTATION
The implementation presented herein maybe termed as complete hardware
handle the creating of further generations. In addition, control hardware allows for
communication with the outside world. The third main feature is the evolving design
GA Pipeline
Control Evolving
Design
As shown in Fig. 5, GA-pipeline and the evolving filter are connected together by a
two way communication. Individuals are transferred to the filter and the filter
response (current output signal) for the current individual are fed back to the GA
pipeline for fitness evaluation. A given individual provides a set of coefficients for the
filter. The reference signal within the generator provides the filter specification i.e. the
required pass-band and stop-band to the GA pipeline. Control logic is not shown in
this figure.
Reference
GA Pipeline
Signal
Individual
Filter
The adaptive FIR Filter design is based on the multiply and Accumulate
structure shown in Fig. 6 This may be compared to Fig. 4 where the GA Pipeline is
the generator and the filter of the evolving design represents the delay line and
accumulator shown in the figure, the coefficients for the evolving design are those
So
……
TAP 0 TAP 2 TAP n
z
× D × D × D
Accumulator
Yo
FITNESS EVALUATION
In the case of a static design, the evolution process drives the evolving design towards
In the case of the adaptive filter there is one single sought solution i.e. the filter most
responds to the input signal in accordance with the reference signal to appear at the
output. The coefficient solution will vary with varying input signals to the filter and,
as such this type of design may be termed a dynamic design i.e. solutions vary over
time.
The fitness functions uses the response from the current filter i.e. the output of the
design represented by the current individual, to calculate a fitness value (Fit value) for
This value is calculated by accumulating the difference between the reference signal
itself (refsig) and the response from the filter (response) i.e. the output signal, for each
sample – i to n. The optimal solution sought is a fitness value of 0 i.e. 100% fitness.
n
Fit value = Σ | ref signal – responsei |
i =1
SIMULATION RESULT
CONCLUSION :
In this paper we have discussed in detail the concept of EHW. In particular,
we proposed and demonstrated that EHW employing evolution at the functional level
Since the EHW concept involves the evolution of desired hardware circuits by
down hardware design technology. The principle of functional level EHW is that both
the function of each PFU and the interconnections between them are dynamically
RESULTS:
This project was first simulated in C, using the same algorithms on the ones
ultimately implemented in the FPGA. Then this project was written in VHDL capable
of being synthesized. The core was simulated and synthesized using Xilinx. Some
experiments were conducted out using the population size of 32 and the genotype
length in 27 bits. These bits are split into 3 eight-bit ratios representing the 8-bit
concept and the remaining 3 bits to select the input signal to the PFUs.
In the selection mechanism is linear rank selection with elitism. Single point
crossover is taken mutation rate is set to 0.27 per bit. These rates are similar to those
used in ETL [11]. The desired response was achieved after 1131 generations. Only
16.27% of the FPGA is used at the operating frequency of 30MHz. This is still in
progress.
REFERENCES
1) A.E.Eiben, J.E.Smith, “Introduction to Evolutionary computing”, Springer
Verlag, 2003.
paper.
(ICES98).