VLSI

Design Hierarchy
Hierarchical design approach is usually adopted in designing VLSI integrated circuit.

It concentrates on the main operation or

function of the chip.
The input/output characteristic is decided.

It is the level where logic network circuit of

each functional block is designed

Circuit design level is the step where logic

network is transformed into transistors.

Physical design level involves

transforming the electronic circuit into
geometrical patterns termed as Layouts.

The final step of the chip design is chip

fabrication where physical integrated
circuit is fabricated and put into package
Layout Design Flow

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Placement
Device placement should be done considering following guidelines:

• Signal routing assisted Placement

• Keep devices near, which share same connection. It reduces interconnect lengths,
parasitic, makes connection easier.
• Try to keep local interconnect in lower metal without having to consume too
much of higher metal layers. It results in Routing congestion.
• Packed layout
• Device should be placed such that there are no empty space left.
• Avoid non rectangular shapes.
• Use Device in Fingers wherever possible.
• It reduces active capacitance
• Also reduces gate resistance along transistor width.
Signal Routing

Following points should be considered while signal routing:

• Min Capacitance:
• Always route signal with minimum overhang.
• Avoid serpentine connections
• Shielding :
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• Proper shielding should be done for critical signals.
• Electomigration:
• Width/Via consideration for EM requirements.
• Routing layers:
• Use only metal layers for signal connection.
Power Routing

Following points should be considered while power routing:

• Always ensure Proper meshing.
• Identify power hungry devices, e.g. derivers, which derives huge current
can cause significant IRDROP.
• Region of nwell and pwell should be identified as that would help in
estimating vdd and vss power line position.
Layout Verification
Layout Parasitic Effects
Experiments have shown that LPE parameters such as Shallow Trench
Isolation (STI)stress effect and the well proximity effect have
demonstrated the profound impact of layout variations on MOSFET
performance.
If these are not taken into account, they can lead to circuit failures.
Designers need to understand these new, complex barriers to compact and
accurate design so that these phenomena can be anticipated.
These phenomena may be considered small in the absolute sense, but to
attain very high precision, they may be significant.
WPE Effect
• Well Edge Proximity Effect (WPE) –During the p or n type well formation,
because of lateral scattering, the concentration of ions gets changed, which in
turn shifts the threshold voltage of MOS transistors
• During the implantations, lateral scattering of the ions nearby edges of the
photo-resist causes well doping concentration.

• This lateral non-uniformity in well doping causes the MOSFET threshold

voltages and other electrical characteristics to vary with the distance of the
transistor to the well-edge.
• This phenomenon is commonly known as the well proximity effect (WPE).
WPE Effect
• NMOS or PMOS that are close to the edge of a well will exhibit a
difference in threshold and Id from that of the device located remotely
from the edge.
• The WPE effect occurs to every MOS: standard VT , high VT , low VT ,
thick/thin oxide MOS.

This means two identically

built PMOS/NMOS
transistors side-by-side will
have different characteristics
due to their differing
distances from the n-well
edge.
WPE
• Layout Recommendations
• Extraction of leaf cells to be done taking into account all the n-well environment.
• WPE impact on Id and VT should be considered for circuit devices during their
placement w.r.t well edge.
• For matched devices WPE should be considered while matching
• Critical devices should be kept away from well edge.

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STI Effect
• The most prevalent isolation scheme is shallow trench isolation
• STI induced stress has been shown to have an impact on device
performance, introducing both Idsat and VT offsets.
• These effects are significant and must be included when modeling the
performance of a transistor.

• STI effect depends on

• Size of active: Poly to STI distance
• STI width

Compressive stress on si lattice

STI
SiO2 SiO2

pwell

Ptype Substrate
 STI Effect
• It has been shown that the residual stress and corresponding shift in electrical
performance can be qualitatively described by two geometric parameters, Sa and Sb
• These represent the distance from the gate to the edge of the OD on either side of the
device.

samin

s
b

s
a

MOSFET parameters such as VT, and Idsat have been shown to vary linearly with the
following function:
STI Effect

Sa/Sb= Distance between poly and

active edge
With the increase in Sa/Sb stress
decreases
Reliability & Signal Integrity

• Electromigration

• Latch up
• Cross talk.
Electromigration
Electromigration is the transport of material in a conductor under the
influence of an applied electric field.

When current flows through interconnect metal, the electrons upon

colliding with the metal ions, impart sufficient momentum and displace the
metal ions from their lattice sites creating vacancies

As technology is scaling down, electromigration is becoming a problem for

layout designers due to increased current densities.
 Effects of Electromigration
The damage should be observed at the
beginning and end of the metallization line.
This is because along the metallization line the
number of atoms arriving in a given local
volume is equal to the number of atoms leaving

the volume.

1. Depletion Of Atoms (Voids)

a) Interconnect Failure--Opens

2. Deposition Of Atoms (Hillocks)

b) Shorts
 Factors Affecting Electromigration
1. Wire Material
Pure copper used for Cu-metallization is more electromigration-robust than aluminum.
2. Wire Temperature
The temperature of the interconnect is mainly a result of the
• chip environment temperature
• self-heating effect of the current flow
• heat of the neighboring interconnects or transistors
• thermal conductivity of the surrounding materials
3. Wire Size

The current density is the ratio of current I and cross-sectional area A,

The wire width exerts a direct influence on current density (Keeping thickness to be constant)
So the wider the wire, the smaller the current density and the greater the resistance to electromigration
4. Wire Length
• There is a lower limit for the length of metal that will be subjected to the effects of EM.
• It is known as “Blech Length” & any metal that has a length below this limit will not fail by EM. This is
due to the mechanical stress buildup causes reverse migration process which compensates the effective
material flow.
Electromigration
Things To Remember While Designing layouts:-
● Calculate the Wire widths & number of vias for critical nets before starting layout
of any block
● Rapid width changes.
Crosstalk
Crosstalk is a phenomenon, by which a logic transmitted in wire creates
undesired effect on the neighboring wires, due to capacitive coupling.
A wire has high capacitance to its neighbor.
• When the neighbor switches from 1-> 0 or 0->1, the wire tends to switch too.
• Called capacitive coupling or crosstalk.

Crosstalk effects
• Noise on nonswitching wires
• Increased delay on switching wires
Crosstalk Noise due to Coupling Capacitance

• The disturbance at 'A' can potentially cause a disturbance at 'V‘ because of the mutual
coupling capacitance.
• If the disturbance at 'V' crosses Noise Threshold of the receiving gate 'R'
• logic at=theCc
Then it may change theVnoise output of* 'R' i.e., output of 'R', which is supposed to
Vaggressor
Cv+Cc
be at logic '1', might switch to logic '0', as it senses a logic '1' at its input, due to the
noise induced on its input by the disturbance at 'A'.
 Timing Degradation due to Coupling
Capacitance

• Consider input of driver 'D' switching from logic '0' to logic '1',thus the logic at node 'V'
switches from '1' to '0'.
• Now, if both 'A' and 'V' nodes have signal switching event at the same time interval, then,
due to noise induced by signal transition at aggressor 'A', a change in the timing instant of
the signal transition occurs at 'V‘.
• Due to this, the propagation delay of the driver 'D' increases by 'dt' amount of time, thus
increasing the overall propagation delay of the circuit, which might lead to potential setup
violation.
 Preventing Crosstalk
• Provide Shielding between critical signals.
• Increase spacing between critical wires.
Latch Up
Essentially in a CMOS design, where you have NMOS transistors next to
PMOS ones

The p-n-p-n junctions inadvertently make a pair of bipolar junction

transistors parallel to the MOSFETs.
When you switch one of them on you get a ton of leakage and the output
refuses to switch.
 Factors Initiating latchup
• Latchup is the generation of a low-impedance path in CMOS chips
between the power supply and the ground rails due to interaction of
parasitic pnp and npn bipolar transistors.
• These BJTs for a silicon-controlled rectifier with positive feedback and
virtually short circuit the power and the ground rail.
• This causes excessive current flows and potential permanent damage to the
devices.
Preventing Latchup
• Reduce the gain product of parasitic BJT’s
• Move nwell & n+ source/drain of PMOS farther apart increases the width of BJT
& reduces the gain.
• Reduce Rwell & Rsub
• Higher substrate/nwell doping levels reduces Rsub/Rwell.
• Guard Rings around p/n wells with frequent contacts to the ring reduces parasitic
resistance.
• If you also provide an electrical isolation between the NMOS and PMOS
regions, then you eliminate the connection between the parasitic BJTs
and thereby prevent latchup.

This diagram explains both shallow trench isolation and deep trench isolation.
THANKS