Experiment No.

13
Mealy Machine
Course Code: CPET 6L Program:
Course Title: Introduction to HDL Date Performed:
Section: Date Submitted:
Leader: 1. Instructor: Engr. Johnathan Richard A. Barrios
Members: 2.
3.
4.
5.
1. Objective(s):
The activity aims to simulate a Mealy Machine using VHDL codes.
2. Intended Learning Outcomes (ILOs)
The students should be able to:
2.1 Create VHDL Module, test bench and simulation diagram of a Mealy Machines.
2.2 Generate RTL Schematic Diagram of Mealy Machines.
2.3 Create a truth table of Mealy Machines in 10 ns.
3. Discussion:

Mealy Machine
A Mealy machine is a finite-state machine whose output values are determined both by its current state and the
current inputs. (This is in contrast to a Moore machine, whose output values are determined solely by its current
state.) A Mealy machine is a deterministic finite-state transducer: for each state and input, at most one transition is
possible.

4. Resources:
Computer System and Xilinx application
Spartan 601 Board (Optional)
5. Procedure:
1. Create a VHDL project (inside Xilinx application) file of a Mealy Machine.
2. Create the VHDL Module source code of Mealy Machine.
3. Create test bench of the Mealy Machine circuits.
4. Create a simulation timing diagram of Mealy Machine in 10 ns.
5. Generate RTL schematic diagram of Mealy Machine, identify the number of slices, 4 input LUTs and
bonded IOB’s.
6. Show the results on the space provided.
5.2.a Mealy Machine VHDL CODE 5.3.1 Mealy Machine Test Bench
Library IEEE; Library IEEE;
useIEEE.std_logic_1164.all; use IEEE.std_logic_1164.all;
entity MEALY is -- Mealy machine entity TB_MEALY is
port (X, CLOCK: in STD_LOGIC;
end;
Z: out STD_LOGIC);
end; architecture TESTBENCH of TB_MEALY is
architecture BEHAVIOR of MEALY is signal CLK : std_logic;
type STATE_TYPE is (S0, S1, S2, S3); signal X : std_logic;
signal CURRENT_STATE, NEXT_STATE: signal Z : std_logic;
STATE_TYPE; component MEALY
begin Port( X, CLOCK: in STD_LOGIC;
-- Process to hold combinational logic.
Z: out STD_LOGIC );
COMBIN: process (CURRENT_STATE, X)
begin end component;
case CURRENT_STATE is begin
when S0 => UUT : MEALY
if X = '0' then Port Map(X, CLK, Z);
Z <= '0'; -- CLOCK STIMULI OF 100 NS TIME PERIOD
NEXT_STATE <= S0; CLOCK: process
Elsif X = '1' then
begin
Z <= '1';
NEXT_STATE <= S2; CLK <= '0', '1' after 50 ns;
else wait for 100 ns;
Z <= 'U'; end process;
NEXT_STATE <= S0; -- X input STIMULI
end if; X_Stimuli: process
whenS1 =>
begin
if X = '0' then
Z <= '0'; X <= '0', '1' after 30 ns,
NEXT_STATE <= S0; 'U' after 60 ns;
Elsif X = '1' then wait for 90 ns;
Z <= '0'; end process;
NEXT_STATE <= S2; end TESTBENCH;
else configuration CFG_TB_MEALY of TB_MEALY is
Z <= 'U';
for TESTBENCH
NEXT_STATE <= S0;
end if; for UUT : MEALY
whenS2 => end for;
if X = '0' then end for;
Z <= '1'; end;
NEXT_STATE <= S2;
Elsif X = '1' then
Z <= '0';
NEXT_STATE <= S3;
Else
Z <= 'U';
NEXT_STATE <= S0;
end if;
whenS3 =>
if X = '0' then
Z <= '0';
NEXT_STATE <= S3;
Elsif X = '1' then
Z <= '1';
NEXT_STATE <= S1;
else
Z <= 'U';
NEXT_STATE <= S0;
end if;
end case;
end process;
-- Process to hold synchronous elements (flip-flops)
SYNCH: process
begin
wait until CLOCK'event and CLOCK = '1';
CURRENT_STATE <= NEXT_STATE;
End process;
end BEHAVIOR;
a. Sketch the resulting RTL Schematic
Number of Slices: _______

Number of 4 input LUTs : _______

Number of bonded IOBs: _______

5.4.1 Sketch of simulation timing diagram of the Mealy Machine
 6. Questions:
a. Relate the VHDL module to test bench.
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b. Discuss the behavior and architecture of a Mealy machine.

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c. Explain the behavior of the mealy machine’s test bench.
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7. Data and Results:
(Show the equivalent truth table of each logic gates in 10nano seconds)
Note: Write or indicate the input and output variable used in the program and give analysis sentence for
each table. You may change the column and rows of each table according to the number of input and
output used.
Table 13-1 Mealy Machine truth table in 10 ns
Every 10 ns Input Input(B) Output(F)

10ns 0 0 0

20ns 0 0 0

30ns 0 1 1

40ns 0 1 1

50ns 1 1 0

8. Conclusion:
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9. Assessment (Rubric for Laboratory Performance):