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Architecture
GOR AN WN I S H A MA A LI
INTRODUCTION
• The CPU sends various data values, instructions and
information to all the devices and components inside the
computer.
2. Address Bus
3. Control Bus
∗ Bus operations
» Read, write, block transfer, interrupt, …
∗ Bus arbitration
» Centralized or distributed.
∗ Bus timing
» Synchronous or asynchronous
Bus Type
• Dedicated buses
• Separate buses dedicated to carry data and address information.
• Good for performance.
• But increases cost.
• Multiplexed buses
• Data and address information is time multiplexed(defined in the next slide
) on a shared bus.
• Poor Performance
• But Reduces cost.
Time Multiplexed Bus
• Address and data information may be transmitted over
the same set of lines using an Address Valid control line. At
the beginning of a data transfer, the address is placed on
the bus and the Address Valid line is activated. At this
point, each module has a specified period of time to copy
the address and determine if it is the addressed module.
The address is then removed from the bus, and the same
bus connections are used for the subsequent read or write
data transfer. This method of using the same lines for
multiple purposes is known as time multiplexing. The
advantage of time multiplexing is the use of fewer lines.
Bus Operations
• Basic operations
• Read and write.
• Interrupt operation.
Bus Arbitration
• In all but the simplest systems, more than one module may need
control of the bus.
• For example, an I/O module may need to read or write directly to
memory, without sending the data to the processor.
• Because only one unit at a time can successfully transmit over the
bus, some method of arbitration is needed.
• Bus arbitration can be done either
Statically.
Dynamically.
Static Bus Arbitration
• Done in a predetermined way.
• For example , we might use round-robin allocation that
rotates the bus among the masters.
• Easy to implement.
• A master may be given a bus even it does not need it.
• This kind of allocation leads to inefficient use of the bus.
Dynamic Bus Arbitration
• Bus allocated only in response to a request.
• Each master is equipped with;
• Bus request line.
• Bus grant line.
• A master uses the bus request line to let others know that it needs
the bus.
• Before a master can use the bus, it must receive permission to use
the bus via the bus grant line.
Dynamic Bus Arbitration cont’d
• Distributed arbitration
• Arbitration hardware is distributed among the masters.
• A distributed arbitration algorithm is used to determine who should
get the bus.
Bus Allocation Policies
• Fixed priority
• Each master is assigned a fixed priority.
• Rotating priority
• Priority is not fixed
• Several ways of changing priority
• Increase the priority as a function of waiting time
• Lowest priority for the master that just received the bus
Bus Release Policies
• Governs the conditions under which the current master
releases the bus
• Two types
• Non-preemptive.
• Current master voluntarily releases the bus.
• Disadvantage
• May hold bus for long time.
• Preemptive
• Forces the current master to release the bus without completing its bus
transaction.
Non-Preemptive Bus Release Policies
• Transaction-based release
• Releases bus after completing the current transaction.
• Requests bus again if it has more transactions.
• Easy to implement.
• Unnecessary overhead if only one master needs the bus.
• Demand-driven release
• Avoids unnecessary bus requests of the previous policy.
• Releases the bus only if another master requests the bus.
• More efficient.
Centralized bus arbitration
• Daisy-chaining
• Uses a single, shared bus request signal
• Central arbiter sends the grant signal to the first master in the chain
• Each master passes the grant signal to its neighbor if it does need the bus
• Grabs the grant signal if it wants the bus
• Easy to implement
Centralized bus arbitration cont’d
• Independent requests
• Arbiter is connected to each master
• Variety of bus allocation policies can be implemented.
• Disadvantages
• Complex to implement.