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EARS SOLVED QUESTION PA

7 [B.Tech]
SIXTH SEMESTER
Microprocessors & Micro Controllers
(ETEE-310)

PRRRQe
AKASH BOOKS
NEW DELHI
 FIRST TERM EXAMINATION [FEB. 2016]
SIXTH SEMESTER [B.TECH]
MICROPROCESSOR AND |
MICROCONTROLLER [ETEE-310]
Time : 1% hrs. | M.M. : 30
Note: Attempt Q. No. 1 which is compulsory and any two more questions from remaining.
Q.1. Attempt any five.

Q.1. Attempt any five: | (5x2)

Q.1. (a) State the priority of execution of HOLD, RESET and INTERRUPT
signals. |
Ans. Priority of execution are:
1. HOLD |
2. INTERRUPT
3. RESET
Q.1. (6) Write a set of instructions to eanster logic 1 from the SOD line of
8085 microprocessor.
Ans. MVI A, OCOH
SIM ee Se
—

HLT BS |
Q.1. (c) How much time is taken by the microprocesser 8085 to execut
conditional CALL. Instruction of 8085 microprocessor if condition i is not true?
Assume Microprocessor is running at 2MHZ? \
Ans. CALL instruction— '9/ 18 T states
- If condition is not true 9 T states is used earaten. 18 will be used ©

Given frequency=2MHZ |

T=1/F =>0,5 microsec

Time is taken by the: microprocessor 8085= 0. 5*9'=>- 4. 5 microsec

Q.1. (d) State the function of TEST and LOCK signals of the mane
Seen

microprocessor.
Ans.1 (d) Refer Q.9. (c) of End Term Exam 2016.(Page No. 48- 2016)
Q.1 1. (e) Explain the LOOP instruction of microporcessor 8086 with suitable
examples.

LOOP label Decrease CX, jump to label if CX not zero. |

~ Algorithm:
CX =CX-1
“ifCX= 0 then

jump~
SS
es0 ter ; Micr; oprocessor and Microcontroller
Sixth Sem
9-2016
! [.P. University\(B.Tech)-AB Publisher 2016-3
else Q.2.(c) Write and explain a software delay routine for 8085.
~ (4)
no jump, continue Ans. To know how many T-States an instruction requires, and keeping in mind
that
a T-State is one clock cycle long, we can calculate the time using the followin
Example: g formula:
Delay = No. of T-States / Frequency
include ‘omu8086.ine’
Example: If the speed of your microprocessor is 2 MHz then for a “MVI’” instruction
#make_COM# uses 7 T-States. Therefore the instruction would require 3.5 u Seconds to complete.
ORG 100h Now we can use a loop to produce a certain amount of time delay in a program.
MOV CX, 5 See an example of a delay loop: .
labell: MVIC, FFH 7 T-States
PRINTN ‘loop!’ | a
LOOP: DCRC 4 T-States
LOOP labell a |
| JNZ LOOP ' 10 T-States
RET
gi cal an d Ph ys ic al .a dd re ss es ? I low th e phys ic al addresses. Here see the first instruction initializes the loop counter and is executed only once
Q.1. (f What are Lo a ‘requiring only 7 T-States.
are generated? BX , SI or DI. It ts ceed
d in the 16 bi t IP, BP , SP ,
Ans. Logical address is containe
The following two instructions which is inside a loop that requires 14 T-States to
a execute and is repeated 255 times until C becomes 0.
known as the offset address or the effective address.
The base segment address is contained in one of the 16 bit contents of the| segment | We need to keep in mind though that in the last rotation of the loop, the JINZ
| | | s a instruction will not jump to the address and so it requires only 7 T-States rather than
registers CS, DS, ES, SS.
the 10. | :
The physical address or the real address is formed by combining the offset and
base segment addresses. This address is 20 bit and is primarily used for the accessing of ¢ Therefore, we must deduct 3 T-States from the total delay to get an accurate
ae delay calculation. | :
the memory.
~~ uy

94h ; Si

with i -
i, {Ore

_ Physical Address = Base Address *10H + Logical Address. | a

pt
Ol a
ee
“
© To calculate the delay, we use the following formula:
Q.1. (g) Which among the following two instructions will be executed faster Tastes a To. Ty | :
and why? MOV AX, [1000H] and MOV AX, [1001H]. 7 sc i T gelay = total delay; T, = delay outside the loop ; T, = delay of the loop
Ans. Both instruction will take equal time for execution. Now using these formulas, we can calculate the time delay for the above mention!
Q.2. (a) Write a program for 8085 to generate fibonacci series. - example:
Ans. MVI D, COUNT ; Initialize counter As oe Ti Ty = 7 T-States Delay of the MVI instruction
MVIB, 00; Initialize variable to store previousnumber ~~ es We 4 *T. = (14 x 255) -3 = 3567 T-States (14 T-States for the 2 instructions repeated
MYVI C, 01 ; Initialize variable to store current number 255 times). | | 3 |
ae
MOV A, B ; [Add two numbers] Now your microprocessor speed is 2 MHz. So we know
BACK: ADD C ; [Add two numbers] T (time for one T state) = I/F
MOV B, C; Current number is now previous number = 2 x 10° sec

MOV C,A; Save result as a new curren

t number hee.
DCR D ; Decrement count -So now we have 3567 T-state so we will get 3567 x .5 psec = 1.7835 m sec of delay.
JNZ BACK ; if count 0 go to BA | (2)
CK Dia
Q.3. (a) Explain the Align and DUP assembler directives.
HLT ; Stop. | ‘Ans, EVEN directive: This directive is used to Align the word boundary
to ~
ieQ.2. (b) Write an iintr 4 segment a address for fast er access. Supp ose we have a data seg men t named as
ie alliodas lecc direct JUMP instruction to jump bac next even
ds_segment, then: Ste , . eee: ‘|
ins. JMPSHORT abel e DS_segment SEGMENT: me
IMP NEAR Label a ahe
(i
\ 7

© es
Num1 db 05h
Short ,jump range(— 127 <d <4 ~ ars | ) | 2
128) Word1 dw 1234h
Long jump range(-32767<4<439768)
 As
2016 Sixth Semester, Microprocessor and Microcontro}}
er

Char db ‘X;
statement.
i c e s D B 5 D U P ( ? ) : A n a rray of 5 bytes I.P. University-(B.Tech)-AB Publisher
Pr 2016-5
ss.
which is an odd addre ae
ter to 0(00AH ie IORC, IOWC are I/O read command and I/O write command signals respectively
EVEN: increment location coun .

ae
en Address These signals enable an IO interface to read or write the data from

gee
or to the addressed
MyData DW 50 DUP(0): Array of 50 words will gt : port. The MRDC,
; ar MWTC are memory read command and memory write command
{ro Man e

r
DS-segment ENDS: r ven addregg signals respectively and may be used as memory read and write signals. All thes

a
e
DB Defined Byte: DB declares a va command signals instruct the memory to accept or send data from or to the bus. For
riable of type byt. . 7
memor y for, the variable of type byte. both of these write command signals, the advanced signals namely AIOWC and AMWTC
Te ee end Teserves ono locationtion init
Exam le: num1 DB 15h, Char] db \ in ) y
are available. They also serve the same purpose, but-are activated one clock cycle
5i earlier than the IOWC and MWTC signals, respectively.
numbers db 100 dup(0); Reserve 7 i | ae.
ei :
an array of 50 words of memory eS :
bytes with 00. Q:3. (c) Design a microprocesser 8086 system having two 4K x 8 EPROM
Aer andi and four 8K x 8 RAM. Avoid any foldback address. : (4)
Array is named as numbers.
Ans. A system requires 16kb EPROM and 16kb RAM. Also
DUP stands for duplicate 2 numbers of 8255, one number of 8279, one number of 8251 and one number of 8254.
the system has

(8255 - Programmable peripheral interface; 8279-Keyboard/display controller,

8251 - USART and 8254 - Timer). Draw the Interface diagram. Allocate addresses to
all the devices. The peripheral IC should be I/O mapped.
Ans. The maximum modes SAT?

° The I/O devices in the system should be mapped by standard I/O mapping. Hence
diagrams. The address/data
and address) separate decoders can be used to generate chip select signals for memory IC and
minimum mode. The only difference lies in mode. ALE is asserted in T1, just like peripheral IC’s. |
the status signals used and the cvanaail
:
. Lhe fig. shows the same for the write operation, — ¢ For 16kb EPROM, we can provide 2 numbers of 2764(8k x 8) EPROM.
1, 4 T, t, | ag 4 e For 16kb RAM we can Srowde 2 numbers of 6264-(8k x 8) RAM.

SB eee ¢ The 8kb memories require 13 address lines. Hence the address lines AO - Al2 are
oC | a J ra fiz t=, | SCR eaae 2s a used for selecting the memory locations.- .
hee Oe aere One pus Y de Li TE a % _ ©The unused address lines A13, Al4 and A15 are used as input to decoder 74LS138

ALE sb gs Pd x 2 ; : (3-to-8-decoder) of memory IC. The logic low enables of this decoder are tied to IO/
-
M(low) of 8085, so that this decoder is enabled for memory read/write operation. The
other enable pins of decoder are tied to appropriate logic levels permanently. The 4-
| S,-S, | Active | | —
outputs of the decoder are used to'select memory IC’s and the remaining 4 are kept for
ADD/STATUS__X_X BHE_X_Sr= 53 future expansion. - |

— | Ded ¢ The EPROM is mapped in the beginning of memory space from 0000H to 3FFF.
X Data outys——a
ADDIDATA —_)—KArs—Aa x
¢ The RAM is mapped at the end of memory space from C000 to FFFFH.
AD,s5 raat AD
¢ There are five peripheral IC’s to be interfaced to the system. The chip-select
AMWC
AIOWC signals for these IC’s are given through another 3-to-8 decoder 74LS138 (I/O
The input to this decoder is All, A12 and Al3
decoder).

WNC ce and appl ied to low enable

- Towe °* Bae ts The addr ess lines A13, Al4 and A15 are logic ally ORed
of I/O decoder.
ble of I/O dec ode r is tie d to 10 / M(l ow) sig nal of 8085, so that
e The logic high ena
-_

.
this decoder is enabled for I/O read/write operation
 I.P. University-(B.Tech)-AB Publisher
2016-7
MOV BX,[2000H] ; take lower 16-bit of NUM2
in BX
ADD AX,BX ; AX
= AX + BX

MOV [3000H],AX ; Store lower 16-bit result at NUM3

MOV AX,[1002H] ; take higher 16-bit of NUM1 in AX

MOV BX,[2002H] ; take higher 16-bit of NUM2 in BX

ADC AX,BX ; AX = AX + BX + CF (add with carry)
MOV [3002H],AX ; Store higher 16-bit result at NUM3

HLT ; Halt 8086

Q.4. (6)Explain LEA instruction of 8086. Explain how it differs from MOV
instruction with a suitable example? (2)
Ans. The MOV (move) instruction transfer data between memory and registers or
between registers. The MOV instruction performs basic load data and store data
operations between memory and the processor’s registers and data movement operations
between registers.The MOV instruction cannot move data from one memory location to
another or from one segment register to another segment register. Memory-to-memory
moves are performed with the MOVS (string move) instruction.
The LEA (load effective address) instruction computes the effective address in
memory (offset within a segment) of a source operand and places it in a general-purpose
register. This instruction can interpret any of the processor’s addressing modes and can
perform any indexing or scaling that may be needed.
ab

LEA BX, 2000H ; 2000 is the effective address

MOV BX, 2000H ; 2000 is the data
Q.4. (c) Draw and explain the maximum mode configuration of 8086?

Ans, Maximum mode 8086 system and timings:

In the maximum mode, the 8086 is operated by sLrapping the MN/MX* pin to
ground. In this mode, the processor derives the status signals S2*, S1* and SO*. Another
chip called bus controller derives the control signals using this status information. In
the maximum mode, there may be more than one microprocessor in the system
configuration. The other components in the system are the same as in the minimum
mode system. The general system organization is as shown in the Fig.

The basic functions of the bus controller chip IC8288, is to derive control signals
Fig. Memory and I/O Port Interfacing with 8085 like RD* and WR* (for memory and I/O devices), DEN*, DT/R*, ALE, etc. using the
Q.4. (a) Write a program for 8086 microprocessor to add number of 16 byte — information made available by the processor on the status lines. The bus controller
chip
by the CPU.
each? 7 | (4) a. has input lines S2*, S1* and SO* and CLK. These inputs to 8288 are driven
DEN*, DT/k*, MWTC*, AMWC*, IORC*, IOWC* and
Ans. MOV AX,5000H ; Initialize DATASEGMENT It derives the outputs ALE,
The AEN*, IOB and CEN pins are special ly useful for multip rocessor systems.
~~ ATOWC*.
MOV DS,AX ; to 5000H | AEN* and IOB are generally grounded. CEN pin is usually
tied to +5V.

MOV AX,[1000H] ; take lower 16-bit of NUM1 in AX

 8—20 16 Siixthxth SeSememest
ster
er, Mi
Microprocessor and Microcontro]
‘O]ller

SECOND TERM EXAMINATION [APRIL-2016]

in SIXTH SEMESTER [B.TECH]
wore a MICROPROCESSOR AND
sas MICROCONTROLLER [ETEE-310]
we eee = RAL Time: 144 hrs. MLM. : 30
lopie jl: CSe ROM : | Note: Attempt Q. No. 1 which is compulsory and any two more questions from remaining.
ee ~ ~ ROM _ Q.1. Attempt any five.
‘ See ae " i Q.1. Attempt any five: (5x2)
= B-sg a Q.1. (a) What is the function Al and AO lines in 8254?

i Al AO Selects
I
| @ | 0 0 Counter 0
aaa | as q 0 0 Counter 1
a : 1. 0 Counter 2 |
So ag . 1 Co 1 _ Control Word Register
4 HORC ; ¢ Q.1. (b) What do you mean by Read Back Command in 8254.
ae
ey Ans. READ-BACK COMMAND. This command allows the user to check the count
3 value, programmed Mode, and current states of the OUT pin and Null Count flag of the
-_ selected counter(s). |
4 Read-Back Command Format

_— | a0,A1=11 CS=0 RD=1 WR=0

| i ~D,D, Ds Dy, Ds D> D, Do

eae Mode 8086 Systeeee _= -

1|CNT
414— \GountStatus| CNT 2] CNT le q QO
fa Fig. Maximum
ae a D,: 0 = Latch count of selected counter(s)
The signifi | ee, eS : D,: 0 = Latch status of selected counters(s)
pin. If nee icance of the MCE/PDEN* output depends
1s grounded, it acts as master cascade nahi 5 upon the status oftheIOB D,: 1 = Select Counter 2
it acts as peripheral data enable used jn th € to control cascaded 8259A:else | D,: 1 = Select Counter 1
used to issue two interrupt acknowled e multiple bus configurations INTA* pin is - D,: 1 = Select Counter0
edge pulses to the interrupt controller or toan ; Dy: Reserved for future expansion: Must be 0
interrupting device.
fer enc e be tw ee n MO V and MO VX ins tru cti on of 8051.
Q.1. (c) Explain the dif
on tra nsf ers dat a bet wee n the acc umu lat or and external
Ans. The MOVX instructi DP TR register or
y be add res sed via 16- bit s in the
data memory. External memory ma sin g, Por t 2 mus t contain
en usi ng 8-b it add res
‘via 8-bits in the RO or R1 registers. Wh
the high-order byte of the address.
i
MOVX @Ri, A The
wee n the two spe cif
cif ied
ie ope ran ds.
bytes bet
The MOVV i instruction moves data to the loc ati on spe cif ied by the first
e spe cif ied by the sec ond operand is copied
byt
Th e so ur ce da ta by te is no t affected.
operand.
te
MOV @Rn, #immedia
; 10-2016 Sixth Semester, Microprocessor and M icrocontroller

LP. University-(B.Tech)-AB Publisher 2016-11

Q.1. (d) Explain EA and PSEN signals of 8051.
| P PSW.0 Parity flag. Set/cleared by hardware each instruction cycle to
Ane EA
The 8051 family members, such as the 8751/52, 89C51/52, or DS89C4 0 pecans RTO aes an odd/even number of 1 bits in the accumulator.
with on-chip ROM to store programs. In such cases, the EA pin is connect a come RS1 —RSO Register Bank Address
For family members such as the 8031 and 8032 in which there js no ined 5 Veo 0 0 0 a
code is stored on an external ROM and is fetched by the 8031/32. Therefo ye | 0 : ; Eee
| 1 0 - LOH - 17H
8031 the EA pin must be connected to GND to indicate that-the cod a ‘Or the
| 1 1 3 18H - 1FH
externally. EA which stands for "external access," is pin number 31 in ta
a 4. = a # and ae be connected to either V.. or GND. tn off | Bits of the PSW ces
ae
| | Q.1. (g) Expain the ACK and OBF signals of 8255.
PSEN Soe er falls to low, indicates
| 4 Ans. OBF (Output buffer full) — This status signal, whenev be set by
This is an output pin. PSEN stands for * " program 4 writte n data to the specifi ed output port. The OBF flip-flop will
store enable." I - that CPU has edge at the ACK input.
system in which an external ROM holds WR sig nal and res et by al ow going
the program code, this pin is connectedfel | a rising edge of
OE pin of the ROM. 0 l @
K sig nal act s as an ac kn ow le dgement to be given
° ACK (Acknowledge input ) AC
ev er low , in fo rm s the CP U th at the data transferred
@-1. ee Te the display RAM section of 8279. ; a by an output device. ACK s ignal, when is received by the output device.
Ans. Display Address Registers and Display RAM: | | is bv the CPU to the output device through the port
hold the addresses of the word cur ; Saree : The Display address registers _a : : to i
8086 using 8285 and write Assembly:
: Motor in Clakwisd direction and in
.
oes a < or read by the CPU to or from the } nee Ee cat ec Lage
display RAM. The contents of the Sterfaced with 8086 in memory
Gees omatically updated by 8279 to accept a aOR ee. : Ege e hat 8255 is in
the next data entry by CPU. The 16-b
RAM contains the 16-byte of data tobe OS: os
‘Ul SvePP1(O). (6)
displayed on the sixteen 7-seg
: displ aysaie
in a.
Q.1. () Name the various iy Sa Ss — | q on eae Stepper Motor to 8086 using 8955 and write Assembly Language
| a | : to rotate Stepper Motor in Clockwise & Anticlockwise
Antic direction.
: 8051 FLAG BITS AND THE PSW REGISTER:: The 8051 has a flag register 2 Program
Ans.
t * = . - . ©

& : | Reference
PON ) register. In this secti i ‘tsof me : 7 PhA mark
this register and provide some examples of how
it is slieed: we epee eno a
PSW (program status word) register .
|
eee

a beget ee Although the PSW register is 8 bits wide, only 6 bits of it are
ge a unused bits
used by the _
are user-definable flags. l‘our of the flags are called | ;
Eee oe ae aaa that they indicate some conditions that result after an 7
ae | ecuted. These four are CY (carry), AC (auxiliary carry), P (pari
me
y), P (parity), and
overflow).
ogee oe PSW.4 are designated as RSO and RSI, respectively, andare __
See stig e ban! registers. They are explained in the next section. The PSW.5 |
- bits are general-purpose status flag bits and can be used bythe programme
r
for any purpose. In other words, they are user definable.
Permanent
CY |AC|Fo0/RS1|Rsolov |-|P : * A magnet
_
-

mY: PSW.7: Carry fla g. rid motor

AC
. Oo-
PSW.6
hase
Auxiliary Carry flag s-section of a two-P hyb
n control of rotating
:

Fig. Cros te positio

is a device used to obta in an: accurate ther than continuo ee
FO
easPSW.5 Available
| to th e user for general
3 purpose Stepper moto :
| r
shafts. Astepper motor employs rotato nof itsSSshaftthein shaft the stepper
terms ofof steps, tf motor, a sequence
4 Register Bank selector bit 1.
,= ne Se
rotation asA in case of AC igor ae of the ofstepper
anerotation the motor,
shaft of the Proper r ae
in steppe
as) SWS Register Bank selector bit 0.
2
| of pulses yi eee for complete
oY PSW.2 Overflow flag. ;
Thenumbers 0
—= PSW.1 User-definable bit.
 12-2016 Sixth Semester, Microprocessor and Microcontroll er ivsi
; her 2016-13
Uner
L.PP.. Univ ersity-(B.Tech)—AB Publis

of inte rnal te et h on its ro tor. T! re.statort

equal to the number ¢
th a pu ls e a r ot an d th e r npteeyt hlogck
rotoei COD E
with each other to fix a position of the sh af t. Wi
gl e Be se to the windin g
ti an
on or an gl e x. th e an
ta te s by -o ne te eth posi
roter ro
ies calculated aay 7. iY. 4: @DATA
x = 3600 / no. of rotor teeth 5
After the rotation of th Be eee
i l a i eeicer re1e —5 e d locks it ‘ self with th .
pele
typical schema tie
e
toot h in th e se qu en ce ms the S
ace
or.
:
fo ur wi ndings is as shown
a.
.
stepper motor with INS
t c ; os
.
designed to work with digital circuits. Bj
MOV AL,PHASEC
ae Sr eras ae
, ORTO
MOV DX,P
de d, Fi : a ts to obta in th e ro ta ti on of th e sh afaftts. ee
The
sequence of the sites can = deci epending upon th OO
pu ls es th e mo tor ca n ie us ed ce ar e e e e of the shai MOV CX,0FFFFH
By suitable sequence of the )
modes of oper ation.
One phase ON (medium torque eee

ON (high torque) LOOP UP

phase
MOV AL,PHASEB
Two
Half stepping (low torque) ;
a D Hex value Be MOV DX,PORTC
| Steps | A B C
OUT DX,AL
MOV CX,0FFFFH
0 0 1 ;
Clockwise 1
03H a
2 pode gle 4 UPI:
| 7 ‘ 06 H
3 1 1
0C H LOOP UP1
4 ae : : s MOV AL,P HASED
09H -i ,
5 0 ie a. MOV DX,PORTC
03H
_| Anticlockwise 1 0 : A 1
03 H 7 _ OUTDX,AL
: : Oak MOV CX,0FFFFH
; 5; : Om F2 1 09 H
OCH 5 UP2:
0
4 5 0
06H ~ a LOOP UP2
: : 14170 MOV AL,PHASEA
00H -
0 0 MOV DX,PORTC
/-
— 5 OUT DX,AL
i @/
is interfaced with 8086 in I/O mapped I/O. 3 :
a re) is @ MOV CX,OFFFFH

OOH
used a s s i

|
P

,
55

im
e 82

a c
ee ee to stepper motor. Th 7

os it
n o mg n
UP3:

i nn
g an
a r
ee

it h
will oaech a
ew
se
d
ot e:
p
g
a
in
h
nd
g
th e wi

n g
coils so each of
tr
be int
put y
nnd n
to be sa te ct unnd dvin gaa motor
need s OUTPUT SEQUENCE
echa 4 JMP AGAIN ; REPEATE
ion to ite eee Output the sequence in sacr
th e de si re d di rect INT 03H
en to aes +
)
sembly Language Progerram t o rotate Stepper Motor in Clockwis
e direction =~ : END START
m to ro ta te Stepper Mo to r in An ti cl oc kw is e di re ction
MODEL SMALL Assembly La ng ua ge Pr og ra
4
ee 100 p MODEL SMALL
ss s F STACK 100
ORTA EQU FFCOH ; PORTAADDRESS |. ‘DATRTAA EQU PORTA ADDRESS
RTB ADDRESS
PORTB EQU FFC2H ; PORT S PO FFCOH
PORTB ADDRESS
C ADDRESS PORTB EQU FFC2H
PORTC EQU FFC4H ; PO =
RT ADDRESS
CWR EQU FF C6 H ; C O N T R O L PO
=a. PORTCEQBQ U F O U PNT e
RO L eP : A D D R E S S
U FFC6H ; CO
PHASEC EQU 03H | SE RI ES TO RO TA TE MO TO R
PHASEA EQU 09H ; SRQUENCE IN
-_ ss. EQU 03H
E s
>PHASEaB sa 06H ; SEQUENCE IN SERIES TO ROTATE MOTOR
EQU 0C H ; IN C L O C K W I S E DI RE CT IO N
HASED
PHASEA EQU 09H
 14—2016 Sixth Semester, Micr
oprocessor an d M
icrocon troljey
PHASED EQU 0CH: INANT ICLOCKWISE p :
PHASEB EQU 06H EDI RECTION
I.P. University-(B.Tech)—-AB Publisher 2016-15
-CODE
Assume that an analog input is present at I/P, of the ADC and a clock input of
suitable frequency is available for ADC.
¢ Solution: The analog input I/P, is used and therefore address pins A,B,C should
MOV DX,CTL be 0, 1, 0 respectively to select I/P,. The OE and ALE pins are already kept at +5V to
OUT DX, AL select the ADC and enable the outputs: Port C upper acts as the input port to receive the
EOC signal while port C lower acts as the output port to send SOC to the ADC.
AGAIN:
¢ PortA acts as a 8-bit input data port to receive the digital data output from the
MOV AL,PHASEC ADC. The 8255 control word is written as follows:
MOV DX,PORTC
D D, D; D, Dz; D, VY,
OUT DX. AL | a £20 is i 8 O20
¢ The required ALP is as follows:
MOV AL, 98h -initialise 8255 as

OUT CWR, AL discussed above.

AL, 02h ‘Select I/P, as analog
MOV Dx,PORTC MOV
OUT Port B, AL ‘input.
OUT DX,AL | | |
AL, 00h -Give start of conversion
MOV CX,OFFFFH | aaa
MOV
Port C, AL ; pulse to the ADC
OUT
UPI: ,
AL, 01h
LOOP UP1 MOV
Port C, AL
OUT
MOV AL,PHASED
MOV Dx,PORTC MOV AL, 00h

OUT DX,AL OUT Port C, AL

‘Check for EOC by
MOV CX,0FFFFH WAIT: IN AL, Port C
- reading port C upper and
RCR |
UP2:
JNC WAIT _ ‘rotating through carry.
IN AL, PortA ‘If EOC, read digital equivalent;in AL
“MOV AL,PHASEB HLT ; Stop.
MOV DX,PORTC
OUT DX.AL i: ——
Vref = <=

MOV CX,0FFFFH me it SV =
UP3: a St FP Nee |, Clock up
LOOP UP3 ©
JMP AGAIN: ; REPEATE OUTPUT
SEQUEN CE
ie
(525) Pay Pag | =O al
INT 03H = ee rs De.
END START Lae
Laces

: a—4 eA of ; a 0808 | Voltage

Q.2. (6) Draw and explain the block cinurarn of 825 OE GNDk—
1. A
Ans. Refer Q. 6. (a) of End Term 2016. ALEA ey ake—
| 8255
55 ; SV B Cc
Q.3. (a) Draw an interfacing diagram to interface an 8-bit analog to ee
digital
converter from 8255 to 8086 in IO mapped IO. Write a program to
take samples _ PB, |
of input analog signal at an interval of 2s, convert il into digital and save IORD
itat
memory location 900011.
Ans. Interfacing Analog to Digital Data Gee
(9 |
es a
° Example: Interfacing ADC 0808 with 8086 using 8255 ports. Use port A of 8255 5
for transferring digital data output of ADC to the CPU and port C for control signals. Interfacing 6808 with 8086
 16-2016 Sixth Semester, Microprocessor and Microcontroller
I.P. University-(B.Tech)-AB Publisher 2016-17
Q.3. (6) Draw and explain the block diagram of 8259A.
corresponds to the interrupt input with the same number. The IMR ey on ay
Ans. The 8259A is a programmable interrupt controller designed to work
With Inte|
IRR. Masking of higher priority input will not affect the interrupt request ines 0
microprocessor 8080 A, 8085, 8086, 8088. The 8259 A interru pt controller can (
1) Hand). lower priority. To unmask any interrupt the corresponding bit is set ‘0’. In ae
eight interrupt inputs. This is equivalent to providing eight interrupt pi NS on oe
register (ISR): The in service registers keeps tracks of which interrupt inpu
where he i
the
processor in place of one INTR/INT pin. (2) Vector an interrupt request an yW :
the memory map. However, all the eight interrupt are spaced at the intery currently being serviced. For each input that is currently being he
e ee
four or eight location. This eliminates the major drawback, 8085 interrup t;al in.
of Cithe, corresponding bit will be set in the in service register. Bach of these 3-reg ae
which as status reg. Priority Resolver: This logic block determines the priorities Oo ee
= oe
all interrupts are vectored to memory location on page OOH. (3) Resolve eig it o z
interrupt priorities in a variety of modes. (4) Mask each interrupt reque
t levels of the IRR. The highest priority is selected and strobed into the ee
an ee :
dually. (5) Read the status of pending interrupts, in service interrupts, an
St indiy). ISR during pulse. Cascade buffer/comparator: This function blocks hae
d maskeg s in the reg. The associ ated 3-I/O pins (CAS0 -CAS i ou a =
interrupts. (6) Be set up to accept either the level triggered or edge triggered the IDS of all 8259A’
is use = 5 S aa
ns
request. (7) Mine 8259 as can be cascade in a master slave confi guration
Interrupt when 8259A is used a master. Master and are inputs when 8259A
device we S ; ee
interrupt inputs. The 8259 Ais contained in a 28-element in line package
to handle 64 As a master, the 8259A sends the ID of the interrupting slave
sn addres
that require es cas0. The slave thus selected will send its pre-programmed
1

only a compatible with 8259. The main difference between the two is that the Ee
the data bus during the next one or two successive INTA- pulses.
can be used with Intel 8086/8088 processor. It also induces ad diti
onal feat
8259 A architecture of 8051. 6)
as level triggered mode, buffered mode and automatic end of i nter
ures Su ch. Q.4. (a) With a neat sketch, discuss the internal
rupt mode. is an 8-bi t mic roc ont rol ler. The major components -
ae ‘ne The 805 1 mic roc ont rol ler
Func tional Description: The 8259 A has eight interrupt req s. |
uest in puts, TR2 of 8051 microcontroller and their function
IRO. The
receives
8259 A uses its INT output to interrupt the 8085A via INTR
interrupt acknowledge pulses from the at its iiput. Vec
pin. The 82594 Intel 8051 Microarchitecture
tor address used by
the 8085 A to transfer control to the service subroutine of the int
err upting device, js
provided by the 8259 A on the data bus. The 8259A is a progra
m mable device that
must be initialized by command words sent.
t

8259 internal block diagram . ‘

>tay.

Sie -

; INTA INT ’ r-

DO-D7 <=>} Date bus |}<=————=+)| 4 T - ~_

bufier N Control logic :

:
> *

T
>

| |
E
Rise ee hea t
RD—>] Read/ N
WR—+ <— IRO
wrile = |-— A In-service Priority Interrupt |<-IR1
AD—>/| logic L register |<=>|resolver|<== request |:
(ISR} register |:
t>——>—_——_?. B . (IRR) |:
U <— IR7
Ss
CASO <—} Cascade
CAS1 <—| bufferf/ |< Interrupt mask register (IMR)
CAS2 <—| comparator
:
SP/EN————_t _ PSEN#
The descriptions of various blocks are, Data bus buffer: This 3- state, bidirectional. _ALE/PROG#
EAH#/VPP
8-bit buffer is used to interface the 8259A to the system data bus. Control words RST
and
status information are transferred through the data bus buffer. Read/Write & contro] |
logic: The function of this block is to accept OUTPUT commands from the CPU. It. i.
contains the initialization command word (ICW) register and operation command
word (OCW) register which store the various control formats for device operation. E
This function block also allows the status of 8159A to be transferred to the data bus. ,
_ Interrupt request register (IRR): IRR stores all the interrupt inputs that are requesting
service. Basically, it keeps track of which interrupt inputs are asking for service. If an
interrupt input is unmasked, and has an interrupt signal on it, then the corresponding
bit in the IRR will be set. Interrupt mask register (IMR): The IMR is used to disabl 7.
(Mask) or enable (Unmask) individual interrupt inputs. Each bit in this register”
 18-2016 Sixth Semester, Micri oprocessor and Micr
ocontroller
An 8051 microcontr
oller has the follow
1. ALU (Arithmetic ing 12 major components:
and Logie Unit) [.P. University-(B.Tech)+AB Publisher 2016-19
2-PC (Program Co
unter) |
Internal operations can be synchronized using clock circuits which produce clock
. Registers es. With each clock pulse, a particular function will be accomplished and hence
tm Ww

. Timers and counte hronization is achieved. There are two pins XTAL1 and XTAL2 which form an
rs , lator circuit which connect to a resonant network in the microcontroller. The circuit
. Internal RAM and
ROM has 4 additional pins .
naa

. Four general purpo

se parallel input/ou 1. EA: External enable
tput ports
Interrupt control logi
c with five sources of | | 2. ALE: Address latch enable
Soon

. Serial date communi interrupt

cation 3 PSEN: Program store enable and
. PSW (Program
10. Data Pointer
Status Word) 44. RST: Reset.
(DPTR) : Quartz crystal is used to generate periodic clock pulses.
11. Stack Pointer (SP)
| ‘ Internal RAM and ROM
12. Data and Address bus.
Now let us see the func sia | ROM: Acode of 4K memory is incorporated as on-chip ROM in 8051. The 8051 ROM
tions of each of these co non-volatile memory meaning that its contents cannot be altered and hence has a
1. tae mponents
All arithmetic and logical
functions are carried out dar range of data and program memory, i.e, they can address program memory as
Addition, subtraction by the ALU ‘as a 64K separate block of data memory.
with carry and multiplica
operations. tion come under ar : ithmetic : The 8051 microcontroller is composed of 128 bytes of internal RAM. This is
a atile memory since its contents will be lost if power is switched off. These 128
‘s of internal RAM are divided into 32 working registers which in turn constitute 4
ter banks (Bank 0-Bank 3) with each bank consisting of — (RO - R7). There
128 addressable bits in the internal RAM. , |
4

instruction residing in Memory and wh

en a command is encountered, it produc
instruction. This es that
way the PC increments automatically, holding 4 General
the address of the next 2 Purpose . 80 bytes
Area
3. Registers: Registers are usually known as data storage devices. 8051 30H + + ; \
microcontroller has 2 registers, namely Register A and Register B. RegisterA serves as 2FH| | ers 16 No. of Bits = 16x 8 = 128
an accumulator while Register B functions as a general purpose register. These registers
red: bytes Bit address OOH — 7FH
are used to store the output of mathematical and logical instructions. 20H = +
The operations of addition, subtraction, multiplication and division are carried out 1FH Register
_ Bank-3
by Register A. Register B is usually unused and comes into picture only when a 18H
multiplication and division functions are carried out by Register A. Register A also - 17H A
, | Ragister
involved in data transfers between the microcontroller and external memory. |
Xo] > 10H Sets
8051 microcontroller also has 7 Special Function Registers (SFRs). They are:
- er Register 32 bytes = 8 x 4 byes |
1. Serial Port Data Buffer (SBUF) 7 |
Bank-1
08H.
2. Timer/Counter Control (TCON) o7H E—-—— -RZ-_-_-_-
3. Timer/Counter Mode Control (TMOD) Register _
“Bank-0
———4—,- =
4: Serial Port Control (SCON) sie fee See se a a alae t

5. Power Control (PCON) —_= —

QoHo ae
6. Interrupt Priority(IP) ontroller
put/Output Ports: The 8051 microc
< se

. Site eral Purpose Parallel In a |

¢

7. Interrupt Enable Control (IE) a ee iev ed

Re. a a recta ports. These are: PORT PO: When there is no NT see
| io n am on g ra l ope rat ion s can be ach
4. Timers and Counters: Synchronizat r ng clo ck pul ses . During gent, °.this port acts as a general purpose es ee a dual role.
re sp on si bl e for ge ne ati
with the help of clock circuits which are th er eb y, as su ri ng sy nc hronization
——
-_mory, ti d address and
it functions as a multiplexe data : bus. a eee eis 5
j
ez -h clock pulse a particul operation will be carriedone out,
ar ration ‘provided with two pins a ¥ eo This port is used for various interfacing activities. Dia obey port
t: rmation of an oscillator, we are p | jae

among operations. For oc alae ting a resonant network in 8051 4 a

3 nl I/O port i.e. it does not perform dual functions.
XTALI and XTAL2 which are used Sor rcs a r
uit also consi ists of fou mor
e pins. They are, Ce +
1 4

microcont roller ice. In addition to this,

dev ci | | cL
Wei
<i
 END TERM EXAMINATION [MAY-2016]
SIXTH SEMESTER [B.TECH]
MICROPROCESSOR AND
MICROCONTROLLER [ETEE-310]
MLM. : 75
Note: Attempt any five questions including Q. No. 1 which is compulsory.
Q.1. Attempts all parts. (2.5x10 = 25)

answer in 41H. Q.1. (a) Explain [9/7 ALE pin of 8085 Microprocessor.
MOV A,RO Ans. IO/M': Consider we have an address to be processed. But how do the processors
SUBB A.R2 aaa know whether the address is for memory or I/O functions. For this purpose a status
3
: ‘ “4 signal called IO/M’ is used. This distinguishes whether the address is for memory or IO.
MOV 41H.A ;Move the answ er to the low- When this pin goes high, the address is for an I/O device. While the pin goes low, the
SUBB16_16- b | ae address is assigned for the memory.
Step 1 of the process ye of he result
MOV A,R1 ’
eet
ALEou
hia
(O): Address Latch Enable
CLR C | ALE is provided by the processor to latch the address into the 8282/8283 address
ov
— late h. It is an active high pulse during T1 of any bus cycle. ALE signal is never floated.
SUBB A,R3 ;Subtract the second
low-byte from the ac Q.1. (b) What are flag registers? Explain auxliaty carry and parity flag of
MOV 40H,A Move the answ cumulato r | ____ 8085 microprocessor.
er to the low-byte of th
e result a an Ans. Flag Registers: It consists of 5 flip flop which changes its status according to
;Step 2 of the process
MOV A,RO ‘the result stored in’an accumulator. It is also known as status registers. It is connected
;Move the high-byte into th to the ALU.
e accumulator :
SUBB A,R2 ;Subtract the second high
-byte from the accumulat _-_—C-- There are five flip-flops in the flag register are as follows:
MOV 41H,A e
;Move the answer to the low- 1. Sign(S) 2. Zero(z) 3. Auxiliary carry(AC)
byte of the result ,
i
;Return - answer now resides in = s4«. Parrity(P) 5. Carry(C) ee
R2, and R3.
RET ae - The bit position of the flip flop in flag register is:

: a ; | ; D, | Dg | Ds | Da | Ds | D2 | Di | Po
-_ ei ah Gaia R PAC pa be (ex (EY
- |
)
-.. Allofthe three flip flop set and reset according to the stored result in the accumulator.
! q 1. Auxiliary carry(AC)-If any carry goes from D3 to D4 in the output then it is set
otherwise it is reset.
a tarry in its final
2. Carry(C)-If the result stored in an accumulator generates
j output then it is set otherwise it is reset.
(c) Exp lai n how phy sic al add res s is gen era ted in 8086 microprocessor?
Bi Q.1.
are four 16-b it seg men t regi ster s that allo w the 8086 CPU to access
‘Ans. There
ory in an unu sua l way . Rat her th an con cat ena tin g the segment
| one megabyte of mem ed
ces sor s who se add res s space ex ceeded
| reg | ister with the a ddress regi ster , as in mos t pro
ore adding it
er siz e, the 808 6 shi fts the 16- bit se gm en t onl y fou r bits left bef
a heir regist a 20-bit external (or
set (1 6x se gm en t + off set ), the ref ore pro duc ing
| to the 16-bit off pair. As a result, each
~ ae
add res s fro m the 32- bit seg men t:o ffs et
sRa
~ effective or physical) pairs.
add res s can be ref err ed to by 2"* = 409 6 dif ferent segment:offset
external
000 0 Se gm en t, 16 bits, shifted 4 bits left
~~
: 9110 100 0 10 00 011 1
0100 1010 1001 Offset, 16 bits
0011

0001 1001 Address, 20 bits

0110 1011 1101
 scheme u 84 conside =
a red co .
at a fixed o fteer aes ee . — d and ¢
at m
~ 15 bytes(suofe Blige IN itsall 9 pr ae LP. University—(B.Tech)-AB Publisher 2016-23

“tL. (da) E Xplain

cont,ent was “nt, avoicin
idi g the neediy fe Q.1. (e) Why IC8259 is needed? Explain.
Ans. The Intel 8259 is a Programmable Interrupt Controller (PIC) designed for the
(PC i ic The Bit Set/Reescat or Wor d de Sist
Smar +o of 8255
er t Intel 8085 and Intel 8086 microprocessors. The initial part was 8259, a later Asufhix
1° a 7) can be se Wena (BSR) mo a
8259
version was upward compatible and usable with the 8086 or 8088 processor. The
to the host
oth er Ports arein ind epe nd oy suitably | ci PoreC combines multiple interrupt input sources into a single interrupt output
VO bas nd the one or
microprocessor, extending the interrupt levels available in a system beyo
a d Selection ena co
| : R mod
0] Word
d oe controller for the
. CS not affe two levels found on the processor chip. The 8259A was the interrupt
= i ISA bus in the original IBM PC and IBM PC AT.
Q.1. (f) Explain the function of bus interface unit.
D,

; . ° ms D, D aND 7 are:
A ety 2 D, fe Ans. The functions performed by the Bus interface unit
| X X B, ¢ The BIU is responsible for the external bus operations.
B B as I/O of data for
1 B, ¢ It performs fetching, reading, writing for memory 4s well
| |
peripheral devices.
on of the instruction
lways 0 for B ¢ The BIU also performs address generation and the populati
| OR SR mod
ode Don't Care 7
queue.
zero flag after execution
Port C bit select Q.1. (g) What will be the contents of carry flag and
8 255 Contro} Register register C contains 27H.
format fo : of instruction CMP C if register Acontains 70H and
8255 BSR mode | r BSR Mode of Accumulator with the
Ans. CMP C; this instruction will compare the conient
VE = raction of A-C =A
: D 7 bit is always 0 for content of C register by performing 2’s complement subt
* Bits D,,D | BSR mode. | As given A= 70H and C= 27H
H5 and D, are don
© Bits D 3» Vo and D, are used to
't car e bits,
eS seen - A>C; so that no CF and ZF will be generated
of Port:oe (
2 used to set/reset the3 selected pinpin se
select the CF=0 & ZF=0 |
e Bitit. Dy is
)
_ Q.1. (h) Write operating modes of 8253.
Selection of Port C pin is determin The D3, D2, and D1 bits of the Control Word set the
ed as follows: Ans. Operation Modes:
; for modes 2 and 3, the D3 bit is
operating mode of the timer. There are 6 modes in total
B3 B2 Bi | Bit/pin of port Cc selae a ignored, so the mis sin g mod es 6 and 7 are alia ses for mod es 2 and 3. Notice that, for
E mus t be set to HIG H to enable counting. For mode 5, the
0 0 modes 0, 2, 3 and 4, GAT
star ts the coun t. For deta ils on each mod e, see the reference links.

5
- rising edge of GAT E
0
os
0 Mode 0 (000): Interrupt on Terminal Count
0. 1 Mode 0 is used for the generation of accurate time
m the init
delay under software control.
ial COU NT value loaded into
In
it,
0 1 ‘this mode, the cou nte r will star t cou nti ng
down to 0. Counting rate is equal to the input cloc
fro
k frequency.
1 0 Mode 1 (001): Programmable One Shot as
d as Mon ost abl e Mul tiv ibr ator. GATE input is used
1 In this mod e 825 3 can be use
1 1 trigger input.

1 1 Mode 2 (X10): Rate Generator

e, thé dev ice acts as a div ide -by -n cou nte r, which is co mm only used to
| In this mod
generate a real-time clock interrupt.
Mode (3 (X11): Square Wave Generator
| do Nita Ve Dy I Do ie
. D3.
de 2. Ho we ve r, the dur ati on of the high and low clock
This mode is similar to mo
PC, from mode 2.
- PCu GBmode} PB pulses of the output will be different |
robe
Mode 4 (100): Software Triggered St
a
| tae
: 7
: ae

remain high until the

;
* - nA)
,
; : “hy (a
"es
UN T is loa ded , the out put wil l
After Control Word and CO
a” ae

se for 1 clock cycle (a

: ae 9 | ae
* *

pul
q

a low
:

e co un te r wil l the n ge ne ra te
counter reaches zero. Th
4 v

wil l be come high again.

;

er tha t the ou tp ut
PortGy
im
) — aft
Pgo
& ode Port str obe
SF

Alwa ys 1 for
1

Group Amed ® Mode 5 (101): Hardware Triggere

d Strobe
me

ortA l

un ti ng pr oc es s is triggered by the
th e co
VO mode This mode is similar to mode 4,
Ho we ve r,
GATE input.

fo r 1/ 0. mode
— g955 Contro |Wo rd
 —_

I.P. University-(B.Tech}AB Publisher 2016-25

In, | Label Mnemonic | Hex code Comment

| 4200 MVI C,00 OE Initialize C as 0
—~y| 4201 00
4 “| — 4202 LXI H,4100 21 Load HL pair with the address
of the data whose occurrence is
5 to be found
74 | 4203 00.
ion | 4204 41
| 4205 MOVA,M 7E Copy the data to the
oe Accumulator
, | 4206 MVI E,01 1E Initialize E with 0
7aa| 4207 mi 01
sar | 4208 LOOP SUB E 93 [A] < [A] + [E]
| 4209 . INR E 1C Increment register E
| 420A INR E 1C Increment register E
| 420B INRC . 0C Increment register C
~420C CPI ,00 FE Compare accumulator content
i” | with 0
ugh | 420D 00
O11. G) Fxsl er second is more realistic | | 420E JNZ LOOP C2 Jump on non-zero to the label
: ee xplain the difference be MEANS) | ; *. LOOP .
8051 microcontroller, | | | ee Ove and Move instruction of | 420F
Ans. The MOYKX i) ie ert pee ee | 4210 42aT |
at, : VX instruction transfers data between the accumulator and external | 4211 MOVA,C 79 Copy content of registerC to
3 Riera . External memory may be addressed via 16-bits in the DPTR registeaal | | accumulator
via 8-bits in the RO or R1 registers. When usin ssi
Sar st raeties . g 8-bit addressin Port? in- | 4212 STA 45003 32 i i 4500
Store the square root in
the high-order byte of the address. | eae Siet oe ae oe ‘| 4218 00 :
MOVC @Ri,A | aR | 4214 45
MOVC: The MOVC instruction moves a byte from the code or program memory to : Sai HEE 8 Brogan oun
the accumulator — aie ts mach psites ee He ' - © Observation
MOVCA, @A+DPTR_ Vile es eae ee =P inputat 4100: 31y |
Q.2. (a) Write a program to find the square root of anumber. Also explain it — Output at 4900 Oy are eauare xe
ee ‘opal ap 4 Oe cae Python code
with the help of ace ae flow chart.
Po suitable on re, | Flow chart x= 16,
Ans. Algorithm: | ans = 0
HL pai r wit h the add res s of the num ber whose squ are root is tobe while ans* ans < = x:
(1) Load the | ans = ans + 1
3 | print ans
found. Simulation

C o p y th e n u m b e r to ac cu mu lator. e ans X ans“ ans

_ (2) |
w i t h O . | 0 —~> Oyes
(3) Initialize E ‘ zie
co nt en t of E fr om accumulator. s+ 1
= ans
an
oo yes
(4) Subtract 3 9 yes
(5) Increment registerEby2: ee i 4 | 16 yes

(6) Increment content cuen si eee ee G25 no)

‘Compare accumulator content Wy a laago tostene om

ip eee
{Print ans/
ee tent is not zero then go to step ce _ nals ed
t in to
:

th
’

e me mo ry .
t o re t h e s q uar e roo
(9) S
n at e t he p rog r am. .
(10) Term i
 26-2016 Sixth Semester, Microprocessor and Microc
ontroller
Q.2. (b) Write a program to generate Fibonacci 1.P. University—(B.Tech)-AB Publisher 2016-27
series.
Ans. Refer Q.2. (a) First Term 2016.
Q.3. (a) Draw and explain hardware Interrupt | Vector address
interrupt structure 8085 microp
:
RST 7.5 003Cy
Ans. Interrupt Structure in 8085. RST 6.5 0034,,
* Interrupt is signals send by an external RST 5.5 002C,
devi ce to the processo
;

processor to perform a particular task or r, to requ, TRAP 0024,,_

work.
* Mainly in the microprocessor based
system the interrupts ar TRAP:
transfer between the peripheral and e used fo
the microprocessor, ¢ This interrupt is a non-maskable interrupt. It is unaffected by any mask or
¢ The processor will check the interr :
interrupt enable.
upts always at the 2nd T- state
cycle. of last m;
¢ TRAP has the highest priority and vectored interrupt.
3 *If there is any interru pt it ¢ TRAP interrupt is edge and level triggered. This means that the TRAP must go
accept the interrupt and send
signal to the peripheral. the INTA oll |
: high and remain high until it is acknowledged.
me . aa
¢ The vectored address of partic
ular interrupt is stored in progra
a ¢ In sudden power failure, it executes a ISR and send the data from main memory
* The processor executes an inte m counter, to backup memory. | ; |
rrupt service routine (ISR) addr
counter. essed in pr ( ° te signal, which overrides the TRAP, is HOLD signal. (i.e., If the aaa
* It returned to main program by RET | = 5, receives HOLD anid TRAP at the same time then HOLD is recognized first and then
instruction. ' TRAP is recognized). | ao
Types of Interrupts: It supports
two types of interrupts. | -¢ There are two ways to clear TRAP interrupt.
¢ Hardware | ° Software 1. By resetting microprocessor (External signal) |
Software interrupts:
; 2. By giving a high TRAP ACKNOWLEDGE (Internal signal)
¢ The software interrupts are program ins
tructions. These instructions arei t RST 7.5: The RST 7.5 interrupt is a maskable interrupt.
at desired locations in a program. : : Spee: *
: ¢ It has the sec ond hig hes t prio rity .
* The 8085 has eight software interrupts fro hig h and no nec d to mai nta in high state unti
m RST 0 to RST 7. The vector ad_ ° It is edge sens itiv e. ie. Inp ut goes to
for these interrupts can be calculated as follows.
:. it recognized.
* Interrupt number * 8 = vector address di bled d by,by. e | :
i errupt. It isis disa
kable int
* For RST 5,5 * 8 = 40 =28H_ ation of interrup
| : | | : ee 2. System or processor reset, 3. After reorganiz
* Vector address for interrupt RST 5 is 0028H | ; e Enabled by EI instruction.

lata anata, a te ia aaa

es ieee 4 : a RST 5.5 both are level triggered. . i.e. Input goes to high and stay
7 ° the | aoe
Interrupt | Vector address | 4 high until it recognized. Sere
a e ble interrupt. itis : | reset; e 3. After reorgamzization 0
ae 1 o | ea snstruction; 2. System or processor
RST 0008, . DI,
| a interrupt.
st oe «Enabled by EI peer Ori RST 5.5 has the fourth priority.
BOE oNreH ° The RST 6.5 has the third priority whereas -o0 2
~RST4 0020,, INTR: oS
RST5 0028, - 7 a e INTR isa maskable interrupt. It is a a -3 After reorganization of —
: RST 6 x 0030, : = -_- : | 1. DI, SIM instruction;
ion; 2. System or proc s
Ra - 0038 ea interrupt.
:
| i ; Te : 4 ¢ Enabled by EI interrupt.
ee ee After recel ving INTA (active low) signal, it has to SUPPLY
Hardware interrupts: | , a
=: e Non- vectored in :
¢ An external device initiates the hardware interrupts and placing an appropl the address of ISR.
signal at the interrupt pin of the processor. | 4 ri ty . ; |
e It ha s lo we st pr io
to hi gh an d it is ne cessary to
* If the interrupt is accepted:then the processor executes an interrupt service "i r | it iv e in te rr up ts . 1. e. In put goes
e It is a level se ns
The 8085 has five hardware interrupts 4 q n hi gh st at e un ti l it recognized.
mainta i
(1) TRAP (2) RST 7.5 (3) RST 6.5 (4) RST 5.5 (5) INTR ey
 MP, University—(B.Tech)-AB Publisher 2016-29
Interrupt type Trigger Priority | Maskable| Vector address
TRAP Edge and level | 1st No 0024H
RST 7.5 Edge gad Yes 003CH
ackn RST 6.5 Level gt Yes 0034H
RST 5.5 Level | AEE Yes 002CH
INTR Level bth Yes -
-Prioity Edge/Level

j. eeare :
2 tA RST Vector location
: ’ -——dAnd) 003CH
75 CLR Q} [Mask
RST 7.5 interrupt recon tse fan] 3
ears RST L-
-0038h
land) 0034h
6.9 Mask i
er, And : 0030h
.
4 > RST and) 002Ch
<=
SOD|SDE MSE |M7.5|M6.5 M5.5 oo |
Mask 0028h
:
Senal output dataqH! 0024h
© —>s-__
4

{TRAP
.

Serial data enable -. —*®RST 5.5 mask si ‘

= Available
0020h

1 = mixed
lf, SDE = 1, bit D7<— _————> RST 65 mask -&
Don't
| pi Soe ff /Y 001
is send to SOD line Care ———> RST 7.5 mask | as
Reset OR—p Interrupt Get RST 0010h
8h
if SDE = 0, bit D, is Any oor enable FF Code o008h
ignored
Sica > Mask set enable© 9 Sls] NTR |= nierunt — -Fanad
If, MSE = 0, Do. D,
and D, are ignored if. — | 3
HW 0000h -
MSE. 1, mask is set. _Q.3. (6) Explain the difference between 8253 and 8254 IC. 5
——> Reset RST 7.5 (5)
ffR75= 1:RST 7. : 3/54 will count out the delay and interrup t tthe
he CPU
CP when it has completed
is not allowed.
its coke ae easy to see that the software overhead is minimum and that multiple
lfR 7.5=0: RST 7- . bo
isallowed. delays can be easily be maintained by assignment of priceaty levels.
~~~
Fig. Format of 8-bit data to be loaded e The 8253/54 includes three identical 16 bit counters that can op
in accumulator in accumulator
before ex ecuting sim i nstruction independently. -
e 16-bit count is loaded in its register and, on command, it begins to decreme
il it reaches 0. | ae
* When RIM instruction is execute “ae
dan 8-bit data is loaded in accumulator, whi
ch 4 ae the end of the count, it generates a pulse that can be used to interrup
can be interpreted as shown in fig. |
CPU. | ae: 7
in binary or BCD. |
j r in
unter can count eithe | oo,
| '
is decrementing
SID | 17.5 | 16.5 : ag aaa
eIna . a count can be read by the CPU while the counter
15.5 IE |M7.5|M6.5|M 5.5
-

j
.
oO ( )
ce

| Mask status of)

:

cater cd
: q
sim

Serial Input Data kr. 4 Se

tae—"RST5.5
©
x sf 8254 |
ae eahise
[esto ral Es Mask.s
on. a| 8253
oe Se
{ Interrupt pending 1. me frequency
Operating Q- 10 MHz.
Operating frequency 0-2.6 MHz.
|
Pending

? RST 6.5 .
status of RST 7.5 | » oe
‘| = 5.
2;
i re N “MOS technology. 2. Uses H-MOS an
Interrupt Pending

; cf : : a
/

. - O +s Read-Back co ae
pena +—— Interrupt 1 = interrupts areenab- | d not available.| 3.
.

. Slats OF RST.68 oo _ Reads and writes of the same

e 'nterrupt is not

Enable Flag [9 = interrupts are disab a 3. e a

Read s eand writs
e es of the same 4
Interrupt pending 4.
a can be interleaved.
| status of RST5.5 * counter can not be interleave
d.
 30-201 6 SiIXxth Semester, Microprocessor an
d Microcontroller
. Q.4. (a) With the hel p of neat
diirra
aggram, explai i
I.P. University-(B.Tech)}AB Pubiisher 2016-31
microprocessor alongwith func 8086
tion of each biodl advent
Ans. The 8086 Microprocessor cee mn nstruction byte. Fetching the next instruction while the current instruction executes
- Internal Architecture (7.5)
Th led pipelining.
e Intel 8086 isa a 16-bitSea microp
rocessor intended to be used ient Registers
as the CPU ;
‘he BIU contains four 16-bit segment registers. They are: the extra segment (ES)
. ,
.

and most of its instruction

|
1 a.

e S are desi i 1Rchit bi: “TS, Ser, the code segment (CS) registers, the data segment (DS) registers, and the
16-bit databus and 20-bit address bus. wie e
ee pinary words. It has . segment (SS) registers. These segment registers are used to hold the upper 16
if the starting address for each of the segments. The part of a segment starting
iss stored in a segment register is often called the segment base.
in
, Code Segment (CS): The CS register is used for addressing a memory location
ode Segment of the memory, where the executable program is stored.
are
_ |, Data Segment (DS): The DS contains most data used by program. Data
ter that
sed in the Data Segment by an offset address or the content of other regis
the offset address. -
k Seg men t (SS): SS defi ned a sect ion of mem ory to stor e addresses and data
}. Stac
- tasubprogram executes.
BNO Ee ee Seg men t (ES) : ES is addi tion al data seg men t that is used by some of the
1 Ser | a3 Extra
?2 | ‘% to hold the extra destination data.
|

gee
. |
1
tream :
3
Queue 8
LS eee ee i ee _ |Code
1
! Data
1
Stack
~ date er eel eek eee one. i o> ee es Sew Sew eae Yeas Samp um sem pee iomn Yau tons oe

j
l EU _| Extra
J .
I ‘ >: Ee , -

j
— - segment registers
j
!
j;

i Ari ithmatic
I
logic unit
i
!
I
j
i
i

8086 Internal Block Diagram

The 8086 CPU is divided into two independent functional parts, the bus interface _ “s

unit or BIU, and the execution unit or EU.

The Bus Interface Unit —__ Nie ee ees a “u ction Pointer (IP)
e
re gi st er , be low e
The BIU handles all data and addresses on the buses for the execution unit such as In the BI U, th e ne xt
0
it sends out.addresses, fetches instructions from memov'y, reads data from ports and “Auction pointer (IP) holds the 16-bit address
memory as well as writes data to ports and memory. In BIU there are so many functional Execution Unit io ns or da ta from,
unit (EU) tells the BIU | wh ere to fetc h in st ru ct
groups or parts these are as follows: : e
1 ei"ne ex executi on ns.
| s, and executes instructio
Instruction Queue ; - }des instruction n un it are control circul try or system, instruction
ec ut io
To increase the execution speed, BIU fetches as many as six instruction bytes rtts of th e ex
_ Bfhe functional paar (ALU|).
logic unit
ahead to time from memory. The pre fetched instruction hytes are held for the EU ina . >der, and Arithmetic va ri o us in te rn al op eratio ns. A | d e c o d e r in the EU
pe rf or m external
first in first out group of registers called a instruction queue. When the KU is ready for to
rc ui tr y in te rn
r n a l or
Control ci om me m o r y to ge ne rate differen t e
This is fetched fr
its next instruction, it simply reads the instruction from this instruction queue. 4 slates instructions
back the
much faster than sending out an address to the system memory and to send * +
*
4

of

i Md
, | . +
~
_

a
 Sixth Semester, Micr
oprocessor and Mic
rocontroller
control signals that required perf 4
orming the o ion,
-

automatically by CP
U after m
divided into two catego
ries:
1. Conditional Flags Vn 0 store 16-bit data. The valid register
Conditional f] _ 8L, BH and BL, CH and CL and DH pairs are AH and
ag8 represent brresu
esnit of
lt of last arithmetic or logical] _ BX, CX, and Dx respectively, an d DL. These register pairs is referred
to the AX
* Carry Flag (CF
: 61cal instructions— a 1. AX Regist : er ‘
: For 16-bit WK 5
perations, AX is called the accumulato
dy stores operands for arithmetic operat r register that
ions.
from lower nibble (i.e. Do — D3 2. BX Register: This register is
: ALU generates a a ca mainly used as a base register. It ho
given by D3 bit to D4 is AF aca ise r
Ca rr at
y/ba MoaSe loc Locati
ation o fa memory ry re region wiith lds the starting
i a data segment.
*

teaoe ee R thin
by the processor to perform Binary e AF wee 1S Set i.e, Can _ 3. CX Register:
to aoe tee | pee w2e Used 7 halsto It is defined a8 a counter. It is primarily
used in loop instruction to
re loop counter.
4. DX Register: DX register is used to
contain I/O port address for I/O instruction.
Stack Pointer Register
}

ae §=6 The stack pointer (SP) register contai

zero else it is reset. It is set to one; if the result ofa rit it hmetic or logica
ns the 16-bit offset from the start of the
i l operatDens ion
ta seg =©8™ment to the memory location where a word was most recently stored on the stack.
| _ The memory location where a word was most rec
rmat the sign of number is indica ently stored is called the top of stack.
ted) Other Pointer and Index Registers
SE
signed numbers are added or subtracted, 4 The EU also contains a 16-bit source index (SI) register, base pointe
r (BP) registers,
land Destination Index (DI) registers.
These three registers can be mainly use
Paci | 4 temporary d for
storage of 16-bit data just like'a general purpose registers.
4 Q.4. (6) Write a program to find the factorial of a given num
ber using yr
“umicroprocessor.

1. Trap Flag (TP): It is used for Ans. MOVSI, 8000

instruction of a program at a ti single step control. It allows user
me for debugging. When trap flag to execute on oy Bxisu
run in single step mode. is set, programcanh 4 MOVAX,01
_ 2. Interrupt Flag (IF): It is -—¥ LABEL 1: MUL BX
an interrupt enable/disable flag
prohibit the interrupti on of a program. If it is set, the mask , i.e. used to alloy DEC BX
and if it is reset, the interrupt is disabl able interrupt is enable JNZ LABLE 1
ed.
3. Direction Flag (DF): It is £ MOV D1. 8050
used
accessed from higher memory address toin string operation. If it is set, string bytesan
lower memory address. When it is reset th ;
string bytes are accessed from lower memory
MOV [Dl], AX -
adress to higher aemary address. 4 |
.
ae a )Wiiat aveliie difeseacs litw
D,. cen R165 aad 8086 microproc osear
8086 Flag Register format Do Re iteaee ? | | :
| 7 Pag ie AE qe ESE | Zeslice
. 3 “|-A.R Atos |r |e |
ae q
Ans. e
8085 microprocessor vs 8086 microprocessor describes difference between
ee :
| Sav
CF: Contains carry our of MSB of result
— 8085 and 8086 microprocessor aetypes: |
E kosb micsnneocemar 8086 microprocessor
0-Unspecified PF: Indicates if result has even parity
| — hit manopmmeessor It is 16 bit microprocessor
AF; Contains carry out of bit 3 ib AL
| ee ~ = line
ZF: Indicates of result equals zero It has 20 bit address line
_ {It has 16 bit a
SF: Indicates if results is negative || It has 8 bit data bus It has 16 bit data bus
OF: Indicates that an coverflow occured in result 4 | Clock speed of 8085 microprocessor Clock speed of 8086 microprocessor vary
IF; Enables/Disables interputs . | is 3 MHz natneat 5. 8 and 10 MHz for different
| a versions.
DF: Controls pointer updates during string operations t i bane flaca It has 9 flags.
TF: Provides single-step capability for debugging i : as = :
a
 34-2016 Sixth Semester, Microprocessor and Microcontroller
L.P. University-(B.Tech)}-AB Publisher 2016-35
4 does not support pipelining. It supports pipelining, 4
It operates on clock cycle with 50% It operates on clock cycle wi > Interfacing of 8253/54 with 8086
duty cycle. th 33% §) With 8-Bit Address
8085 microprocessor does not 8086 microprocessor Support
Support memory segmentation. segmentation. : Memo | CLK,
It has less number of transistors
Do Yo —L- GATE,
It has more number of transisto D; D, ——— OUT,
rs compa
compare to 8086 microprocessor. to 8085 microprocessor. It is a
bout 29)
It is about 6500 in size. in size. % a * CLK,
It is accumulator based processor. ae GATE,
It is general purpose register | MIS -dep H—— OuT;
b age
processor. se 1OR
It has no minimum or maximum hy “he CLK,
It has minimum and maximum modes
\ . . .

mode. —
We ee WR GATE,
a 7 8253/54 [;— OUT,
In 8085, only one processor is used. In 8086, more than one processor is iw
Additional external processor can Ayn '
alsoh Agauee
employed. | a
In this microprocessor type, only 64 In this microprocessor type, 1MB memo As—— cs
KB memory is used. Ag
is used. — Ay
Q.5. (6) Explain the interfacing of 8254 wit
h 8086 with the help ofa
diagram. Fig. 4. Interfacing of 8253/54 with 8-bit address
, .

4 \% ]

a faite ha fd :
Ans. To generate a square wave of 1KHz fr equency We know that, 8253/54 has two address os e
on OUT 1 pin 0f8253/54. Asal ‘byte of demultiplexed data bus IBA.
CLK1 frequency is 1MHz and address for con trol reg ,
ister = OBH, counter 1 = 09Ha aci ed fo hos dac e line s of 825 3/5 4. The 825 3/54 IC decodes A,
counter 2 = OAH. Bek cal OE cad tae nade
to sel ect one of its por ts or con tro l reg ist er.
a : pee oo )
Sol.: To get square wave mode 3 is selected count should be can be use d to gen era te chi p sel ect sig nal . Fig . sho ws the
a address lines (A,-A4 )

1MHz
of 8253/54 with 8086. _
1KHz eee _. Address Map:
Address lines Address
Control word: } |- ports/Control

D, D, ‘D,; D, D, D, D, Do ae Pert A, |Ag | As | Aa | As | Ao | Ar | Ac

_| SG | SC, | RW, | Rw,| M, | M, | | 0. 0 0 0 0H
M, | BCD =77H) Counter 0 0 | 0 0 0 0
ADS Ace 4 1 P21 1 1 | 0 | G15 = FG 0 0 1 0 02H
Ki
Counter 1
Source program 4 QO: 120: 0 0 | 0 1 0 0
-Counter 2
MeV AL, 77H | 0 1 1--|-0 06H
Control Register-C 0 0.| 0 0
OUT 0OBH, AL ; Loadscontrol word (77H) in
| ae ; the control register. With 16-Bit Address .
:
wi th
i 16 bi
-b it ad dr es s. Here RD and :
§ 86
80
MOVAL, 00H ; loads lower byte (00) of the count he i n acging of 8253/54 with
rfacin ith
‘Figg. sh Ww
is lo w, in di ca ti ng VO bus ¢ Vy cle. To ge
gnal
LV ar ete ne: M/IO si
OUT 09H, AL ee | WER sisi gn oa : e
. mal ining addr es s li ne s (A , —A ,; ) ar e us ed to decode th e address
absolute address, all re |
MOVAL, 10 ; Loadshigherbyte (10)of the count for 8253/54. a
OUT 09H, AL |
 36-2016 Sixth Semester, Microprocessor and Microcontroller
|

| L.P. University-(B.Tech)—AB Publisher 2016-37

| Do Do CLK, |
D D GATE ' a
: 0
f OUT, |
Ay Ag
A A CLK
Transmit
2
ie 2 1 G ATE,1 D7-D,
Data bus bonsai buffer + -& TX
; buffer ae
( | TTL (P-S) !
RO: RD OUT
1OR '
Ay =: | ;
WR TOW wis CLK, ‘
8253/54 GATE, | Reset ——» |
Aa OUT, | s CLIC= Ft adhere Rx )
—»> TXRDY
bree > XE
A. : .a RD
GD. —>< control +> Sn >I——— TXC
Az
WR—><d logic a
As Ten ae £
A, i
7
CS Oo
a
As
DsR —>< g Recieve
2 CS |
A, 0 4 DIR + Modem EX buffer i4——- rxp
q CTS —>s «control A-_A|— (S-P)
Ay | tists 4 RTS + VV
Ax2 4
Ay 3 | | | : a =
As4
| Age | | ——
4 .
; .
3 _ ss LL» RXRDY
a |! Recieve i, RXC
af
Fig. Interfacing 8253/54 with 16-bitne
) 7 control |e» sYNDET/BD
address
Note : When 16-bit address is use dit is necessary
ees
to access 8253/8254. eae to use indirect add
ressing mode_ ;;
us
:
Address Map: 7 -. Block diagram of the 8251 USART (Universal Synchrono
| a Asynchronous Receiver Transmitter) =
CAE S | : -_—
S| | Mea tional
hae configuration isi programmed by software . Operation between
7
noe sees line | Address} the ae a epi executed by program control. Table. shows the operation between
Register Alb Al4 413 AyQ qq
; 3 A4l | 7 .
the device.
AyQ Ag Ag “7, 4g AG Ag AQ. Ay ol AQ § ee ee Table 1: Operation between a CPU and 8251
CounterO] 0 0 0 0 0 0 9 | ==
0 0 g Os 020502120 0: on TS Tee
CS |C/D|RD| WR
Countert 7 0.0 DO 0 (0.0 0 000 0 oe
| i
i-| x | x | x | Data Bus 3-State
Counter2 | 0 0 0 0 9 | - Annall +— Data Bus 3-State
Dr) 0.07" 20: 40-49 . 0 | ley 0ne 30 0004H) OS ice hedon =o
peo 4 Status >CPU
| Control 00-0 DD OSD 020 0 0 0 0 ee ee nee
Register |
0 | 1-| 1 | 0 | Control Word <CPU
c | | 0 07:10 1 Data > CPU
Q.6. (a) Explain architecture of 8251. USART with the help of neat diagram, | Orton to Data < CPU
PS ari

Ans. The 8251 is a USART (Universal Synchronous | ;

Asynchronous Receiver
Transmitter) for serial data communication. As a peripheral dev ‘Control Words
ice of a microcomputer o ty pe s of co nt ro l wor d. 3
, There ar e tw
system, the 8251 receives parallel data from the CPU and tra of function)
nsmits serial data after in st ru ct io n (s et ti ng
conversion. This device also receiyes serial data from the outside and transm 1. Mode ‘ aii) 3
data to the CPU after conversion.
its parallel nd (setting of operat io n o e
on of the
| 4 st ru ct io n 1s used fo r se tt in g th e fu nc ti
stru
Inct ct io n: Mo de in al re set or external
te
a

Mode instru ion will be in “wa it. for wri te”

ite” at eit
i her 1n
int ern
2
8251.
 38-2016 Sixth Semester, Microprocessor and Microcontroller
I.P. University-(B.Tech)}—AB Publisher 2016-39
reset. That is, the writing g of a control w ord after ‘ resetting
; will be recognized ag a “mod :
instruction.” DO; By De By a De 1D,
Items set by mode instruction are as follows: : ae scs |—ESD| EP |PEN| &| & 0 0

¢ Synchronous/asynchronous mode a ne] Charactor length

| 3 t 7p -
* Stop bit length (asynchronous . mode) | { ‘ —> 0 0 1 1
4 j . | Gbits | 7 bits | 8 bits
5bits
* Character length ~ | : |

| ae Pari
* Baud rate factor (asynchronous mode) | 4 s ~ 4 ak. 1
a
| x.)
e Internal/external synchronization (synchronous mode)
: :
a a rBce 2 : ;
. Odd Even
2
©
<7
a Disable | parity |Disable | parity
Number of synchronous characters (Synchronous mode)
The bit configurat ion of 4 .
1s shown in Figures. In the case 9 ZS ' | she ahs Synchronous mode
Synchronous mode, it is ie adetee |1
© one-or two byte syne characters. If es
sym xe . —> 0
characters were wri eae = oe
constitutes partaf itten eis: be set because the writing of sync. charaalil | : Internal External
iy i. synchronization | synchronization
= 3
L De | Ds D, esi
D. D D D 3
aa Number of synchronous charactors
S,| s, | Ep] PEN Ean B, a |
0 1 ;)
: fail
a ?
a !
sao Baud rate facotor
|
ia 2 charactor |1 charactor
= of }— Sef Oz 7 |
os ? 0 . Olena 4 a Bit Configuration of Mode Instruction (Synchronous)
syne | 1x 16x] 64~ 4 (2) Command

an d is use d for set tin g the ope rat ion of the 825 1. It is possible ‘to write a
2 e Charactor length 4 -- Comm and sync. characters.
an d whe nev er nec ess ary afte r wri tin g a mod e ins tru cti on
4 comm
oe as eaapeat 2 e 4 |
>| 0 0 1 ; |_ Items to be set by command are as follows: —
S bits| 6 bits} 7 bits]. 8 bits 4 -e Transmit Enable/Disable
e Receive Enable/Disable is
Parity check
= : | * DTR, RTS Output of data.

: parity | e Sending to break characters

oe step ent | e Internal resetting e

+ T 0 0 1 : | ¢ Hunt mode (synchronous mode).

(5)
Inhabit} 1 bit 11.5 bits! 2 bits Q.6. (b) Explain input and output modes of operation of 8279 in detail.
Bit C oe Ans. 8279 Pr og ra mm ab le Ke yb oa rd /d is pl ay interface
: Configuration of Mode Instruction (Asynchronous) | ac e a ma tr ix ke yb oa rd an d a mu lt ip le xed
This is a hardware approach to interf
try ora left entry.
:
© 6

di sp la y ca n be se t as ar ig ht en
i display. The
7 ~

40-2016 Sixth Semester, Microprocessor and Microcontroller Te ch )- AB Pu bl is he r 2016-41

LP. University -( B.
ro ws of a ma tr ix ke yb oa rd an d dig it drivers of
mx _Reset DB,-DB, These 16 lines can be connected to

Ve ie multiplexed display.
MPU INBTERFACE SECTION
This section has 8 bidire
es for in te rf ac in g in
ct
cl
io
ud
na
in
l
g
lin
buf
es.
fer
DB
ad
,
dr
-
es
DB . 1
s lines Ap.
in te rr up t request line(IRQ).

lea +— I/Ocontrol 6 lin

- sig nal s are in te rp re te d as con tro l word or status.
When A, is hi gh
data.
When A, is low - signal is interpreted as
wh en ev er dat a is re ad y to be lo ad ed into MPU.
IRQ goes high h 8255 in IO
g of 8 bit DAC with 8086 throug
Q.7. (a) Explain the interfacin ra te sq ua re wa ve . (7.5)
e a prog ra m to ge ne
internal data bus 8)
mapped I0 technique. Also writ
xDisplay ieee . es,
8x8
1 ;3 Ans. In te rf ac in g of
The digital to analog converters
DA C wi th 80 86
convert
through 8255
bi na ry nu mb er s in to th ei r an alog equivalent
conversion.
Di *| Control and — chniques are em pl oy ed for di gi ta l to an al og
address sy
timing FIFO/sensor = Keyboard — voltages or currents. Several te
registers splay >) a and
registers , RAM |
control (i) Weighted resistor network
, ig a : (ii) R-2R ladder network
[ yee i a
r
(iii) Current output D/A converte
~
Timing

a
motor speed
Scan
ga in s,
contr | "|
and we gi ta ll y co nt ro ll ed
Display le
areas like di
The DAC find applications in vo lt me te rs , pa ne l me te rs , etc. D/A
counter _ Return mm ab le ga in am plifiers, digital
cont ro l, pr og ra
si de s th os e wh er e th ey are used with a
ications be
converter have many appl er for ex am pl e a 14 -o r1 6- bi t D/A converter
sk audio play
Ta | 4 microcomputer. In a compact di di sk by a la se r to an an al og audio signal.
Out A,-A,, out B,-B, BD SL-SL,
us ed to co nv er t th e bi na ry da ta read off the nv ert stored
CNTUSTB is ai n a D/ A co nv er te r to co
RL-RL. in te gr ated circuits cont
8279 Block Diagram RG S ha Most sp ee ch sy nt he si ze r
da ta wo rd s in to an al og au dio signals.
binary
KEYBOARD SECTION ‘Characteristics l input. It
Sa ‘

r on e LS B ch an ge in di gi ta
ti on : It is a ch an ge in analog output fo
This section has 8 lines. . RLRL, - RL... Plus 2 aadit
: 0
The keys are automatically debounced and Ebon
additional li |
aa oboe an twomodes:
and CNTL/STB. 1. Re
is given by
so lu
(1 /2 n )* Vr ef . If n = 8 (i. e. 8- bit DAC)
1/256*5V = 39.06mV
>>two key lockout mode or DA C to se tt le fo r a fu ll sc al e code
li ng ti me : I tis th e ti me re quired for the
2 Sett
>>N-key rollover. |
change.
alog converter
pressed simultaneously only first keyi
| tieIns tw e id lockout mode if 2 keys are 08 00 8- bi t Di gi ta l to An
DAC
Features: ct ur ed by Na ti on al se miconductor.
In N key rollover mode, simultaneous k eys are recongnized and stored in inte nalt 80 0 is a mo no li th ic 8- bit DAC manufa
(i) DACO
buffer: around 100ms °
es , it can also be set et up p so so that no key recongnized until only one key is remai red (it ) It ha s se tt li ng ti me
i.e . fr om 4. 5V to +1 8V . Us ua ll y
on a ra ng e of po we r su pp ly voltage
(iii) It can operat e ke pt at a m i n i m u m of -12V.
This has a FIFO RAM. V+ is 5V or +1 2V . The V— pin can be
the su pp ly
; ti on of th e D A C is 39.06mV
The status logic kee ps track
:
request) signal when FIFO is ee ape
m
ee
provides IRQ(interruptl (iv) Resolu
25k
| v 14 WW SV
DISPLAY SECTION at hey oP
= B,-Bs +s
This section has 8 output lines divided into 2 groups of 4,A,—A, and Do-D7 PA-PAg
T re ap 7 3g B o- By. =
hese lines can be used in: both ways 8 lines or 2 sets of 4 line —W— 15 =§
Vo
s
eee eoep os
TOR, 4 8255
Se ay can be blanked usius ing
The displ; ea li
BD line. The section has 16 x 8 disp] ay NAM
~-
om, | | ~12Ve—
r e e 3 Tapers Se oe
This section has scan counter and 4 scan lines. SL 0.1 4 4
decoded 1usi
using a 4 9 — SL,. These 4 scan lines canbe
— 16 decoder to generate 16 lines for scanning =
:
 42-2016 Sixth Semester, Microprocessor and Microcontrolle
r
ALP to generate Square wave
LP. University—(B.Tech)-AB Publisher 2016—43
0000:4000 MOV CL,FF
are available
* Internal Data Memory: Up to 256 bytes of internal data memory
O0nn:4002 DEC CL
0000:4004 JNZ 4002 ia depending on the 8051 derivative. Locations available to the user occupy addressing
is divided in several
| _ space from 0 to 7Fh, ise. first 128 registers and this part of RAM
0000:4006 RET and indirectly
blocks. The first 128 bytes of internal data: memory are both directly
0000:4007 MOV AL, 80
) addressable. The upper 128 bytes of data memory (from 0 x 80 to 0 x FF) can be,addressed
0000:4009 OUT 67, AL | + only indirectly.
0000:400B MOV AL: 012 | r t Since internal data memory is used for CALL stack also and there is only 256 bytes
is crucial for fast
ee a splited over few different memory areas fine utilizing of this memory
0000:400D OUT 63. AL ;
_ and compact code. See types efficiency also.
0000:400F MOV AL. 00 which means that each
Memory block in the range of 20h to °Fh is bit-addres sable,
a a : this
are 16 such registers,
0000:4011 OUT6 ,
3 | | bit being there has its own ‘address from 0 to 7Fh..Since there
0 :
000:4013 CALL 4000
1, AL block contains in total of 128 bits with separate addresses ( Bit 0 of byte 20h has the bit
MOV AL. FF | address 0, and bit 7 of byte 2Fh has the bit address 7Fh).
0000:4016
| | a 3 | | Three memory type specifiers can be used to refer to the internal data memory:
0000:4018 OUT 61, AL
0000:401A CALL 4000 ee ee |
tr ne ee seats sae ae
pe pee tee ea gen G :
ae aa
inde aaeentn
| |
Sree
JMP 400F
an
0000:401D

ee
Q.7. (b) Explain. the interfacing of 8254 wiihieiee <.
| aae : addressin rect addressinging
— a
indi = ng !|

|
n ‘ | ~ Bark O Foohex |OOHT
with the help of neat di

Bark 3 1F; a !
1 |
eeeOo. (2 Q.5
} (6) of End Term 2016. <
addressablefe
| 16 bitregisters P Le, S | :
functions aan and ee RS1 bits memory organizt ion in the € 8 8051 and also write the aan_ Ce ee r |
in the PSW of 8051 Ww ;
. we
ew . tin
Ans 8051 Memory Organization Th

into Program Memory and Data Mem ory. Program microcontr

¢ 8051 Memory oller’s
(ROM) is memo
used ry is di divided 1| 80 free |1
Saving program being executed
uted, while Data Memory (RAM di ae OE ae | ls
storing and keeping int € intermediate results and variables ~ 18 used for tempor arily | — 7F hex FFh !

2 1 ~ RAM memory {
Address FFFF hex apse ys se e
aoem naar TS Tee ee paoeeemr
am
numbers are stored in RAM locations 50H onwards.
| Q.8. (6) Ten hexadecimal largest number should be5)
Eo) Be Seesa program to find the largest number - .
in se set. The
EA pin =0
eS Write
5 | Additional rom saved in 60H. ere
to find largest number among given block of numbers using
| Ans. A program
(oak nee is ; 5 |
max.
‘microcontroller ~ |
Address FFFF hex so
MOV DPTR,#5000H:
= |
: | | “CER 6 >
: Address 4000 hex MOV R2,#09H e
BN 1a
c :
|

im +f t er MOVXA,@DPTR
| Seonn nmomo
ee Address 3FFF hex | MOV 60H.A |
Embedded ROM | UP: INC DPTR-
ee MOVXA,@DPTR
Werccentralles CJNE A,60H,DN
-Address 0000 hex-» | ee
Se ce = ———__—/ ¢ ee 51
ne See aS SS SJMP NEXT
aw - LIL IL ILI}
wren
=
 A ao a so es 5 ——
. ar. <a a - a a
. ‘ Le? is
~ 1
peeks 2 BIS eal. Se)
.
} — ee rs eee Ag - os
24) eg
y
3 Pi) 71 7 i
F Pity * 4
an
a
Pod eAcae SoU IAN ie Soe a
MSO ee ree aid As
a tats | oh)

MO V 60H,A : controlle,
“rO k
a Publisher 2016—45
; i | LP. University-(B.Tech)—-AB
IN XT: DJINZ R2 Up
ica tes tha t ope ran d is a dat a. If ‘# is not present
6BH ind
) f > ¥ given above ‘#’ symbol before
; as a address.
M ee DPTR ae ‘hag Z then the hexadecimal number considered
OV A,60H
| | a Direct addressing mode:
MOVx @DPTR A the add res s of the data (source data )
g mod e in whi ch
= ae This is type of addressin
3 d.. i.e. it is giv en dir ect ly in the for m of numerical data.
RET __ Fisgiven as operan
f Block of numb ae e.g. MO V B,2 0H; The ins tru cti on abo ve mov es val ue at add ress 20H memory location
se f :
r om location 5000-5ers ; 1Sj stored at locat
s of SFR.
block eos ¥ to register B. Here 20H is addres
Register R2j Iss eae oe °000H, oa
al Bye Numbers gto.) ; ference between direct addressing and immediate addressing mode is, we
f The dif
etched during first te 4S a counter for 10 ike immediate mode.
> 8 don’t use Ww in direct addressing mode, unl
j xecutio number S, It is set to 09
First number
is stor as tw ® number a‘rel Register addressing mode:
pre
Second Number is ee In Accumulator and This is typ e of add res sin g mod e in whi ch we use the reg ist er nam e directlyas source data.
en fetched and st Served in location 60H
exe cut ion of this ins tru cti on con ten t of register R5 is get
e.g MOV A, R5 After
ater) copied to location accumulator.
a Register direct addressing mode:
data is given by value at regist er
In this mod e of add res sin g add res s of sou rce
ars
ire ctl y tha t’s why we cal lit asa ind ire ct register addressing mode.
| ind
Her e in this ins tru c tio n reg ist er R1 hol ds the address, suppose
e.g. MOVA, @R1
er exe cut ion of abo ve ins tru cti on val ue at location 20H is
| value at R1 is 20H’ then aft
Her e sym bol ‘@’ ind ica tes add res s. In thi s type addressing
transferred to to accumulator.
mode w e can use only register RO
and R1 to provide indirect address.

oy Indexed addressing mode:

groups: instruction :‘
In this type of addressing mode we use following
Arithmetic Instructions
1. MOVCA, @A+DPTR and
Branch Instructi 10ns at the location
2.MOVCA, @A+PC ‘MOVCA, @A+DPTR’ instruction copies value
Data Transfer Instructions of content of accumulator and 16 bit register DPTR. Suppose
_ given by result of addition
| 7 valu e ‘100 0H’ then afte r the execution of
Logic Instructions 3 | a - Accumulator contain 01H’ and DPT R cont ains
Bit-oriented Instructi ? te e,
A, @A+ DPT R the valu e at add res s ‘1001H’ will be transferred to
| 3 ‘a - instruction ’MOVC
Aen | fas
°*INCR
1 — Means: Increment register R1 (increment register R1); ia ~ accumulator.
n by result of addition
MOVC A, @A+PC’ instruction copies value at the location give
Lon Jum p LAB S (lon g e jum p
aaa to the add res
addre ss s mar ked
mark ed as (P ro gr am cou nte r). Suppose Accumulator
P 5 — Means: g | of content of accumulator and 16 bit reg ist er PC
LABS); ‘10 00H ’ the n aft er the exe cut ion of ins tru ction "OVC
contain 01H’ and PC contains value d to accumulator.
e JNZ LOO P — Mea ns: Jum p if Not Zero LOOP (if the number in the accumulator is g at ad dr es s ‘1 00 1H ’ wil l be tr an sf er re
: ng modes. _ A, @A+DPTR the value
not 0, jum p to the add res s mar ked as LOO P) diff eren t type of addressi st er s of 8051 in detail. (5)
TM OD an d TC ON re gi
LPO 2 J Se ea Q.9. (6) Explain
¢ Immediate addressing mode r Co nt ro l (T CO N) Sp ec ia l Function Register
Ans. 8051 Ti me
e Direct addressing mode TCON Bit Function
Bit Symbol
: rol ls fro m all 1's to 0.
e Register addressing mode 7 TF1l Timer 1 Overflow flag . Set whe n tim er
upt ser vice
pro ces sor vec tor s to exe cut e int err
: Regi ater indirect addressing mode a Cleared when
¢ IndexedAn addressing mode. | 7 a ‘| routine located at program address 001Bh.
= eee is scemnedes con tro l bit. Set to 1 by pro gra m to enable timer to
6 TRil Timer 1 run
ediate aat —
ie Aes er ediate’ thi addressing mode transfer 8 bit imm count; cleared to 0 by program to halt timer.
a , an
AS word indicate ‘immeaia 1S
eo)
to destination. imme a
ee ata hex 6B to accumulal =

—
:

the
*

In
: ‘ .. yi aX ALY

.
the

data
ae gh 7 Res ae ‘ oii a a .

ediate
‘,

imm
moves .

‘nd icate
instruction

| modé we use ‘#’ symbol to

A 4 #6BH; Thi s
F Foci ee ee

i ano” >
~S. as ian
“4a
; on een
i o

%
Sees 2 aete
ee
Ye a
se
 46-2016 Sixth Semester, Microprocessor and Microcontroller
4
I.P. University-(B.Tech)-AB Publisher 2016-4
5 TFO | Timer 0 Overflow flag. Set when timer rolls from aj] l’s tone | Bit Addressable)
Cleared when processor vectors to execute interrupt sora TMOD: Timer/Counter Mode Control Register (Not
routine located at program address 000Bh. ®1
| . a aoe Te mo) gate | crt 11 Mo
4 TROI Timer 0 run control bit. Set to 1 by program to enable timer jp
k count; cleared to 0 by program to halt timer. at Timer 1 Timer 0
3 IE1 1 External interrupt 1 Edge flag. Set to 1 when a high-to-low
| edge, edo.
signal is received on port 3.3 (ENE4), Cleared when procegadl ;
Gate When TRx (in TCON) is set and Gate = 1, timer/ counter ; will: ia Se i si
rae |e
vectors to interrupt service routine at program address 0013h - | high (handware control). When Gate = 0, timer/counter x, will run only while
Not related to timer operations.
= control) (i
2 IT1 ] a
External inter .
rupt 1 signal type control bit. Set to 1 by programot C/T Timer or Counter selector. Cleared for timer operation (input from interna
system clock). Set for counter operation (input from Tx input pin),
to! enable external interrupt
: 1 to be triggered by a falling edge |
signal. Set to 0 by program to enable a low-leve
. M1..-~- Mode selector bit (note 1).
interrupt 1 to generate an interrupt. signal
1
on external ; MO. Mode selector bit note 1).
ae

1 IEO1 ~—_—s&External interrupt 0 Edge flag. Set to 1 yy M1 MO Operatingmode .

signal is received on port 3.2 (ENF). when a high-to-low edge 0 0 O 13-bit timer
Cleared when processor 0 i 1 16-bit timer counter
vectors to interrupt service routine oa . ad timer/counter
at 1
Not related to timer operations. ee adres 0003h, 1 a Fs Seno tik as 8-bit timer/counter controlled by the standard timer 0 control
control bits.
0 ITO] External interrupt 0 sign bits is an 8 bit timer and is controlled by timer 1
4-4. 3 (Timer 1) timer/counter 1 stopped

signal. Set to 0 by program

interrupt 0 to generate an interrup
When TRx (in TC ON ) is set and GA TW = 1, Ti me r Co un te r, wil l ru n
t.
GATE trol). When GATE = 0, ‘im
Bit addressable as TCON.0 to TCON.7 only while INTx pin is high (hardware con
q counterx will run only TRx = 1 (softwar
e control).
Direct Byte Address is. 88h. —. oT < ion (input
Timer or Counter selector. Cleared for Timer ageration ne from
ae
(MSB) TCON Register ae
ar lock). Set for Counter operation (input from
internal system clock).
TCON.7 TCON.6 TCON.5TCON.5 TCON.3 TCON.2T at in).
See CON.1TCOMS ae
ae MI ‘Mode
F
selector bit (NOTE 1).
irect address 88H} TF1{/ TR1]| TFO | TRO Et IT1 EO | 1T0 at MO Mode selectro bit (NOTE 1).
Bitaddress 8F 8E 8D 8C 8B 8A 89° 88 Note 1: _
| rating Mode
This bit is set by the processor when there is an interrupt is an
interrupt at NT1
M1 MO ore
This bit Is cleared by the processor when there is a jump to ISR of NT7 ORO 0
&
13 bit-Timer
2
Set this bit (0) for an interrupt generated by a bw level signal at NT1
a 1 Yq 16-bit Timer Counter
Ciear this bit (1) for an interrupt generated by a falling edge sign
atal
NTT 2° 8-bit Auto-Reduced Timer Counter
This bit is set by the processor when there is an interrupt at NTD | 1°. 0
| | , 3 (Timer 0) TLD isoe an 8- bitit Timer
Tim counte
Grisr contro led Timer
on Bbit by the
This bit is cleared by the processor when there a jump to ISR of NTO
bi | standa
Set this bit (0) for an interrupt generated by a low level signal at NTO and is rd Timer
contro lled u by
Siegr recove
Timerred 1 bits
contro | bits
its.
3 Clear this bit (1) for an interrupt generated by a falling edge signal at NTO
3 (Timer 1) Timer Counter 1 symbol.
———_—_—____
1 ot | | ;
it Function
: TMOD Bit : imer 1. Set
Bit _ OR gate enable bit which controls eon is set and
ce 7 Gate — OR ga to enable timer to run if bit TR1 in oan to
oS to 1 by program L interrupt INF# is high. Cleared to 0 by P
art
; on external in e
Spat it time to run if bit TR1 is set.
ay e
 48-2016 Sixth Semester, Microprocessor and Microcontroller
6 C/T —Set to 1 by program to make timer 1 actasa counter by c 3
from external input pins 3.5. Cleared to zero by program to makegen
e im
E PulseDule. FIRST TERM EXAMINATION [FEB. 2017]
a timer by counting internal frequency. er Actas
© M1— Timer/counter operating mode select bit 1. Set/cleared a SIXTH SEMESTER [B.TECH]
select mode. i)
oc’ PY Program MICROPROCESSOR AND MICROCONTROLLER
a [ETEE-310)
select mode. a#o wa . Sed
‘al Time:1, Hrs. MLM. : 30
3 Gate—OR gate enable bit which controls RUN/S
TO P of timer
j 0. Set
‘ to iy“ii | 1 is; compulsory. Attempt any two from
Note: Q. No. the remaing.
program to enable timer to run if bit TRO j TCONi i ;
at and signa a
itenupt ENF is high. Cleared t 0 ze §
0 by program to set
enable t; l On externa) Q.1. Attempt Any five.
TRO is set. e ti en
| | me to run if bi , Q.1. (a) What is transparent latch and why is it necessary to use a latch with
_ output devices such as LEDs? (2)
frrom om external in put pin 3.4. Cl Ans. A transparent latch is a storage element. It has an input, an output, and an
eared to ze gram to make timer
timer by counting internal frequency. act ag a
:
enable or gate pin. When the enable is active, the output transparently follows the
ieekos
| input (with some small delay). When the enable becomes inactive, the output freezes.
!

1 M1 — Timer/counter o perating mode select The latch is necessary for output devices to return the result otherwise the result will
select mode. bit 1. Set/cleared by shes
25 |
disappear.
0 M0W— Timer/counter operating mode select bit 0. Set/cleared by progr Q.1.(6) The memory address of the last location ofa 1K byte memory/chip is
a (2)
select mode. | given as FBFFH. Specify the starting address.
Q.9.(c) Explai
at
4 b Ans. As given last location of [Kbyte = FBFFH
he piain the following 8086 instruction
7.

| __— Number of register= 1K= 1*1024

2s
a
~

TEST:; Logical
7B co mpare 2 instructi
j ‘
a
t>
w

af Starting AddresssF BFFH-03F FH=> F800H.

logical AND operation on the Q.1.(c) Explain why unconditional RET instruction is requires 4T
state s to
t=
* =

two speeds = eae instruction performs a bit by bit fetch.

fetch whereas conditional RET instruction requires 6T states for
qT; - | a eties tis . : (2)

another eee When

ner instruction.
LOCK it instruction prefix, T
is executed the has: ) r with Ans. RET: Return from Subroutine Unconditionally
es it } , nothone The program se quence is transferred from the subroutine to the calling program
the spec ifie d flag of the PSW as desc ribe d belo w. The two byte s from the top of
based on
execution begins at the new
the stack are copied into the program counter, and program
address.
RZ, RNZ
RET conditionally: RC, RNC, RP, RM, RPE, RPO,
if Carry is set) The program sequence is transferred toa
.4 i Example RC: - (Return
is 1)
| particular level or a 16-bit address if C=1 (or carry
4T states to fetch the calling address of the program.
ae Unconditional RET requires
|
| | | _ It doesn’t require to check any condition.
7
Whereas conditional RET requires 6T states to fetch the calling address of the
‘apt | a
the con dit ion is ful fil l. If con dit ion is not true, it
| = a program, as it has to be wait till
es fewer T- states.
continues the sequence and thus requir us ed in 808 6.
‘a
OF FS ET as se mb le r dir ect ive s
| @.1.(d) Explain ASSUME and (2)

ASSUME directive is used to tell the assembler

e
Ans. ASSUME Directive - Th used for a specifi ed se gment. The 8086
sh ould
that the name of the logical segment ent s: a Code segment, a data segment, a stack
be
ly 4 physical segm
works directly with on
segment, and an extra segment. bl er th at th e lo gi ca l se gment
CS :C OD E ;T hi s tel ls the a ss em
Example: AS UM E for th e pr og ra m an d sh ou ld be treated
co nt ai ns th e in st ru ct io n statements
named CODE .
.
ee
.
ae refers to. |
: |
tel ls th e as se mb le r that for any
.
ee ‘T hi s gi ca l segmen
da ta wi ll fo un d in th e lo
a data in the data segment,
 Ee. University-[B.Tech.|-A
B Publisher

ae One bus cycle

qT; Bah 2 poN 1 ¥
CLK
Ay9/Sg—-Ay6/S,— A BHE Out

and BHE/S, i Status Out >———-

4
OS

< Data INS

_
|

fa
Address Out

4
A
:
Hs
MO ~< Low-I/O READ, HIGH=MEMORY READ

~
><

Padi
hid
Ea
i

Serial Output Da

Meus se
RD sac eter Tat

os
Pei = emma
ta
#-TRLDV —} pune

£\,
DUR in ae eee

trie
Serial Data Ena

if, SDE =1, bitDti

i ealiih $ Biinlde
LT

> 0 = Available
Crk
if Send to SOD Don't

Stas,
if SDE = 0, pit ne Care Fig. (a) Input (read operation)

SAT
ignored,

=
_ nas Ss These are explained in steps.

=
Mia? t ~
=
@O
@

Ss
a
®

@
’ MSE = 0, D6 D7 Se
1, When processor is ready to initiate the bus cycle, it applies a pulse to ALE

t
& D, are ignored if =

Bros.= 2
set
_| during T1. Before the falling edge of ALE, the address, BHE , M/IO, DEN and DT/R
»ResetRST7.5
R 7.5 =RST7, 4 | - must be stable i.e. DEN = high and DT/R =0 for input or DT/R = 1 for output.
is not allowed 2. At the trailing edge of ALE, ICs 74LS373 or 8282 latches the address.
IfR 7.5= 0; RST 7. 3. During T2 the address signals are disabled and S,-S, ale available on AD,,/S,-
MVIA, C8H; Content of SIM=C is allowed,
8H a AD,,/S, and BHE /S,. Also DEN is lowered to enable transceiver.
SIM
HLT 4. Incase of input operation, Rp is activated during T, and AD, toAD,, goin high
| impedance preparing for input.
Q.1.(f) How Type 2 dedicated interrupt is generated. What is its we ci 5. If memory or I/O interface can perform the transfer immediately; there are no
location?
| _ wait states and data is output on the bus during T;.
Ans. Type 2: NMI (Non Mask-able Interrupt) (INT2)
6. After the data is accepted by the processor, Rp is raised high at the beginning ez

¢ This is the highest priority hardware interrupt and is non mask-able. The input of Ti: *
is edge triggered but is synchronized with the CPU clock and mus be active
t for two ; 7. Upon detecting this transition during T,, the memory or I/O device will disable
clock cycles to generate recognition. ) ; its data signals.
¢ The interrupt signal may be removed prior to entry to the service routine. a data on the
-8. For an output operation, processor applies WR = and then the
¢ Since the input must make a LOW to HIGH transition to generatane interrupt, data bus during T,.
spurious transition on the input should be suppressed.
e If the input is normally HIGH, the NMI low tim
| e cant qiarenica Sigua aoa 9. In); WR is raised high and data si gnals are disabled.
is oe . i oe
10. For either input or output operation, DEN
\
CPU clock times. in th e In te rr up t Ve ctar Ta ble ( VT) ord ing to the c
transfer
next e at this i tobe nectiv3 e
2 x 4 = 00008H er. Als o M/I 00 i is set acccor di
e Its ISR address is stored at s loca| tit on
transceiv he |
fa il ur es fo r ex am pl e pov , bus cycle in 8086 is four c
for catastroph ic filled by
I in te rr up t inp ut is 1s us ed the gap between the successive cycles is
pits
ll y NM
r
ca
:
e Basi
Sa,
ea
Hee 3
Sa ee
ti me ou t of sy st em watc hdog timer.
se failure, minimum mode memory re" ideal state clock cycles.
uickly during transfer, wait
di ag ra m for 8086 d
a a -@:3. (@) Draw the timing When the memory or I/O device isandnotT, able to respond q READY input of the 8086.
by disabling the
mo de 1s s h o wn} : states (Tw) are inserted between Ts
i n i m u m
diagram for read operation 1 n
am m The bus activity during wait state 1s s
ame as during Ts.
eet
'
 S
ae se Cotten: ixth Semester, Microp ro
c :
co e for MOv is “es
0010
binary cod
© for the MOV Cg, > | [BX]
cessor and Microc
7 ee
Ans,
~15. Tech. |~ 2017-5
Convertir
hstructions to ene Uage
— MOD = 11 aoe
Effective Address Calculatit
|
R/M W=0 Wei
de
=
MOD aa
POODE .
AL a. a =t0
; 000 =<
B(BX)+(S1)+D
= 000 = (BX)+(6D) (BX)+(51) +D,
SH oT oa
| a
001
CL
=
CX | on (
(BX)+(DI) a ae
3 _ xan
= DL .
* An instructic
can be coded ed w ; Be sre ne | 010
Hl ae as 010 (BP+(s1
°B ion
conta;
1 ¢ 6 bytes
=p with | +(SD+D (BP iG
yte 1 three kinds of O11 B ; +(SD+ Dig
Opokas « sare AH gp (BP + (DI) (BP)
(DI) +D, (BP)+(1)+ D i
: intormati ; 100
BP
100 (SD) (SI) +D 3 (ST)
eld (6 bit
s) Specifies th
© operation such
10n;
101 CH 101 (D en a
Bex Register D} irection Bit
1t (D bit) ch as add subtr fact | ST fie a
(DI) + D,

* Tells the regi

110 DH
re ld; :
Or Move
ee ee | (BP) i.+ D..
(BX) —
sister operand in REG e
BH DI 111 obi (BX) + Dg)
og Data fl
or d | - ee 16
eld in byte 2 is source r desti [¢ ;
Data Ow to the REG field f; om R/M Nation operand
override prefix 3
0:
— VU: Data f] id) | Segment Byte 1
Shee ow from the REG field to the R/M | | |code format
—-D
ata Size Bit (W bit) bi Opcode MOD. REG RM
© Specif \0 Oe yy
will be r ; 100010DW
— : led whether the operation Sead 16-bit dat } | a O41 ee ;
Wl be performed on 8-bit or 10001 00 0
—2 ae 0:3 b=i -= ,
z ata. 2a CS 5 Opcode FromDL om ate
its ‘2 ; eee =
° ; | : Memory No Disp
° Byte 2 has two fields mst | Machi
bit: =F er achine Code = 2E8817H
— Mode field (MOD) - — 22 bits Q.2.(c) Explain the difference between LEA
i ot | - a en (2)
oe field (REG) — 3 bits MOV instruction z
ot Ans. The :
| __ The MOV important
instruction is the mostIt also
— #tegister/memory field (R/M field)
th Se oe has uae in the 8086 because it moves
¢ REG field is used to identify ’ the register for the first operand z
one location to another.
4 , data from
th ee eters; soit theto
REG oo programmer can use MOV effectively, are easier
Jak assembler y, the rest of the commands
Z| ? = Wes
000 ae| understand.
foe 6 : AX
|
ae format:
oer ape
|
001 Cle: CX: is a a destination,source
DL ; | DX
aval V copiespies the the data ata ini the source to the destinati
this has to be explicitly sated a oa Fee eet ait
. BL at He word. Sometimes ee ee
Kae . ve BX
cctermine from the operands whetheré ab yte or word is being referenced.
100
SP feae The MOV:
CHre a a V instruction has a few limitations: 7
|
101 BP ) : register directly (i.e. mov
ae ‘ae ¢ An immediateate value cannot be moved into a segment
110 - | | F as,10)
| ee — | : sf
111 re ; a
cannot be copied directly (i.e. mov es,ds)
;
i a registers ea
specify the second operand — - | . location (i.e. mov
e 2-bit MOD
> Le
field and 3-bit R/M field together
a e ¥ * A mem copied into another
memory
: RTE?
| Te :
Ste : ed ,a: aNumber ?aDigit) leeation
a : ;:
—
ee copied to (i.e. mov cs,ax)
a eC
Explanation
; 2
.
— e —
follows. 4 overcome using indirect data
ata movement thro through a general
Code displacement : can be g
-
b- mode. no os imitations a
0| ‘Memory ¢ | ;
in the general format given above.
|j, ) ae | purpose register as illustrated
called an address.
| 01 MeO? mode 8 bit aaa of the possible values for the destination and source is
displacement follows e LEA instruction
Memory Mode., 16-bit 3
10 . a
|
displacement follows | |
a register, momory
loads the specified register with the offset of a memory
: Address
11 Register Mode no— displacement 1 oad Effective
— Ocation,
-bit displacement follows The following two lines of code are identical:
Fixcept when R/M = 110, then 16 )
 6=—2027 Sixth Semester, Microprocessor and Microcontroller I.P. University-[B.Tech.|-AB Publisher 2017-7
mov ax,OFFSET aMessage ie Mnemonics T-States
lea ax,aMessage
MVI D, 03H 7
However, the MOV instruction cannot be indexed because OF FSET is an assemble, Loop2: LXI B, FFFFH 10
directive, not an instruction. It would be impossible to say Loop1: DCXB 6
mov ax,OFFSET aMessage+[BX]
MOV A, C 4
since the offset calculation is done at assembly-time. On the other hand, it is ORAB 4
possible to issue the command
JNZ Loop1 10/7
lea ax,aMessage[
BX] DCR D 4
example: — JNZ Loop2 10/7
lea dx,aMessage
Time delay given by Loop1 (td1) =0.314568 second
mov ah,09h
Approx. Total time delay (td)= 3* tdl=> 1 second
ructions
Q.3.(c) Describe the effects on the Flags when the following inst
int 21h
Notice that this is the same standard method of outputting a string to the screen, | h ins tru cti on, ass umi ng all Fla gs = 0 (re set ) and register
are executed. Before eac
It is preferred to use the LEA instruction in such situations, makin g offsetting of the contents are: A= DAH; B = 06H; C=9CH 4)
string easier in future. Mov. B,A
Flags DCR Cc
The flags are a set of variables in the CPU which indicate the status of various. i ADD B
calculations and components of the CPU. Flags are used, amo g others, in the following IN 22
contexts:
RAL . |
* to indicate errors Ans. MOVB,A; B=DAH
* to indicate the sign of the last calculation DCR C; C= 9BH
B; A= B4H & CF=1. es
* to enable a carry during arithmetic operations 7 i F ess 22 data.
ow the con ten t f inp ut por t ad dr
* for debugging nee A=XX. as we don’t kn ae
| :
A number of instructions perform certain tasks based on th e current state of the | RAL; A=01H & CF=0 s of the 8 =
the da ta in ce rt ai n re gi st er
flags. Q.4.(a) At a particular instant,
- BP
BP == CD CDEFH; CS

een
Q.3. (a) Given that: BX = 637D, SI = 2A9B, Displacement = C237. SI = 567 8 H; DI = AB EF H;
ae= = 12: 34 } H: ’ BX == 3456H; CX = 10 H;
Determine the effective addr : ess (if a pplicable) resulting from these
in st ru ct io n MO VS B
S B 1 ed
is executat
registers and the addressing mode: (3) 4 : SS=9097H. If now the
poses i
1” the me mo ry . . Als Also indicate wha
(1) Immediate (2) Direct = 2 st e
at ee eearly what happens
cl
by he Sear s
e le ft in th e ab ov e registers.
(3) Register using BX (4) Based Indexed sactem bed ible
da ta ar
.

me D fl ag is se t | |
Ans. (i) No effective address is used © Assu S:SI into ES: DI
-

of byte . D
(i1)Direct effective address is given in the instruction itself 3 | qi
Ans. MOVSB : copies contents
= 0 ; Fo rw ar d pr oc essing (L 0
(111)No effective address is used Direct io n Fl ag
| | ‘ ( R to L)
DF = 1; Backward processing C8H
(iv)BX+SI = 8E18H
d r e s s of s o u r c e D S : SI =Sis 959
Physical Ad ation BS : DI = 7256FH
Q.3.(b) Write an ALP to produce a delay of 1 second. Consider the 8085 | e d fr om 959C8H to
10 bytes of data are m o v
clocked at 5 MHz. Physical Address ate nvaer
; | (3) He r e D F = 1 & C X = 1 0 , That m e a n s
Ans. In 8085 single register cannot be used to generate 1 sec time delay, So wen
to use time delay using a loop within a loop technique:
eed —
“a
: ‘1256Fy : system having
a
_ Given tame delay= 1 second and every time DF = 1. ocessor 8086 based microcort Jevice. The 10
Qh) Designs ee ory map should not
oKram, | input See Ths memmem
Frequency of 8085= 5MHz | 4 chips of 4k RAM. ace memory mapped 10, ory map of a lete
Time period of 8085= 0.2usec devices are invertace aa asem. the comp
a have any fold back 4
ALP to generate 1 sec delay
microcomputer system.
 ee a a
% . de her POA Bas: s age

8-2017 Sixth Semester, Microprocessor and Microcontroller

Ans.
Four chips of 4K RAM = 16 K RAM _ END TERM
Two chips of 2K RAM = 4 ne EXAMINATION [MAY-JUNE. 2017]
| SIXTH SEMESTER (B.TECH.]
16K RAM address lines : 24x 2! =A. -A
4K RAM address lines : 2? x 210 ak e . — ll
. MICROPROCESSOR AND
:
MICROCONTROLLER
Table Memory Map 7 [ETEE-3 10]
See = _ = _ - . Ay A) An Ajy Aw Ate Any Ape Bos Ay Agy by Ay A, Ti:me 3 Hrs.
FC000 . iacce URS M.M. : 75
q
eee lee al T- fi Note: Q. No. ‘1 is compulsory. Attempt any five Questions from remai
1 l l 0) 0) 0) 0) 0) 0 () 0) 0 0) 0) 0) 0) 0 | questions from each
ning. Select one
unit,
16 K RAM a
FBFFF aap a Poe ey 1-7 Q.1. (a) Draw and explain timing diagram of memory
FB000 read machine cycle of
bore e Be O00 eee 0 0 9 | 8085- | (2.5)
| | Ans. Read Cycle : The high order address (A,, <>A,) and low order address (AD, ©
| , a AD,) are asserted on 1st low going transition of the clock pulse. The timing diagram for
= of 10/M read are shown in Fig. The A,, A, remains valid in T,, T,, and T, i.e. duration of
2 ae cle,, but AD, 7 <= AD, 0 remains valid only in T,.1 Since it has to remain valid for
the bus cycle
= Odd | the whole bus cycle, it must be saved for its use in the T, and T,,.
16Kx 8 "
.
| 4-1, BHT, PE T3 Et 1 4-T Et Tt CT
Poo Os ae CLK
CS, + cs, =Ai2 Ais Arg
lOMae |O/M = 0,S,=1.S,=0
cS, = CS, { ee
CS, , a F S4;S0
ake = Odd - .
Cs, +c =O 14 16K x 8
oe PC L=Ai, = Ag Xe Unspecified
a : As
F
D,-D,.

CS,

ae 4K x8

: | | —J D,-D,5 3 I
Q.4.(c) Consider the Instruction Fi - Memory read timing diagram
ee teh e ing of T, of each bus cycle and is negated towards the
: 2010H JUMP p; oF ALE is asserted at the beginnin
What 1sis the
th value of Disp , das the clock pulse to latch the address
= to go meto the memory (2) | endofT,. ALE is active during T, only and is used as the clo FT. Itends at the end of
Ans. 2010H locati 0 a‘| AD
: H JMP 2005H
ry location 2005 H. (AD, AD,) during i T.. The RD is ase asserted nearchethememo
begirynninorg I/OOF port
45. to assert data. RD
| | T,.As soon as the RD becomes active, it forces emory to terminate the data.
rr
a| & inact
becomes inact ive towar ds the end of T,,3 caus the in
port g
orm
: orv :
location 7000H into regis ter B by
of Q.1.(b) Transfer 8 bit data of memory | (2.5)
2 _ using three methods.
ie Ans, (i)LXI H, 7000H

| j , | | - (ii)LDA 7000H
i 3 ie : on MOV B, A
(iii)LHLD 7000H
MOV B, M
 10-2017 Sixth Semester, Microprocessor and Microcontroller I.P. University-[B.Tech.|-AB Publisher 2017-11
nte r poi nts to loc ati on 00 00 H. In wh ic h memo, |
Q.1.(c) In 8085, the stack poi oe
used? (2. Q.1.(e) The contents of DS is 32A5H. The amount of data that is to be
location will be stack contents be stored if the stack is is 12K byte. Wher e in memory, will this segment be located?
; data
in segm ent
Ans. So in order to answer this question, we need to really understand how the Ans. Data segment
PUSH instruction actually works in 8085. Consider the following situation: DS : BX/SI/DI gives the physical address.
Register B has contents 0xAA Q.1.(f) Draw and explain Interrupt Vector Table of 8086.
interrupt
Register C has contents 0xBB Ans. Interrupt Poini t table/Vector Table: : When an ininterrupt : occurs, the
a FAR Ste
SP = 0000 eR are called in the same manner as that used for calling
a 086, two 16-bit data words are required to specify the memory location, i.e.,
Now, Let us assume the instruction encountered is PUSH. The PUSH instruction As in S so two 16-bit data words are used to specify the location of the eens ee
first decreases the stack pointer SP addres
ano ‘ One word is used to load the CS register and points to the starting
B -> OxAA eede segment containi ining ng the service routine. ) .
C -> OxBB t word s for all thes e inte rrup t ae o ee Pet icetions
i ae ee offse
ble or interrupt point table. In 8086, the firs t .
SP -> FFFF
interrupt seo to 0OO3FFH are set aside for this interrup pointer table. ’
and then stores the higher order register, decrements again and then stores the starting with hea
the 256 type s of inte rrup ts are classified as Sons
lower order registers as well. As seen from figure, ;
~1ots and available interrupts her are the reserved interrupts. Eady
B -> OxAA reserved pees by the intel for the furt processor. hie on Be ieee
C -> 0xBB their ISR addr esse s in these oe :: r
eae. “ee for load ing
FFFF -> 0xAA 255 are avai labl e to the user to store their ISR addresses.
ee 0 ae
FFFE -> 0xBB
SP -> FFFE
Q.1.(d) Explain assembler directives: EVEN, PROC, END. . (2.5) |
Ans. EVEN - This EVEN directive instructs the assembler to increment the location \
of the counter to the next even address if it is not already in the even address. If the word |
is at even address 8086 can read a memory in 1 bus cycle. If the word starts at an odd | .
address, the 8086 will take 2 bus cycles to get the data. A series of words can be read
much more quickly if they are at even address. When EVEN is used the location counter|
will simply incremented to next address and NOP instruction is inserted in that ehii! 4

incremented location.
:
a

s :
Example: x a7
DATA1 SEGMENT ; Location counter will point to 0009 after assembler reads”
ynext statement SALES DB 9 DUP(?) ;declare an array of 9 bytes oak Reserved
_ EVEN ; increment location counter
to 000AH | : ;
interrupts
(27)
RECORD DW 100 DUP( 0 ) ;Array of 100 words will start ;from an even address for_
quicker read ) ~-
DATAI1 ENDS
PROC - The PROC directive is used to identi fy the start of a procedure. The term
near or far is used to specify the type of the procedure.
Example: 4 |

SMART PROC FAR; This identifies that the start of a procedure named as SMART
and instructs the assembler that the procedure is far .
j :
ie

SMART ENDP This PROC is used with ENDP to indicate the break of the procedure, & .
END - END directive is placed after the last statement of a program to tell the 4
assembler that this is the end of the program module. The assembler will ignore | oo)
rs

any statement after an END directive. Carriage return is required after the END gg
*

©
wah

directive. : |
eel ete:
ih
he
= ee
Ba
 LP. University-(B.Tech.]|-AB Publisher 2017-13
er , Mi cr op ro ce ss or and Microcontroller
Sixth Semest
12-2017 (2.5)
(25 Q.1.(h) With the help of a waveform, explain 8253 in mode 3.
e an d ex plai n B S R mo de of 8255.
Q.1.(g) Writ ch li ne of po 6 Ans. Mode 3 (X11): square wave generator
mode is appl ic ab le to port C only. Ea
Ans. The Bit Set/ibe Reset (BSR)itab ly the con trol wor d regi ster . BSR mode This mode is similar to mode 2. However, the duration of the high
and low clock
loading
(PC, - PC.) can be set/reset by suitably of BSR mod e does not affe ct the oper a and pulses of the output will be different from mode 2.
VO mode are independent and selection Lion of
Suppose n is the number loaded into the counter (the COUNT
message), the output
other ports in I/O mode. for n/2 coun ts, and low for n/2 coun ts. Thus , the peri od will be n counts, and
will be high
.
if n is odd, the extra half-cycle is spent with OUT high
Mode 3: Square Wave Generator
x - By B, By SIR
0 X X
= MU UU UU Ue
UU UU U

y t Setiwatl
_
ae, Gi kee
CLK

Don't care Port C bit select - mal OS Ce el Pele le

Always 0 for BSR mode
cK ~ JUUUUUUUUUUUUUL

8255 Control Register format for BSR Mode OUT — —J ba bees

iE ECEREREE
a — (UU UUUUUU UL CLK
8255 BSR mode
oe a
¢ D, bit is always 0 for BSR mode. se piri) GATE
od
* Bits D,, D, and D, are don’t care bits.
* Bits D,, D, and D, are used to select the pin of Port C.
of 8051.
* Bit D, is used to set/reset the selected pin of Port C. Q.1.(i) Explain format of PSW register
TH E PS W RE GI ST ER : Th e 805 1 has a flag register
Ans. 8051 FLAG BITS AN D
Selection of Port C pin is determined as follows:
h as the car ry bit . Th e fla g reg ist er in the 8051 is
to indicate arithmetic conditions suc
- eal led the pr og ra m st at us wo rd (PSW) register.
| Bl Bit/pin of port C selected | _|
. gister
PSW (program status word) re o re fe rred to as
st er is an 8-b it reg ist er. It is als
The program status word (PSW) regi
PC
0 Te ie
a yam Ss

0 wi de , on ly 6 bits of it are used by the

PC, aa the flag register. Although the PS
W re gi st er is 8 bit s
the flags are called
0 8051. The two unused bits are
us er -d ef in ab le fl ag s. Fo ur of
di ca te so me co nd it io ns th at result after an
they in
conditional flags, meaning that ry ), AC (a ux il ia ry ca rr y) , P (p ar it y) , and
are CY (c ar
0 Peek an instruction is executed. These four
: 0 : PC, . : | Es :
OV (overflow).
Es 0
at ed as RS O an d RS I, re sp ec ti vely, and are
e design
Jee The bits PSW.3 and PSW.4 ar ar e ge ne ra l-purpose
: ;| 0 o used to change the bank register
s. The PSW. 5 an d PS
fo r
W.
an
1
y
bi
pu
ts
rp os e. In ot he r words,
er
st at us fl ag bits and can be used by the programm
| ECr a: |
- they are user definable.
RSO | OV |- P.
: nD D; D, Disseas D0 Fe ¥ Cy | AC | F0|RS1|
: 1 ; Gh
~
1
PSW.7 Carry flag.
yada wees usar

LeECY¥
“ otha

_ GAmode | | |
Auxiliary Carry flag
le,

L x PCu GBmode}] PB. = PC, AC PpSWé_

‘

purpose
ee

th e us er for ge ne ra l
Available to
é
Ste

Teo PSW.5
Register Bank selector bit 1.
atid

RS1 PpSw.4_
»&
Owlhedt

Always 1 for
Y

GroAu mop de Grdu pA 0.

1/0 mode a r ae
Selection bit — PortA
Gro RSO PSW.3 ; Register Bank selector bit
“5

Port Gy 074 : cane ° mae : :

Overflow flag.
Spas
>

OV PpSW.2 a
‘a

pened | Ae I -Input | selecodetionOllo.{input cna 3

om ‘Ja
PSW.1 User-definable bit.
U ut (0-m
-outp
ik ea ch e a
.

routpu t] [0-output ft Parity flag. Set/clea re d by ha rd wa re

PCu- port upper P PSw.0. number of 1 bits 1n the oe
8255 Control Word for /O mode PC\-port C lower s indicate an odd/even

A
 M i op ro ce ss or an d Mi cr oc on troller
14-2017 Sixth Semester, * Mi cr [.P. University—[B.Tech.|-AB Publisher 2017-15
Register Bank Address
RS1 RSO Q.2. (b) What is an addressing mode? Explain various addressing modes of
OOH - 07H 8085 with examples. (6.5)
0
08H - OFH Ans. Addressing Modes in 8085
1
10H - 17H These are the instructions used to transfer the data from one register to another
2 register, from the memory to the register, and from the register to the memory without
3 18H - 1FH
, 1 any alteration in the content. Addressing modes in 8085 is classified into 5 groups—
Immediate addressing mode
Bits of the PSW Register
g aft er exe cution of ae In this mode, the 8/16-bit data is specified in the instruction itself as one of its
Q.1. (j) Sho w sta tus of CY, AC and P fla
5) operand. For example: MVI A, 20F: means 20F is copied into register A.
instruction: Register addressing mode
MOV A; #88H In this mode, the data is copied from one register to another. For example:MOV A,
ADDA, # 93H B: means data in register B is copied to register A.
Ans. MOV A, #88H Direct addressing mode
ADD A, #93H In this mode, the data is directly copied from the given address to the register. For
Both are the format of instruction used by 8051 microcontroller example: LDA 5000H: means the data at address 5000H is copied to register A.
Status of CY=0 Register Indirect addressing mode
AC=0 In this mode, the data is transferred from one register to another by using the
address pointed by the register. For example: MOV M, B: means data is transferred
P=]
from the memory address. pointed by the register to the M(memory pointer).
UNIT-I
Implicit addressing mode
Q.2.(a) Explain following pins of 8085. (6)
This mode doesn’t require any operand; the data is specified by the opcode itself. For
ALE, IO/ M, READY, HOLD example: CMA.
Q.3.(a) Write an assembly language program to sum the following series:
Ans. ALE: Address Latch Enable:
WZ iccceccsecescccassscsssscenmsorta: +F, (5)
In the previous article we saw how ALE helps in demultiplexing the lower order
Store the result at memory location 4000H assuming that the series start
address and data bus. This signal goes high during the first clock cycle and enables the
from memory location 3500H.
lower order address bits. The lower order address bus is added to memory or any ~
external latch.
Ans. Statement: Calculate the sum of series of numbers. The length of the series
is in memory location 3500H and the series begins from memory location 3501H.
READY:
Consider the sum to be 16 bit number. Store the sum at memory locations 4000H
READY is used by the microprocessor to check whether a peripheral is ready to ~ and 4001H.
accept or transfer data. A peripheral may be a LCD display or analog to digital converter
3500H = 0FH
or any other. These peripherals are connected to microprocessor using the READY pin. —
If READY is high then the periphery is ready for data transfer. If not the microprocessor — 3501H = 01H
waits until READY goes high. 3502H = 02H
HOLD: 3503H = 03H
This indicates if any other device is requesting the use of address and data bus. 3504H = 04H...
Consider two peripheral devices. One is the LCD and the other Analog to Digital Result = 14+2+3+4+5...4F= H
converter. Suppose if analog to digital converter is using the address anddatabusand —
4000H = Lower byte
_if LCD requests the use of address and data bus by giving HOLD signal, then the d f
microprocessor transfers the control to the LCD as soon as the current cycle is over. _ 4001H = Higher byte
After the LCD process is over, the contro] is transferred back to analog and digital Source program:
converter. LDA 3500H
1O/ 1 ’: MOV C,A : Initialize counter
Consider we have an address to be processed. But how do the processors know LXIH,3501H _ : Initialize pointer
whether the address is for memory or I/O functions? For this purpose a status signal SUBA : Sum low =0
called IO/M ’ is used. This distinguishes whether the address j s for memory or IO, When MOV B,A Sum high = 0
this pin goes high, the address is for an I/O device. While the pin goes low, the address BACK: ADD M - Sum = sum + data
is assigned for the memory. JNC SKIP
 16-2017 Sixth Semester, Microprocessor and Microcontrolje,
I.P. University-[B.Tech.J-AB Publisher 2017-17
P INR B - Add carry to MSB of SUM
SKIP: INX H : Increment pointer .
Start ISR
DCRC
JNZ BACK
: Decrement counter
; Check if counter 0 repeat
— | sae eee
Request device
STA 4000H : Store lower byte go get Ready
MOVA, B 7
STA 4001H : Store higher byte | 1 Execute data : transfer
Fetch next instructio
and execute ce
HLT : Terminate program execution

—Start| Check for

Interrupt
Restore Processor
Status

Yes :
Enable interrupt | .
Sum =0
Pointer = 2201H- System
Count = (2200H)
Call ISR associated
>} with this interrupt Return to main
program
Sum = Sum + (Pointer) Fig.(a) : Main program execution sequence (b): ISR execution sequence

HARDWARE INTERRUPTS OF 8085 An external device, initiates the hardware

Pointer = Pointer + 1 interrupts of 8085 by placing an appropriate signal at the interrupt pin of the processor.
Count = Count— 1 The processor keeps on checking the interrupt pins at the second T -state of last machine
cycle of every instruction. If the processor finds a valid interrupt signal and if the
interrupt is unmasked and enabled, then the processor accepts the interrupt. The
acceptance of the interrupt is acknowledged by sending an INTA signal to the interrupted
device. The processor saves the content of PC (program Counter) in stack and then loads
the vector address of the interrupt in PC. (If the interrupt is non-vectored, then the
interrupting device has to supply the address of ISR when it receives INTA signal). It
starts executing ISR in this address. At the end of ISR, a return instruction, RET will
be placed. When the processor executes the RET instruction, it POP the content of top of
(2300H) = Sum stack to PC. Thus the processor control returns to main program after servicing interrupt.
The hardware interrupts of 8085 are TRAP, RST 7.5, RST 6.5, RST 5.5 and INTR.

Interrupt type Trigger Priority Maskable ace

TRAP Edge an Level = No 0024H

RST 1.5 Edge * Yes 003CH

RST 6.5 Level 3 Yes 0034H
RST5.5 Level 4" Yes 002CH
INTR Level 5" Yes =
The type of signal that has to be placed on the interrupt pin of hardware interrupts
of 8085 are defined by INTEL. chee
¢ The TRAP interrupt is edge and level sensitive. Hence, to initiate TRAP, the
interrupt signal has to make a low to high transition and then it has to remain high
until the interrupt is recognized. | ie
the RST 7.5,
x»peratio >. At thee * es * The RST 7.5 interrupt is edge sensitive (positive edge). To initiate
ae nsnd for an : need not remain high
interrupt| diver artonS executing nd
uting
of; ISR the
its main; Processor
7 status is retrieve?
nce the interrupt signal has to make a low to high transition an it
a transfer program. The sequence |
Scheme of — until it is recognized.
is Shown in figure below.
¥

-
ae
a
sere

a _
 18-2017 Sixth Semester, Microprocessor and
Microconty l] 3
e The RST 6.5, RST 5.5 and INTR are level sensitive interrupts H
interrupts the interrupting signal should remain high, until it js Fevopnined: for thes
UNIT-II ye : - Itis used to test . and debug the hardware and software
of an exte
Q.4.(a) Draw and explain chart of program execution as the prototype ofa microprocessor based instrument.
Part of the atiinieat in a ier
assembler. Explain various program development tools used j follow; is a multiwire cable which connects the host system
n it. 8 by an to the system being developed :
Ans. Assembly Language Program Development Tools (6.5)
1. Editor | EDITOR
- An editor is a program which allows you to create a file cont PROGRAM
aining the ass
language statements for your program. embly
[we asm
Example: PC-Write, Wordstar.
- As you type in your program, the editor stores the AS CII codes for the letters i .
numbers in successive RAM locations. - d i
ASSEMBLER
PROGRAM
- When you have typed in all your program, you then save the file on the tag ig 2
This file is @ lied source file and the extension is .asm, ” My file. Ist
_My file obj. | Other obj file
2. Assembler
=e - An assembler programnis is used
U to translate the a ssembly |] LINKER
instructions to corresponding binary codes. When you run ONics ae for PROGRAM
the anemia
source file of your program from the disk whe
re you have saved it after sa
- On the first pass through the source program, the ngeee | |e abs :
| . +S
.
displacement of named data items, the
offset of labels, etc. arid sucete ae
a symbol table. ation Heein OH
PROGRAM
- On the second pass through the source pr
grove Onay
ogram, the assembler
code -forTheeachasseinstmbruct ion and inser ts the offsets, etc. that it calculated durin g the first pass, f
ler generates 2 files on the floppy disk
called object file (.0b/), or hard disk. The first fileis
Myfile. hex

- The second file gs generated ‘ Q.4.(b) Explain the difference between 8085 and 8086 microprocessor. (6)
pivene xtenei n (is) ed by assemb ApS
ler is called the assembler list file and is. | z Ans. 8085 microprocessor vs 8086 microprocessor describes difference between
8085 and 8086 microprocessor types.
8085 microprocessor 8086 microprocessor
It is 8 bit microprocessor It is 16 bit microprocessor
It has 16 bit address line It has 20 bit address line
about the linked files (exe). | It has 16 bit data bus
LR a It has 8 bit data bus
4. Locator 7 | [ae
Clock speed of 8085 microprocessor is Clock speed of 8086 microprocessor vary
-A locator is a program a : a 3 MHz between 5, 8 and 10 MHz for different
object code are to be aaa ae ee ete address of where the segmentsts f versions. _
-A locator pro 7] ; 7 7 egis It has 5 flags. It has 9 flags.
(DOS). EXE2BIN converts EXE2BIN comes with the IBM PC Disk Operating System — It does not support pipelining. It supports pipelining.
5. Debugger a .exe file to a .bin file which has physical addresses. eb BoE It operates on clock cycle with 50% It operates on clock cycle with 33% duty
- A debugge | te 8 ans ca duty cycle. cycle.
system oe aoe os to ed your object code program into 8086 microprocessor supports memory
- 8085 microprocessor does not
gger allo ws oudi esho ot or deb ug it ory loca tionirae
s— support memory segmentation. — segmentation.
- The debu
after your program runs you to look at the cont ents of regi ster s and mem
; of transistors
It has less number of transistors It has more number
compare to 8085 microprocessor. It is
_ noer
thea arn.ws you to change the contents of registers and memory locations andre-run
-It allo ol i compare to 8086 microprocessor. |
It is about 6500 in size. about 29000 in size.
- Some debuggers allow you to sto eek ih a It is accumulator based processor. It is general purpose register based
check or alter after ea
as
P €xecution after each instruction so that you can oe processor.
ch register contents. ‘
‘

It has minimum and maximum modes.

63 ry ar eae x
It has no minimum or maximum mode.
te
‘ier.
Lon ee

In 8086, more than one processor 1s used.

° ion

In 8085, only one processor is used. be

Additional external processor can also
employed.
In this microprocessor type, | MB memory
In this‘microprocessor type, only 64
is used.
KB memory is used.
 20-2017 Sixth Semester, . Micro processor and Microcontrol}e,
Mj
|
Q.5.(a) Draw and explain 8086 maximum mode configurat;
Ans. Maximum mode 8086 system and timings: 10n, .
(6 5)
In the maximum mode, the 8086 is o perated by strapping ¢ | 7 | LP. Uni nMiversity-[B. Tech. J-AP
;
ground. In this mode, the processor derives the status Signals ond ars ne Mx . Pin to Q.5.(b) Interface four chips of 2K RAM 5 ae
chip called bus controller deriv es the control signals
iona usi : So*. | Give complete memory map of the sys = two chips of 2K ROM with 8086
, an

the sais using this status informat; Other

ih maximum mode, , tl there may be more than one Micr mi oproce
em :
: 0 | (6)
guration. The other components in the system are the same wet in‘ “ie
tha'ae syste th FFF FOH. Hence this addr €S must lie in the
EPR OM. The addres
em
s of RAM may be
. The ; basic functi
ct ons of the bus con troller chip IC8288
|

; deriy 3
like RD* and WR* (for memory
and I/O devices), DEN* DIR
information made available b y the process ; ‘A
; UR » “o
etc.te
Cc, Sign
ysi al :
has input lines S2*, S1* and S0* S0* andPp CLK. orTh on the status lines. The bus contr USING the| Address Aig'9 hec 1s Ay“17 e ye. ay
It derives the cutouts Ale GEN “nese inputs to 8288 are driy Oller chip FFFFFH {4 eee “12 Air Aig Ago Ang Aoy Ang A,
AIOWC*. The AEN*. IOB an and CEN pinnaefee ne MWC ; IORG#| othe CRY Be a gf pg 1
AEN* and IOB are generally eroee sea ae specially useful for multiproccase om and| FE000H LE e ket ae jones .
gr ed. CEN pin is usually tied to +5y SOr systems | FDFFFH it Pepe age es bs OO OS OO OE 8-8 go gg. G
aH | es eae tts
—+| Reset o,, stTAa FCOOOH«=—stiséd:(C(iédd -
__IN hosel ia be Ee Ore 6° e- 6-6 O06 6 0 6 1
:
Generator
——_» RDY fencen ed Sp MRC
Reset Clk RDY —> S; 8288 f—-> MWIC —~1
—>s, Bus | » bac Tae
ueRe e—s
| - —»| “Controller
ALE eae 4——
Reset Clk RDY DE |
, S» 1 (eee Saai ea a
, J CS ° | ee
S, ; CS, RAM Aue
“> —p} Logic — CSe ROM. 22a
8086 BHE ROM — S Oe S
ie ee -—— CS;
°: OF ’
aR So lO.
~A :
|
|
O pr 2
a KK 1P/st8, Latches — Os 3
16/9 3—
Aid/Sg | 2 0r3.Qi |!
74373 |1 | = ‘
d Os 5
a et
MN / MX 4 & Data Or Pp?
X! buffers”
4. : 74245 |
~ DIR E
4 Yl CSo

RAM
| RO wa aT).
he: 1S
MRDC Mwre °
= Total 8K bytes fof EPROM need 13 address lines A,-A,, (since 2'° = 8k). Address
—
m5 lines A,,—A,, are used for decoding to generate the chip sel ect. The BHE signal goes low
when a transfer is at odd address or higher byte of data is to be accessed. Let us assume
for
that the latched address, BHE and demultiplexed data lines are readily available
interfacing fig. shows the interfacing diagram for teh memory system.
mem ory syst em in this exam ple cont ains in total four 4K x 8 memory chips.
The
parallel to obtain 16 bit
The two 4K x 8 chips of RAM and ROM are arranged in
data bus wi dt h.
If Ay is 0, ie. the add res ses is even and is in RAM , then the lower RAM,
cati ng 8—bi t tran sfer at an even a ddr ess . If A) is 1 i.e. the address is
chip is selected indi
 29 201 7
Sixth Semester, Microprocesso
r and Microcont
ro ] ler
odd and is in RAM. The BHE goes low the uppel! [.P University{B.
RAM chip is Selec Tech
that the 8-bit transfer is at an odd address. If .]-AB Publisher
the selected addr “o¢: Further indica 2017-23
respective ROM chips are seledcted. If at a time A, and BHE nee are in ROM, OUT Port C, AL
or ROM chips are selected; i.e. the data
MOV AL, Oth ; pulse to the ADC
|
transfer is of 16 bit : The se ae th OUT
takes place as shown in table. e RAM | Port C, AL
lection of7 Chips h ere MOV AL, 00h
Table. Memory chip selection
OUT | Port C, AL
Decoder UP I/P -5 A, A, Ap Selection geIT: IN
WA AL, Port C ;Check for EOC by
Address/ BHR RO As A) BHE comment
:Ww ces transfer
; reading port C upper and
: on D, > De 0 0 0 Even end’ega “Fae
| oe , a srotating through carry.
pis transfer on D, > D, 0 0 1 Oniy oe ae ae ; mrs ete
in RAM lf EOC, read digital equivalent
;i n AL
bt transfer on D, > D,,, | 0 1 0 Ohieas PPE: In RAM .
= transfer on D, > D,, 1 0 0 ivenaca al €ss in RAM
Se ee on D) > D, 4 0 1 Ongae
Se
i in ROM cs
Vref+ SS
yte transfer on D.> De 1 1 0 Only odd dae SV =
a
|
SS in ROM +SV Vec «Clock up

<D 5,
fsivnaQ.6t . D raw and d explain block dia aeof 825 PA;-PAgK = 4 0,-0,
required to initialize 8251 in gr am 1 in detail. §
asynchronous mode for foll 1
. °
ow: be ie A | rc, E00 BRC eo Pie
(i) 5 bit character length a ios : A, ~ el oe 0808 =
(ii) Event Parity (12.5) LOE GND
(iii) Internal Sync de
tection
(iv) Single syne charac =
.

ter.
- 2

IORD
= Ss

Ans. Refer Q.6. (a) of —_———_——+ PB,

End Term 2016. PB,
Q.7.(a) WWi ith the he] P own: | PB,
of a dii agram : and
analog of digital con
verter with 8086 sa
in eure IC
Interfacing 0808 with 8086
Q.7.(b) Explain internal architecture of 8259. (6.5)
Ans. The 8259A is a programmable interrupt controller designed to work with Intel
microprocessor 8080 A, 8085, 8086, 8088. The 8259 A interrupt controller can 1) Handle
eight interrupt inputs. This is equivalent to providing eight interrupt pins on the
processor in place of one INTR/INT pin. 2) Vector an interrupt request anywhere in
the memory map. However, all the eight interrupt are spaced at the interval of either
four or eight location. This eliminates the major drawback, 8085 interrupt, in which
all interrupts are vectored to memory location on page 00H. 3) Resolve eight levels of
interrupt priorities in a variety of modes. 4) Mask each interrupt request individually.
5) Read the status of pending interrupts, in service interrupts, and masked interrupts.
rrupt request.
| 6) Be set up.to accept either the level triggered or edge triggered inte
handle 64 interrupt
10) : 7) Mine 8259 as can be cascade in a master slave configuration to
8259 Ais cont aine d in a 28- ele men t in line pack age that requires ye
inputs. The
ae required ALP is 2 a ‘ 8259 . The mai n diff eren ce bet wee n the two is that the ae A i :
compatible with features such as leve
6/8 088 proc esso r. It also indu ces addi tion al
OUT used with Intel 808
ae “i ‘Initialise 8255 as , bu ff er ed mo de an d au to ma ti c en d of interrupt mode.
MOV triggered mode es uts,, TR2
t inputs
AL 02h ‘discussed above, ‘ntion: The 82 59 A has i
eig g h t ht 1
in te rr up t re qu
Fun i The 8259A
OUT Port Bar Select I/P, as analog ; 9 yA usg
pi95na es E its INT outp ut to in te rr up t the 80
80 85 A via IN TR pin .
e at its inpu t. Vector ig used 2
MOV AL, 00h 1 t.
ANpu ee ees acknowledge pulses from th
of the interrupting device,
to th e se rv ic e su br ou ti ne
;Give start of conversion the 8085 A to transfer control
 24-2017 Sixth Semester, Microprocessor and Microcontr I]
Oller
I.P. University-[B.Tech.|-AB Publisher
provided by the 8259 A on the data bus. The 8259Ai 2017-25
eee rian
must be initialized by command words sent by the. BG nee device that UNIT-IV
The descriptions of various blocks are,
Q.8.(a) Write a program to generate square wave of 50% duty cycle in P1.5
Data bus buffer: : This 3- state, bidirectional 8-bi
-bit buffer j bit of 8051. Timer 0 mode 1 is used to generate time delay ‘ (6.5)oo
8259A to the system data bus. Control words and status inturaaeion *0 interface the
through the data bus buffer. wiere transferreg | Ans. In sed the following
| pro gram, we are creating a square wave of 50% duty cycl
Read/Write & control logic: : The function n of | this block ji (with equal portions high and low) on the PI.5 bit. Timer 0 is used to generate ha ‘a
ise) |
Snes from the CPU. It contains the initialization cbintihnd oe ine OUTPUT delay. Analyze the program.
operation command word (OCW) register which store the vario ne LC W) register | MOV TMOD,#01 ‘Timer 0, H mode 1 (16 — bit mode)
or device operation. This function block also allows the st ue ORUEG! formats - TLO = F2H, the Low byte
| Here MOV TLO, #0 F2H
transferred to the data bus. status of'8159A to be
| MOV THO, #0FFH | - TLO = FFH, the High byte
Interrupt
é request | register
2 (IRR): : IRR stores all the int
Sera service. Basically, it keeps track of which intexrape ie sbuts that are | CPL P1.5 stoggle P1.5
vice. If'an interrupt input is unmasked, and has an interrupt a
corresponding bit in the IRR will be set.
ae asking for
Pt signal on it, then the
ye ACALL DELAY
| SUMP HERE - load TH, TL again
Interrupt mask register (IMR) : The IMR is used t o |
di
U : =o used to disab : delay using Timer 0
eee interrupt inputs. Each bit in this vobinter eect or Snable
DELAY:
Ree the same number.
the The IMR
interr upt operat
requestion on
lines the
of lo: Mee vile
IRR Maskin g of |
higher
o .* Pst
ority input will not affect SETB TRO - start Timer 0
mask any interrupt the corresponding bit is set ‘0’ “Ol lower priority, To ©
AGAIN: JNB TFO, AGAIN - monitor Timer 0 flag until
service register (ISR): The in service registers kee
ps tracks of which int
inteerr
rr upt ; - it rolls over
in ut

- stop Timer 0
y 1

corresponding bit will be set in thei in service register. Each CLR TRO
y

of these 3 -reg can be read

as Status reg. CLR TFO -clear Timer 0 flag
ive
Priority Resolver: This losi
ee ogic block determines the prioriti ee tC RET
IRR.
The highest priority is selected and strobed into the corteapondiaeeel of iho aa
during pulse. }
e 7
Solution:
following steps.
cade ba : In the above program notice the
of allCas
ee es function blocks stores and compare the IDS Sta=
B259A is used'amaci eo e associated 3-I/O pins (CAS0-CAS2) are output ; h 4 ‘ 1. TMOD is loaded.
3 er. Master and are inputs when 82594 is used as a slave a a he ooae 2. FFF2H is loaded into THO — TLO. |
master, the € 8 52594 sends the ID of the interrup | AS
ting slave device onto the cas2-cas0. 8 P1.5 is toggled for the high and low portions of the pulse.
The slave th us selected will send its pre-programmed subroutine oe
address on to the _ a

using the timer is called.

data b us duriing the next | one or two successive IN 3
- 4 The DELAY subroutine
TA- pulses the “SETB TRO” instruction.
rs aio ;

by
—

0 is started
<4, a

‘Timer
ee

8259 intemal block diagram

«~ i, o |
5 In the DELAY subroutine, is provided by. the crystal
which
; a

, e passing of ea ch cl oc k,
1. Timer 0 counts up with th th e st at es of FF F3 , FFF4, FFFS,
ts up, it goes th ro ug h
oscillator. As the timer coun
-_-_

on ti l it re ac he s FF FFH. One
DO-D7<=>] Data bus | ve ou
, FF FS 8, FF F9 , FF FA , FF FB, and so un
buffer | FFF6, FFF7 th e JN B instruction
| :Wi : Control lo = in g th e ti me r flag (TFO = 1). At th at po in t,
; ? ae more clock roll s it to 0, ra is
falls through. e D E L A Y su br ou ti ne ends,
by th e ‘n st ru ct io n “ C LR TRO’. Th
ae write /
Read : es t inves
2. Timer 0 is stop ped
ated.
and the process 18 repe s and
—
, pees Prionity Interrupt
oon IRO
<-IRI TL an d T H re gi st er
a <=> |resolver|<==|request e pr oc es s, we m u s t reload the
th
Notice that to repeat
|:
3 R) register |:
:: cole
(RR) start the timer again.
| <= IR7 ‘

Interrupt mask register (IMR)

 ee
26-2017 Sixth Semester, Microprocessor and Microcontro]]
er
LP. University-[B.Tech.|-AB Publisher
Q.8.(b) Explain the criterion for choosing a microcontroller Gi 2017-27
application areas of microcontroller.
© lve m
ajor
.
Application of Microcontroller in Industrial Con
trol Devices:
Ans. 1- The first criteria for choosing a Microcontroler ig "Num ‘ er ae Industrial instrumentation devices
of Bits”. if
market you will find 8-bit, 16-bit, 32-bit MCU(Micr-Controller Unit) Process control devices
Here we have to
make our choice. Mostly for hobbiest and learners,the 8-bit MC
Application of Microcontroller
in Metering & Measurement Devices:
eliminating other two will make our life much easy.
Volt Meter —
, 2- There are four “Major 8-bit MCU”. They are, Motorolla’s
Zilog’s Z8, and PIC 16X from microchip technology. Each of these M 6811, Intel’s 805] 3 | Measuring revolving objects
CU are different “ih i
their instruction set and registers are concerned, therefore they are not Current meter
each other. Program written for one will not run on the other. We hav ues © with ¢ Hand-held metering systems _
these four listed previously on the basis of the following criteri Thue from
a. Intel’s 8051 based _ Q.9. (a) Discuss in detail RAM memory space allocation in 8051. (6.5)
MCU are made by many manufacturers and are radily available
j
them are Intel itself, Atmel, Philips, AMD, Siemens, Matra, and Dall a market Among Ans. The 8051 microcontroller has a total of 128 bytes of RAM. We will discuss

———
Siemens and Intel are no more manufacturing ductors about the allocation of these 128 bytes of RAM and examine their usage as stack and

ee
MCU. The list of thess ox ue es along
pani register.

——
with their websites is given at the end.
RAM Memory Space Allocation in 8051

_
it; for some people this might be unnece Py

ssary but i think fo

ene
to spend too many dollars for r beginners | : ; | The 128 bytes of RAM inside the 8051 are assigned the address 00 to 7FH. They
same System when you can make it with a si ngle Making the __ can be accessed directly as memory locations and are divided into three different groups
dollar?. So, price conside rat |
important. You can consult your local mar ket ion is very Ls -as follows —
for this purpose, but in
¢ 32 bytes from 00H to 1FH locations are set aside for register banks and the
stack.
read/write
e 16 bytes from 20H to 2FH locations are set aside for bit-addressable
memory.
write storage; it is
° 80 bytes from 30H to 7FH locations are used for read and
Cre -

_4- Availibility in Market; so far we ‘ane used for the purpose of

which MCU are avail
choose MCU from Atmel called as scratch pad. These 80 locations RAM are widely
able in m —
pu ve have » see storing data and parameters by 8051 programmers.
age |
are available.
AT89C51 3c rn RAM memory space allocation in the 8051
heck
I pic ked Atmel’ s
Huotisia chet Risk wc ae
<i oe, va
oS

can choose any MCU from AT8951 series. But do

> ou 4
ae
{2 en
, aa 4 “4
3 ON 4a

7FH
cm Scratch pad RAM

Bit-Addressable RAM

Register Bank 3
=| Register Bank 2
—— (Stack) Register Bank 1
Register Bank 0
* Light sensing & controll
ing devices A
Temperature Sensing
‘
and controlli ng devi
ces
\ -

Fire detection & Safe

ty devices | Register Banks in 8051 st er ba nk s and the stack. These
Industrial instrumen t e s of R A M ar e set as id e for the regi
tation devices | A total of 32 by fo ur re gis te r b a n k s in w h i c h each bank has 8 registers, RO-R7.
is RA M lo cation
Process control device are di vi de d in to O-R7 w h e r e R 0
s 39 bytes
e se t as id e fo r b a nk 0 of R
oe aa from 0 to 7 ar
 98-9017 ‘Sixth Semester, Microprocessor
and Microcontroller L.P. University-[B.Tech.|-AB
Publisher
0, Rl is RAM location 1, R2 is location 2, and so on, until th © me
mory location ts +i dh; CJNE@RI1,#data,reladdr 0xB7
2017-29

belongs to R7 of bank 0. CJNE RO0,#data,reladdr

wo w

6
0OxB8

wWwwwwmww
The second bank of registers RO—-R7 starts at RAM location | ae CJNE R1,#data,reladdr
08 and go 0xB9

' 2:
OFH. The third bank of RO-R7 starts at memory location 10H
and Seeee 7 = tions o CJNE R2,#data,reladdr 0xBA
17H. Finally, RAM locations 18H to 1FH are set aside for the
fourt h bank ° ofoca
ROe-R7”

A
CJNE R3,#data,reladdr 0xBB
Default Register Bank
CJNE R4,#data,reladdr OxBC
If RAM locations 00-1F are set aside for the four re

Oe
ister CJNE R5,#data,reladdr
bank of RO-R7 do we have access to when the 8051 is Seno a he ich Tegister 0xBD
register bank 0; that is, RAM locations from 0 to 7 are accessed ith th CJNE R6,#data,reladdr OxBE

Oa
© answer jg
R7 when programming the 8051. Because it is much
easier to refer thes RAM rot CJNE R7,#data,reladdr OxBF a | C
by names such as RO to R7, rather than by their mem or
y locations, eae locationg . Description: CJNE compares the value of operand1 and operand? and branches to
How to Switch Register Banks the indicated relative address if operand and operand2 are not equal. If the two
operands are equal program flow continues with the instruction following the CJNE
instruction. l
desired register bank, since they can be accessed by the bit addicts 3 oe
HBG ss | eee cn soweewers
ae h CLR. For example, “SETB PSW.3” will set PSW.3 = 1 and select tie - a ee Q. Gi) CPLA
ae te ee

earn : © Dank = ae Ans.

: ae Pe ed | Operation: CPL
oe (PSW.3) ea ne Function: Complement Register
Bank 0 0. ; 0 e a Syntax: CPL operand
Bank 1 0 ] ATES oes SS ve Instructions OpCode Bytes Flags
Bank2 1 =a cee CPLA OxF4 1 None
Bank 3 1 i a
2 ‘ C
CPL | OxB3 | Fk €
| aes CPL bitaddr 0xB2 2. None
=
Explain folloOwin
Q.9.(b)ns
cia ee nea
wing g ; instruct 3 , oe Si | Description: CPL complements operand, leaving the result in operand. If operand is
ions of 8051 with example... (6) : a single aed the state of the bit will be reversed. If operand is the Accumulator then

Ans sw oe all the bits in the Accumulator will be reversed. This can be thought of as “Accumulator
Ee ae oe _ Logical Exclusive OR 255” or as “955-Accumulator.” If the operand refers toa bit of an
Operation: | SWAP ; : - output Port, the value that will be complemented is based on the last value written to
a Swap Accumulator - “Nibbles that bit, not the last vate read from it.
yntax: SWAP A = Q. (iv) ANL destination, source .

aoe OpCode Bytes Flags - | ae Ans.

oo None ee = a Operation: ANL
; oe
€scription: S\ ae . t ae ; es
ACCU eter This Ea pit oe f the Accumulator with bits 4-7 of the Function: Bitwise AND
Q.Q. (ii)
(ii) cCINE destinat
paigeion, Sour
rae ia ce,aces labe] exec
__uting “RR A” or “RLA” four
M time
E s. Syntax: 2 ANL operandl, | oper
= and2
ars3 3 as MEE
CINE BSH | i —_ Instructions OpCode Bytes ass
: se ; Zee a es TL iram addr,A 0x52 2 —
. ; eS one
z sags and JumpIf Not Equal / 5 : ANL iram addr,#data | 0x53 } q ee
‘uctions aye operand operand? reladdr | ) ANL A,#data
CINW A c:.. OpCode Byteses «BY ABS | ANL A,iram addr
Onda
be
: None
UNE A,#tdata,reladdr 0 S 1 None
NE Aram addr,reladdr 0xB5 ae dS |
CINEROAdatareladdr Ovpg 83 5 | .
$

-
7

"
a_
5

4
=)

:
+p
.
ae
. a

e
ae
»
Py
i

rae
Se)
at
ge
S

Pig 7
' « me
hie’
 80+2017 Sixth Semester, Microprocessor and Microcontro]ley

ANL A,@R1 0x57 1 None

ANL A,RO 0x58 1 None
ANL A,R1 0x59 I None
ANL A,R2 Ox5A 1 None
ANL A,R3 0x5B ! None
ANL A,R4 0x5C 1 None
ANL A,R5 0x5D 1 None
ANL A,R6 0x5E 1 None
ANL A,R7 Ox5F 1 None
ANL C,bit addr 0x82 2 | C
ANL C,/bit addr 0xBO 2 C
Description: ANL does a bitwise “AND” operation between operand]
and operg
leaving the resulting value in operand1. The value of nd2,
operand? is not affected. A |o
“AND” compares the bits of each operand and sets the
corresponding bit in the reg i c a l
byte only if the bit was set in both of the original operands ulting
, ot he rwise the resultin
cleared. ) £ bit is
|

-
s
tas
 FIRST TERM EXAMINATION [FEB. 2018]
_.__
ra SIXTH SEMESTER [B.TECH]
_ MICROPROCESSOR AND MICROCONTROLLER
[ETEE-310]
Time: 1%hrs. M.M. : 30
+ Note: Q.No.1 which is compulsory. Attempt any two questions from the rest.
Q.1. (a) Write the instructions to move value 5FH in memory location 3000H
using indirect addressing mode in 8085 microprocessor. (2)
Ans. LXI H, 3000H
MVI A, 5FH
MOV M,A
HLT | : |
Q. 1. (b) Explain the concept of segmented memory in 8086? | (2)
Ans. Memory Segmentation in 8086 Microprocessor .
| Segmentation is the process in which the main memory of the computer is divided
_ | into different segments and each segment has its own base address. It is basically used
_ | to enhance the speed of execution of the computer system, so that processor is able to
| fetch and execute the data from the memory easily and fast.
- The Bus Interface Unit (BIU) contains four 16 bit special purpose registers
_} (mentioned below) called as Segment Registers. |
i \ Code segment register (CS): is used for addressing memory location in the code
- | segment of the memory, where the executable program is stored.
: Data segment register (DS): points to the data segment of the memory where
+= | the data is stored. | es
a Extra Segment Register (ES): also refers to a segment in the memory which is
en
“
LF
{dee

, =
an

»
:
i cP
x

other data segment in the memory.

Stack Segment Register (SS): is used for addressing stack segment of the
-mory, The stack segment is that segment of memory which is used to store stack

_Q. 1. (c) Explain the function of ALE pin of 8085. (2)

Ans. ALE-Addres latch enable signal. This is used to demultiplex (latch) the (LSB)
, ™42ress and data when it goes high. |
Q.1. (d) What is wrong with MOV 1000H, BX instruction? sae
Ans. In this example destination is a data value, which can’t be possible.
Correct answer: MOV [1000], BX
| re or
a
— MOV 1000, [BX]
st ru ct io n wi th ex am pl e. } (2)
Q. 1. (e) Explain SCASB in
on is use d for sea rch ing a par tic ula r charac ter or set of
| ; SCAS instructi
‘A pee 8 a string. The data item to be searched should be in AL (for SCASB), AX
| (for SCASW) or EAX (for SCASD) registers. The string to be searched should be in memory
ES:DI (o r ED I) re gi st er . Be
) and pointed by the . (1 )
Y pi n in 80 85
Q. 1. (f) Excpiais the function of READ it e cy cl e
ed to de la y the mi cr op ro ce ss or Re ad or wr
s. Re ady- Th is si gn al 1s us
. An : lis ready to send or accept data.
untill a slow responding periphera! } ye diagram of MVIA, 32H instruction. (5)
ee i.
Q. 2. (a) Draw and explain the timin H. As sh ow n 1n Fi g. , the in
aOre VI A, 32
‘
imiing) Dine
en Tiss - ele is OpCode fetch. It takes 4 Tapes 4 clock
(#4 me mo ry re ad wh ic h ta ke s
ri od s) Wi e a o a ma ch in e evi.
| Pe
| Qstruction cycle takes 7 ‘T-stavcs. |
 roller
2-—2018 Sixth Semester, Microprocessor And Microcont
I.P. University-[B.Tech]-Akash Books 2018-3
M, (Opcode fetch) M, (Memory read) sa ASSUME Directive-The ASSUME directive is used to tell the assembler that the

“LLL ae
T, Tt Ts T, qT; oe he. Ts <n name of the logical segment should be used for a specified segment. The 8086 works
directly with only 4 physical segments: a Code segment, a data segment, a stack segment,
and an extra segment. |
Example: ASUME CS: CODE; This tells the assembler that the logical segment
named CODE contains the instruction statements for the program and should be treated
as a code segment.
Junspeciiep 20H memdyHigh-order
address |. q
ASUME DS: DATA; This tells the assembler ti.at for any instruction which refers
Low-Order Low-Order to a data in the data segment, data will found in the logical segment DATA.
EQU Directive: The EQU directive is used to give name to some value or symbol.
‘ OOH ==( SEH Opcoda-+--<-<== ' --+439Hidata oi
AD Kach time the assembler finds the given names in the program, it will replace the name
____ | Memory addres Memory address ; with the value or a symbol. The value can be in the range 0 through 65535 and it can be
another Equate declared anywhere above or below.
The following operators can also be used to declare an Equate:
THIS BYTE
M
Y Status 1D/M =0. [S,& S, ‘Opcode lO/M = S,|& S,= Status line THIS WORD

‘ Th Aes
S. “= $Slatus Tine fetch THIS DWORD
A variable-declared with a DB, DW, or DD directive — has an address and has space
reserved at that address for it in the .COM file. But an Equate does not have an address
1 D
or space reserved for it in the .COM file.
Example:
Here is description of what happens in the system bus until the instruction MVI A-— Byte EQU THIS BYTE
32H is executed (again I will explain a generic microprocessor rather than 8085): | DB 10
= The Program Counter loads the memory address 2000H into the address bi A_ word EQU THIS WORD
during T1 of the Op. Code machine cycle. . 3 = _ DW 1000 |
* The address decoding system locates and identifies the memory location A_ dword EQU THIS DWORD
20008
* At T2, the Timing and Control unit produces the MEMR-signal (Read) which las DD 4294967295
during T2 and T3. During this window of time the memory places the Opcode 3EH fror g Buffer Size EQU 1024
location 2000H into the data bus. | ae Buffer DB 1024 DUP (0)
* The operating system places the Opcode in the Iastruction Register then into tht
Buffed_ ptr EQU $ ; actually points to the next byte after the 1024th byte in buffer. .
Instruction Decoder. When the Instruction Decoder decodes the Opcode it feeds thy
decode d signal into the Timing and Control Unit. The fetch operation is completedit Q. 3. (a) Explain all the addressing modes of 8086 with suitable example. (5)
73 Ans. Addressing modes: The method by which address of source of data is given
* The Program Counter is incremented to 2001H. alongwith instruction is called as addressing mode of source. -
¢ During T4, the Timing and Control unit finds out that a second byte which contains 1. Immediate addressing mode (IAM): If 8/16 bit data required for executing the
| instruction
is given alongwith the instruction, then it is called immediate addressing mode.
the data needs to be read (i.e. address 2001H).
* The second machine cycle is Memory Read cycle. - Example: 1.MOVAL, 75H
. 2. MOV BX, 7506 H; 7506 H > BH BL
* At the T1 of the 2nd machine evc] aitthe :
address 2001
Sta A Ans tine yele the Program Counter loads 2. Direct addressing mode (DAM): If 8/16 bit data is present in memory and 16
bit E.A. of this memory location is given alongwith the instruction, then it is called direct
* The address decoding system locates and identifies the memory location 2001H. ; addressing mode instructions.
* At T2 the Timing and contro] oa ° ‘

and T3. During this window of tim unit produces MF'MR signal which lasts during T
it
Example: MOV AL, [9106H]
the MPU. ie the data 32H is placed into the data bus then int : 3. Register direct addressing mode (RDAM): If 8/16 bit data required for
* During the rest of T3, the executing the instruction, is present in register and the name of register is given
data 32H is stored into the accumulator.
Q. 2. (b) Explain: DB alongwith the instruction, then it is called RDAM instruction.
»ASSUME and EQU assembler directives with examples:

Ans. DB-The DB
a
dir ective
sa (5)
Example: MOV CX, BX
4. Register indirect addressing mode (RIAM): If the data is present in memory
is used to declare a BYTE -2-BYTE variable
“is made up of 8 bits. -A BYTE and the E.A. is present in a register, then it is called RIAM instruction.
Declaration examples: KA=(BXJASU/ADI) ~
Bytel DB 10h | | Example: MOV CX, BX
Byte2 DB 255 ; OF Fh, the max. possible for a BYTE 5. Register relative addressing mode (RRAM): Data is present in memory
CRLF DB 0Dh, 0Ah, 24h; Carriage Return, terminator BYTE ocation and the EA = [BX){BPV[SI/[DI + 8/6 bit displacement.
Example: MOV CX, 97H [BP]
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, -
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ie 5 -
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Ah
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ie Ie
9
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- a 5

4—2018 Sixth Semester, Microprocessor And Microcontroller et

5 3es

= a bee en enone mode (BIAM): Data 1s present in memory Iecation and i

‘

I.P. University-(B.Tech|-Akash Books - 2018-5

e KA= a
Example: MOV CX, [BX] [SI] ae The 8085 has five hardware interrupts
7. Relative base index addressing mode (RBIAM): EA. = [BX)/[BP] + [ST] (DY) “ (1) TRAP (2) RST 7.5 (3) RST 6.5 (4) RST 5.5 (5) INTR
+ 8/16 bit displacement a Me
Example: MOV AH, 1907H [BX][DI] oes es Oo Geter
MOV DX, SAH[BP][SI] is used the relative base,index addressing mode. eee —
8. Implicit addressing mode (IPAM): If address of source of data as well as addre ae RST6.5 00347
of destination of result, are fixed then no operand is given alongwith the instruction _ a RST5.5 | _002CH
Example: CLD, DAA, STD es Be TRAP 0024H
Q. 3. (b) Explain different interrupts of 8085 and their vectored locations_ TRAP:
What is a non-maskable interrupt? (5)
Ans. Interrupt Structure in 8085. | oh ae This interrupt is a non-maskable interrupt. It is unaffected by any mask or
interrupt enable.
* Interrupt is signals send by an external device to the processor, to request the oe
processor to perform a particular task or work. ¢ TRAP has the highest priority and vectored interrupt.
Sea a
* Mainly in the microprocessor based system the interrupts are used for da ee ¢ TRAP interrupt is edge and level triggered. This means that the TRAP must go
OF- Gate high and remain high until it is acknowledged. ae
transfer between the peripheral
; and the microprocessor. | : ee ae ¢ In sudden power failure, it executes a ISR and send the data from main memory
; * The processor will check the interrupts always at the 2nd T-state
of last machine: nwtae
Pee SE

*
*
1s
to backup memory.
at ee
F at ad
¢ The signal, which overrides the TRAP, is HOLD signal. (i.e., If the processor
*If there is any interrupt it accept the interrupt and send the INTA (acti ene
Me eae

receives HOLD and TRAP at the same time then HOLD is recognized first and then
nl
Hf /

signal to the peripheral. , P ac ee

»

TRAP is recognized). | |
* The vectored address of particular interrupt is stored in program counter. —_— ¢ There are two ways to clear TRAP interrupt.
¢ The processor executes an interrupt service routine (ISR) addressed
in program ae 1. By resetting microprocessor (External signal)
counter. . Ax | | Oe
~

2. By giving a high TRAP ACKNOWLEDGE (Internal signal)

* It returned to main program by RET instruction.
RST 7.5: The RST 7.5 interrupt is a maskable interrupt.
Types of Interrupts: It supports two types of interr
upts. ¢ It has the second highest priority.
. Hardware ° Software _ © It is edge sensitive. ie. Input goes to high and no need to maintain high state until
Software interrupts: it recognized.
i
. The software interrupts 3G Eee
are program instructions. These instructions Lf Po eae ¢ Maskable interrupt. It is disabled by,
at desired locations in a program. areinserted
| | | ar 1. DI instruction; 2. System or processor reset; 3. After reorganization of interrupt;
= cae 8085 has eight software interrupts from RST 0 to RST 7. The vector aicodn ‘4 . | -¢ Enabled by EI instruction.
or these interrupts can be calculated as follows 5 ae a RST 6.5 and 5.5:
e
heap number * 8 = vector address ¢ The RST 6.5 and RST 5.5 both are level triggered. . i.e. Input goes to high and stay
or RST 5,5 * 8 = 40 = 28H high until it recognized. .
* Vector address for interrupt RS o%
T 5 is 0028H ¢ Maskable interrupt. It is disabled by,
The Table shows the vector addresses ofall
interrupts. 1. DI, SIM instruction; 2. System or processor reset; 3. After reorganization of interrupt.
* Enabled by EI instruction.
interrupt | Vector address] e a _ « The RST 6.5 has the third priority whereas RST 5.5 has the fourth priority.
RSTO 0000H ~ a ~ INTR: ae
RST 1 0008H | * INTR is a maskable interrupt. It is disabled by, | e
| RST 2 0010H ce RAGS SIM instruction; 2. System or processor reset. ; 3. After reorganization of

: BST e | 0018H : _ ¢ Enabled by EI instruction. i

ae | RST4 0020H 2 ¢ Non- vectored interrupt. After receiving INTA (active low) signal, it has to supply
ermee ~ RST5 — 0028H the acne of Sua ee .
ernie aro er Re | RST 3 2 ¢ It has lowest priority. ? : a
Be rag ss ts, a RST : DPBF ‘ Ye ° It isa level sensitive interrupts. i.e. Input goes to high and it is necessary to
pe see Sa eee 7 0038H ee ~ maintain high state until it recognized. |
ei Hardware interrupts: © | | Mh dope ¢ The following sequence of events occurs when INTR signal goes high.
_ -—-—s * An external device initiates the hardware interrupts and placing an appropriate P 1. The 8085 checks the status of INTR signal during execution of each instruction.
| 1fthoi : i Bs he | ) 2. If INTR signal is high, then 8085 complete its current instruction and sends
ee St Ifthe interrupt is accepted then the processor executes an interrupt service routine, active low interrupt acknowledge signal, if the interrupt is enab
led.
 h Se me st er , M icr opr oce sso r An d Mi crocontroller
6=2018 Sixt a
I.P. University-[B.Tech|—Akash Books 2018-7
to th e ac kn ow le dge sig nal, exte rnal logic places an ingty Uction
3. In response
s. In th e case of m ultibyte instruction, additional jnt | Interrupt type | Trigger Priority | Maskable | Vector address

—
OP CO DE on th e da ta bu rrupt
ra te d b y the 8085 to transfer the addi tion 4
dg e ma ch in e cy cl es ar e ge ne
acknowle bytes TRAP Edge and level 1 No 0024H
into the microprocessor. RST 7.5 Edge gQnd Yes 003CH
808 5 sav e the ad dr es s of next ins tructi on ta 4
4. On receiving the instruction, the RST 6.5 Level grd Yes 0034H
stack and execute received instruction. |
RST 5.5 Level Ath Yes 002CH
SIM and RIM for interrupts:
i
| INTR Level 5th Yes -
© The 8085 provide additional masking facility for RST 7.5, RST 6.5 and Reps
Ny

using SIM instruction.

5| Prioity Edge/Level
Vector location
D Q
a
5. 7 fas RST a) 003CH
¢ The status of these interrupts can be read by executing RIM instruction. a
cg
7.9 CLR Q' = Mask} |
¢ The masking or unmasking of RST 7.5, RST 6.5 and RST 5.5 interrupts can b 4
RST 7.5 interrupt recok Etcpepo | ; 0038H
performed by moving an 8-bit data to accumulator and then executing SIM instriehiil a
ys RST fy

,
e The format of the 8-bit data is shown below.

*
Se * ee
eS ask
And | f 0030H
Be Bs 6De PDs sDypD5. 47D; Do

—
RST diana 002CH
4 ee Pakee

SOD/SDE}] X |R7:5|MSE|M7.5|M6.5|M5.5
a2 frase 0028H
0024H

= Available —
Serial output data<— | —® RST 5.5 mask pol > TRAP

1 = mixed
Serial data enable \_____» R EK 0020H
if, SDE=1, bitD———_ Don't Se Rese? oy To ude Getet RST 0018H
is send to SOD line care ®RST 7-5mask 5it Pabe INTR
Any recognised
interrupt
hierdie
enable FF fea) 00 a
0010H
9008H
if SDE = 0, bit D, is —> Mask set enable~
ignored If, MSE = 0, Do. D, ans 0000H
and D, are ignored if. — .
Q. 4. (a) Write an assembly language program to gener ate Fibonacci series
MSE. 1, mask Js set.
upto first ten terms using 8085 instructions. (5)
>» Reset RST 7.5
FR7.5=1:RSTZ Ans. MVI D, COUNT ; Initialize counter
is not allowed. MVIB, 00 ; Initialize variable to store previous number
lfR 7.5 = 0: RST 7. MVI C, 01 ; Initialize variable to store current number
is allowed. MOV A, B; [Add two numbers] — |
Fig. Format of 8-bit data to be loaded in accumulator in accumulator
BACK: ADD C ; [Add two numbers]
_ before executing sim instruction MOV B, C ; Current number is now previous number
: The status of pending interrupts can be read from accumulator after executia
al MOV C, A; Save result as a new current number
RIM instruction: DER D; Decrement count
* When RIM instruction is executed an 8-bit data is loaded in acc
umulator, which _JNZ BACK ; if count 0 go to BACK
can be interpreted as shown in fig. HLT ; Stop.-
Q. 4. (b) Write an assembly language program to find square of a 16-bit
Ds D, D; D, D, Do number stored at location 2000H of data segment. Also store the result
at location
3000H. (5)
SID 17.5 16.5 15.5 lE M7.5 M6.5 M 5.5
Ans. LXI H, 2200H : Initialize lookup table pointer
~
_LXI D, 2000H : Initialize source memory pointer |
|. Mask status off
Serial Input Data <—
TPeRSTSS LXI B, 3000H : Initialize destination memory pointer
= Unmarked

BACK: LDAX D : Get the number

= Marked

f Interrupt pending Lesion d Mask status of

MOV L, A:A point to the square
nterrupt is not pending

Status of RST 7.5 RST 6.5

Interrupt pending

Interrupt pending
_» Mask status of MOV A, M : Get the square
RST 7.5 j
STAX B : Store the result at destination mem ory location
Dit

Status of RST 6.5. L___, Interrupt

r Oo
1 interrupts are enab -
| Interrupt pending Enable Flag [9 = Interrupts are disab | INX D : Increment source memory pointer
| status of RST5.5 *— INX B : Increment destination memory pointer
MOVA, C CPI 05H : Check for last number
JNZ BACK : If not repeat
HLT : Terminate program execution
 I.P. University-[B.Tech]-Akash Books
2018-9
END TERM EXAMINATION [MAY-JUNE 201
| _ Explanation - Registers A,
D, E, H,L , C are used for general purpose:
8 o 7 1. MOV is used to ranstier the data from
SIXTH SEMESTER [B.TECH] |
; a 2. LXI is ‘are bad Mae acta aes ee Byte
MICROPROCESSOR AND MICROCONTROLLER 4 se ee i ie gh
[ETEE-3 1 0] C a immediately into any of registers (2 Byte)
. 4. STAX is used to store accumulator int
Time :3 hrs.
o re ister pair indirectly (3 B
MM oh le 3 instruction) e ~ - a
Note: Attempt five questions in all including Q. no. 1 which is compulsory, Se leet Gia ae : — is a to decrease register by 1 (1 Byte instruction)
from each unit. Assume missing data if any. | fon - INX is used to increase register pair by 1 (1 Byte instruction)
ae 7
-. JNZ is used to jump if not zero to given memory location (3
Byte instruction)
8. HLT is used to halt the program
6 Geis}
Q. 1. (b) Which addressing mode in 8085 moves a byte (or a word) betw
yte een
a memory location and a register? Also give an example of this type of addressi
ng.
Input Data 05 | 04 03 02 01 Ans. : (i) Direct addr
, essing mode |
Memory Address [>| 2504 | 2503 | 2502] 2501| 2500! outs
| 7 (ii)Register indirect addressing mode

Moved Data » | 3 ‘ ae Q. 1. (c) Write a program to generate a delay of 1 milli-second in 8086

|
wou ee | oe microprocessor. | (3)
= ee care - | . ; . 2 | 4 Ans. Generate a delay of ms in 8086 microprocessor
(let frequency 10MHz)
:
Memory Address [>| 2604 | 2603 | 2602| 2601 | :2600 ee:
4
Program T-states
MOVCX, COUNT P
ee
orir = | = e Se
4ie BACK: DEC CX 2
1. Load register pair H-L with the address 5000H
. NOP
2 Load register pair D-E with the address 8000H g
3
JNZ BACK 16/4
3 Move the content at memory location into accumulator
- RET
4 Store the content of accumulator into memory 2
pointed by D-E -Number of clock cycles for the execution of loop once (m): 2 +3+16 = 21
5. Increment value of register pair H-L and D-E by. Te:
6 Sa 4 DY. Z Time required for execution o loop once: m*T = 21* 0.1us = 2.1ps
. Decrements value of register C by 1
Count = td/(m*T)
7. If zero flag not equal to 1, go to step 3
8.o> Stop ue
a
a
= 1Ims/2.1s
= 476 = 01DCH = peas
__Program - | , Es hee : - By loading 01DCH in CX register, the time taken to execute the delay program is
[ MEMORY | MNEMON os e an approximately lms. :
es — = ee oe ERANDS oe COMMENT pv aoe A : Q. 1. (d) How does an 8086 microprocessor recognize an NMI interrupt?
ne
LXI H,
Oe
5000
sls 3; [H-L]
(Cleee 5000
06 aa _ Ans. In computing,
| _)
a non-maskable
interrupt (NMI is a hardware interrupt that
LXI ~ D. 8000 nimi es ‘4 standard interrupt-masking techniques in the system cannot ignore. It typically occurs
7 LD-E] <- 8000 : to signal attention for non-recoverable hardware errors. An NMI is often used when
‘MOV A,M [A] <- [[H-L]] 4 response time is critical or when an interrupt should never be disabled during normal
_STAX : Dz “TAS [(D-E]] ) 4 system operation. Such uses include reporting non-recoverable hardware errors, system
‘INX _ H [HL] is reas | debugging and profiling, and handling of special cases like system resets. |
INK: — D | [D-F — is ‘| NMI (Non Maskable Interrupt) — It is a single pin non maskable hardware interrupt
CaN. n Legit Ps (DE #1 - which cannot be disabled. It is the highest priority interrupt in 8086 microprocessor.
zs ei ale e's [Cj yt 7 After its execution, this interrupt generates a TYPE 2 interrupt. IP is loaded from word
location 00008 H and CS is loaded from the word location 0000A H.
co
eel. ONZ 2008 = |dJumpifnot zero to 2008 | |
te. MILT itor , — = Stop 3 4 | |
 roller
10-2018 Sixth Semester, Microprocessor And Microcont
fe at ur es of the programmable interrap, I.P. University-[B.Tech]}~Akash Books 2018-11
Q. 1. (e) Write the di ff er en t
a a
controller (8259). Q. 1. (g) What are the classes of control transfer instruction used in 8051
microcontroller?
Ans. Features of 8259(PIC) (3)
ubed to implemenent Ans. Branch Instructions
1. Itis a LSI chip which manages 8 levels of interrupts i.e. it is : There are two kinds of branch instructions: Unconditional jjump instructions: upon
8 level interrupt system s.
| their execution a jump to a new location from where the program continues execution is
be ca sc ad ed in a mas ter sla ve con fig ura tio n to han dle UP, to 64 lev els
2. It can SS " executed. Conditional jump instructions: a jump to a new program location is executed
|
interrupts. only if a specified condition is met. Otherwise. the program normally proceeds with the
. Ss
8. Itcan identify the interrupting device. e any extemal 4 next instruction.
req ues ts 1.e. it doe s not req uir
4. Itcan resolve the priority of interrupt a
BRANCH INSTRUCTIONS
priority resolver. Mnemonic Description Byte Cycle
various pri ority mo de s stich as fix ed pri ori ty and rot sting fi
5. Itcan be operated in
priority. yw ‘n
ACALL addr11 Absolute subroutine call 2 6
LCALL addr16 Long subroutine call 3 6
7p

6. ‘The interrupt requests are individually mask-able. RET Returns from subroutine 1 4
7. The operating modes and masks may be dynamically changed by the software RETI Returns from interrupt subroutine 1 4
at any time during execution of programs. AJMP addr1il Absolute jump 2 3
8. Itaccepts requests from the peripherals, determines priority of incoming
i request :# LJMP addr16 Long jump | 3
checks whether the incoming request has a higher priority value than the level SJMP rel Short jump (from —128 to +127 2 3
currently being serviced and issues an interrupt signal to the microprocessOm locations relative to the following
9. It provides 8 bit vector number as an interrupt information. instruction) 3
10. It does not require clock signal. JC rel Jump if carry flag is set. - 2 3
11. It can be used in polled as well as interrupt modes. Short jump.
JNC rel Jump if carry flag is not set. a. 3
12. The starting address of vector number is programmable.
3 Short jump.
13. It can be used in buffered mode. JB bit,rel Jump if direct bit is set. 3 : 4
Q. 1. () Compare the merits and demerits of asynchronous communication 3 7 Short jump.
with sychronous communication. | , a JBC bit,rel Jump if direct bit is set and clears 3 4
Ans. Asynchronous Communication | | | bit. Short jump. —
Advantages: JMP @A+DPTR Jump indirect relative to the 1 2
| DPTR | Bre
.

* Requests need not be targeted to specific server.

~ os

Jump if the accumulator is zero. pe 3

,
yous:

JZ rel
£

© Service need not be available when request) is made. , |

Short jump.
Fre

oe
'
ad j a

e 2: No blocking, so resources could be freed. 3

niet, )

Jump ifthe accumulatoris not 2

a
rt

JNZ rel
hes

=
)A

|
.

a connectionless protocol
Could use ei S STs. Sie ee at a zero. Short jump.
-
Cp
ON
at

sd Disadvantages: ; : Si iy A Sopa s a CJNE A,direct,rel | Compares direct byte to the | 3 ee

‘

IN ‘ f : ; ‘ a
vey

i
"

oe
;

accumulator and jumps if not

er.

saree ‘eae
4
E

Eo5 meee * Response times are unpredictable. — 5 Paw BE INE Se a

:
ee
ee aFl

|
at
eS

i,

is Sa EBS equal. Short jump.

i

_ Error handling usually more complex. ie

ay
a age
r

3
teas

Bee
rt

=’
*
th

ry

Compares immediate data to the eS Se 4

o pope ct 1 CJNE A,#data,rel
Pe

oa en ‘Usually requires connection-oriented protocol. eee

iYS.RPhie a

~ | accumulator and jumps if not

pe

| ae
cas

ri :

,
it

epee equal. Short jump.

AAs
a!
eye

dae

raat €
=i

Compares immediate data Pe the = , 4

CJINE Rn,#data,rel
j
eee

1K
%, YS

register and jumps if not equal.

a8

|
:

x
ans

pe Mose ew | Short jump.

te
es

CJNE @Ri,#data,rel| Compares immediate data to 3 a

es
au

hee
Tarn

ts
s Abts ic Bsa adi

_| indirect register and jumps if not

iL

spas
ent

tat
Pee Ps TP
-

sn

equal. Short jump. |

|
9 (AM
ALiSsecrite Vea
ES a

DJNZ Rn,rel — Decrements register and jumps ocak 9

Mens uc pate if not0. Short jump. '
DJNZ Rx,rel - Decrements direct byte andj jump | Ba a
\ | | ifnot 0. Short jump.
NOP _ | No operation _ : : 7
 12-2018 Sixth Semester, Microprocessor And Microcontroller
< ; Li. University-[B.Tech]-Ak
ages ofmicroprogramm ash Books
Q. 1. (h) What are the advantages and disadvant 2018-13
ed
|
control and hardwired control unit. ALU: The ALU performs the computing functions. It
includes accumulator, the
Ans. Advantages of micro-programmed control unit | (3) ‘ temporary register, the arithmetic and logic circuits and five
flags. The temporary
2. Cheaper | a register is used to hold data during an arithmetic/logic operation. The result
1. Simplifies design of CU.- is stored in
y. | the accumulator, and the flag (flip-flaps) are set or reset according to the result of the
3. Less error prone to implement.
operation. The flags are affected by the arithmetic and logic operations in the ALU. In
Disadvantage of micro-programmed control unit at
most of these operations the result is stored in the accumulator The flag
1. Slower compared te hardwired control unit. a a s generally
reflect data conditions in the accumulator with some exceptions. |
Advantages of hardwired control unit | S-sign flag: If bit D, of the result is 1, the high flag is set. This flag is used with
1. Faster than micro- programmed control unit. signed numbers. |
2. Can be optimized to produce fast mode of operation. ar. ie If D,—1 (Negative number)
Disadvantages of hardwired control D, — 0 (Positive number)
pe 4
1. Instruction set control logic are directly a Z-zero flag: If result is 0, the flag is set (1) and the flag is reset if the result is not 0.
AC-Auxiliary Carry flag: If their is a carry from the bit No. D, to D,, then this AC
2. Require change in wiring if designed has to be controlled. | : ap ee flag is set.
| UNIT-I | c P-Parity Flag: If the result has an even number of Is, the flag is set.

micreprecesoer? Expisin alt Proeramniable roginteny an C,-carry flag: If an arithmetic operation results in a carry, the C 41s set, otherwise
it is reset.
Ans. Block diagram of 8085 micro Es | i DD 0. Db Bb BD, D,
SZ EXACT XEP Tx cy
>

X-don't cares.
Timing & Control Unit: This unit synchronizes all the microprocessor operations
Ke with the clock and generates the control signals necessary for communication between
the microprocessor and peripherals. The control signals are similar to a syne pulse in an
, ;
‘ae
mae he
oscilloscope. RD and WR pulses.
- _Instruction Register and Decoder: These are the part of ALU. When an instruction
is fetched from memory, it is loaded in the instruction register. The decoder decodes the
t

instruction and establishes the sequence of events to follow.

|

Register array: B, C, D, E, H, E are the general purpose register. W and Z are the
te I

_. temporary register. | a
~
.
SILC

Q. 2. (b) Explain the need to demultiplex the bus AD_-AD). (3)

ary

: Ans. The AD oAD 7 lines . Schematic diagram to latch low order address bus.
hy 2Ass

in an 8085 are multiplexed to : Dus

‘

reduce the pin count of the IC. Avs

4
~.

Raed

Aig
pve, sig

‘Several added features were Ai High-Order

ri

iz Address Bus
A

- added to the 8085 from the 08s

9

-
Na
wal

}
ie’

8080 design, and Intel did |"

¥
bus
an Groth ee.
yr

5
Mob

:
ri

As
‘
AA

not want to require a larger ae

‘

iia
}
4
3
mn Ha

;
ee me

package. -
oa

Ad, ns
Tees
-4 oe hye

Pa
. Pry
ARAB

; a4

: aSA,
a
SPS lee

Low-Order
S

bakers

~ Address Bus
.
a

A,
Ay
D>
Dg
Ds
<=

pi Data Bus
 Sixth Semester, Micro
processor And Microcon
troller
Q. 2. (c) What are the diff
: ere nt vectored j : ‘ a oe University-{B.Tech]-Akash Books 2018-15
| No condition needed if it is a plain jum
Ans. Refer to Q. 3. (b) of First Term Examination 2018 (4.5) =| check some status flags to do this jumping P instruction otherwise sometimes it can
action in memory.
Q. 3. (a) Write a pro us a Jump Instruction
numbers 3AH and ain aad to dhapiny thi uuagaces
Ge eae NC aS Sea eam ITE ero
Ans. MVI A, 3AH; Move immediate 3AH into a pile vm oe ae ) The program sequence is transferred to the memory
ADI 48H; Add immediate accumulator with 48H | es gibt —— oe a oo ena
OUT 01H; Store the result of accumulator at output port
01H . 3 ;‘le ae sas caus PE CTs mmian eageemes
HLT; Stop a | | 4 : =
7 | | 2. JC: - (conditional jump
Q. 3. (b) Explain how many times the following loop will be sseeuten: (5) 4q or a 16-bit PPO if Si Cteure ees oe
LXI B, 0007H a} Kg: - JC ABC Gump to the level abe if C=1) 3
LOOP : DCX B eos | 3 s 3. JNC:- (conditional jump) The program sequence is transferred to a particular
MOVA,B | ; Oe 4 level or a 16-bit address if C=0 (or carry is 0)
ORAC ta | a Eg: JNC ABC (jump to the level abe if C=0)
_JNZ LOOP | ; 3 = = : 4. JP: - (conditional jump) The program sequence is transferred to a particular level
Ans. 7 times | — or a 16-bit address if S=0 (or sign is 0)
Lx1IB.0007H tao | sees , : | 4 Eg: - JP ABC (jump to the level abe if S=0)

Loop: DCX B ae pose aries | eis : | 4 a 5. JM: - (conditional jump) The program sequence is transferred to a particular level
MOV A,B — Sood | eee s a Ne = ora 16-bit address if S=1 (or sign is 1)
| 7 | = ane 2385 ale Eg: - JM ABC (jump to the level abc if S=1)
PEAS 5 | a | NS i ee oe i 4 6. JZ:- (conditional jump) The program sequence is transferred to a particular level
_JNZ LOOP - o | eu es Se , ae or a 16-bit address if Z=1 (or zero flag is 0)
‘ _ Load Immediate register pair BC with 0007H | | - Eg: - JZABC Gump to the level abe if Z=1) |
| | | a = oF 3 7, JNZ: - (conditional jump) The program sequence is transferred to a particular
at DCX B - reduces the contents of BC pair Ae | ae a level or a 16-bit address if Z=0 (or zero flag is 0) ©
Z = | P20 C206. 3. cae cae - Eg: - JNZ ABC (jump-to the level abe if Z=0)
ious - MOVA, B= : se a . A-=-00 | BE ao nerare 3 é aa 8 JPE: : (conditional jump) The program sequence is transferred to a particular
7

Be - Bhit 16 bit 7 es : | = Jas pate 2s . $53 | a ~. - level or a 16-bit address if P=1 (or parity flag is 1)
=

es “ORAC-A j rc
Abot

60
Yeasts

or Te . . | ae
ba

a ~ Eg: - JPE ABC (jump to the level abc if P=1)

a particular
9 JPO:- (conditional jump) The program sequence is transferred to
- ah ao ri!it mec 4

level or a 16-bit address if P=0 (or parity flag is 0)

cingremmanntenndues

Ceo

eer aM
Se {
mine
:
aaanes

Eg: - JPO ABC (jump to the level abc if P=0)

een!
‘
:
sem,

om et

UNIT-Il
VERT
tehseiah
5
Fade

ORS Se heD, |.
ai
ee a
Va

:
Po
i

Q. 4. (a) What is the main difference between minimum and maximum mode
ER oeTe RN =

operation of 8086 microprocessor? Pe = ”

:

(2.5) = Ans. Case 1: Minimum mode configuration of 8086: If pin number 33 of 8086 is
Ree ar Nee 2
1p
re fens
5

: ; ist ful go d irectl

>
dta

"€ ‘ ly to the instruction when your conditiojs

n Satisfyor ~ eonnected to logic 1 then 8086 operates in the minimum mode. Pi :
EPA
:

ae eet ot
jump is encountered, the processors loada new address from where it 8086 will have the function as shown in the parenthesis, next to these pins.
,Rha
’
wr

J
 16-2018 Sixth Semester, Microprocessor And Microcontroller
I.P. University-(B.Tech]}-Akash Books 2018-17

“on Nad output is enabled. When DEN = 1, the transceiver output floats in tristate. So, DEN
A x |
is used to enable the transceiver. This output is active low during each memory and I/O
31+ ROGT, / oN access. |
30 {+ Rar,zt| ~ (HLDA) | we" THE MINIMUM 7. HOLD and HLDA: Both HOLD (pin 31) and HOLD acknowledge (HLDA)i.e.,
29+ LOCK| (WR pin 30 are used for DMA (Direct Memory Access). We have already discussed DMA earlier.
8086 7K epee Case 2: Maximum Mode Configuration of 8086: If pin number 33 of 8086 is
CPU +S, | : (Mid)
connected to logic 0 then the processor operates in the maximum modes. The
27-+- S, 1 (OTM) configuration is quite complex and is used for the multiprocessor systems. Herein, pins
| eS, | EN 24 to 31 have functions described outside the dotted line in Fig. 1. Like now pins 26,27
25 as, \ (ALE) _ and 28 works as Sy,5; and S, respectively. These are control bus signals.
24- as, \(INTA)
INTA)
|/
\ f To achieve maximum mode for use with external coprocessor, the MN/ MX pin must
Vio
be connected to ground. Let us see the pins of this mode now

_ Please note here that pins 24 through 31 have dual functions depanding on the mode
1. S,,S, and S, : Status bits show the function of the current bus cycle. Such.
of operation. signals are normally decoded by 8086 bus controller. Let us see ina tabular
form, their functions.
In minimum mode, for example, pin
29 acts as write. (WR)- This pin will go low
Functions

OC Of,W|
when 8086 wants to carry out a operation on memory or ports. Also note that the minimum

OoOrRrF

OCrF OC]
mode of operation is suitable for a single processor systems. Interrupt acknowledge

SHOR
OOO oO
Let us now study the signals which correspond only to minimum mode shown in I/O read
dotted lines above. I/O write
Halt
1. M/IO (Memory/IO ): In minimum mode, pin number 28 acts as Memory/OQ.
Opcode Fetch
a

ee
output line. The status of this pin indicates whether memory is being accessed or VO - Memory Read
port is being accessed by CPU. | Memory Write

HE

rr
If M/IO = 1 then CPU is accessing memory.

Be
Passive
: else if MIO =0 then CPU is accessing I/O devices.
3 2 Write WR: It is an output an number 29. If processor wants to perform a write '. 5
“ag A
2- RO/GTI and RO/GTO :The request/grant pins request DMA during maximum
mode operation. Both these lines are bidirectional and are needed to request and grant
oy
a

= operation on memeory and I/O devices then the WR pin gives low. a DMA operation.
OS | 3. INTA (Interrupt Acknowledge): It is an active low signal which is sent tit e 3. LOCK: The lock output is used to lock peripherals off the system. This pin is
fc, ae interrupting device to tell it that its interrupt requiest has been accepted. ~ a activated by using the clock prefix on any instruction.
5 ae 4. ALE (Address Latch Enable): It is an active high output line (Pin no. 24). If 4 4. QSI and QSO: The queue status bits show the states of the internal instruction
e 2 = ALE « 1, it indicates that address is present on the multiplexed address/data bus. This queue. These pins are provided to access numeric math co-processor (8087). The operation
strobe (ST B) inp uts of the ext ern al lat che s to strobe in ; a
ALE signal is connected to the of the queue status bits is in truth-table below:
: a= or latch this address into them. Qs, Qs, Function
a |= ae 5.DT/R (Data Transmit/Receive): 1 output pin of 8086 in minimum peas that 0 0 Queue is idle (NOP)
0 \ae First byte is opcodes
the direction of flow of data on the data line.
~

a2 fs _ decides
2 0 Queue is empty
: _«‘IfDT/ R = 1 then data flows out from CPU. 1 1 Subsequent byte of opcode

2 -else if DT/R = 0 then data flows into the CPU.

ere

Q. +. (b) Why is memory divided into the segments in the 8086

Ah

an a * °

microprocessor? (4)
-

6. DEN (Data Enable): It is : an output pin number 26 in the minimum mode DEN
» nh , q
A ‘ ‘
Aa
4

Ans. Advantages of the memory segmentation The main advantages of

§__isconnected to OF (output enable) input of transceiver. When DEN =0. the transceiver segmentation are as follows:
 18-2018 Sixth Semester, Microprocessor And Microcontroller

e It provides a powerful memory management mechanism. 0 iP Uist:

e Data related or stack related operations can be performed in different i ine ‘*. University-[B.Tech}-Akash Books 2018-19
“ee Ment Data-Transfer Instructions
© Code related operation can be done in separate code segmentg.
e It allows to processes to easily share data. | | ‘ ie The data-transfer functions provide the ability to move data either between its
a at

¢ Itallows to extend the address ability of the processor,

ras Ntiatsa:
i.e. segment avin eee
ee
E
The data-transfer functi
Pe ;
the use of 16 bit registers to give an adcressin
segmentation, it would require 20 bit registers.
g capability of 1 Megabyte s, ekWile
thous Mbyte or word),
segment) XLAT(Load
and LES (Translate Wisi LEAete. oatomecne
extra segment) diane) LDS (Load
address), dead date
data
aes
J

-e Itis possible to enhance the memory size of code data or stack ge BMents7
hey, Theoe LEA, LDS, 2 and LESI Anstructions — The LEA, LDS, LES instructions
; provide
64 KB by allotting more than one segment for each area. ; =a ‘ ie el ay ira eater ae addresses by loading either a 16-bit offset address
| ee - er or a register together with a segment address i
_ Physical | DSorES e.g. LEA SI, [(DI+BX+5H]} aero
- EFFEF
addressH _ Memory <= Hlghent nadie a3 a
xe Following g is the € table showi
table showing 7 of data transfer instructions:
the list :
7FFFFH - | =~ OPCODE | OPERAND EXPLANATION EXAMPLE
Extra a Mot me he MOV AX, [SI]
| , | | =2 ese rioht | | 2 oe a PUSH D pushes D to the stack PUSH DX
our segment registers : an 3
in BIU ea «. a S POP D pops the stack to D POP AS
Es} 7 1010.10 SFFFF H + Top ot saa me 6| PUSHA none put all the registers into the stack _ PUSHA
eed ag 025-010 2] | Stack ee ie POPA none gets words from the stack to all registers | POPA
SS 41.5 102] 0-1-0 3} | Segment a a XCHG D,S exchanges contents
of D and S XCHG [2050], AX
DS} 2 }|0]0 ]0 SS 50000 H <— Bottom of stack segment g IN D,S copies a byte or word from S to D IN AX, DX

a. 0d , Top of Code(at Samet a.

[OUT D,S copies a byte or word
‘
D; to S
from Be
OUT 05, AL
the upper 16 bits of the |e S ene ae eee ~4| XLAT none translates a byteinALusingatabiein | XLAT
_ Starting addresses of se aa 3 the memory
urmemory s t ole . :
that 8086 is morktag ait eae ‘ | <— Bottom of Code Segment | |LAHF none loads AH with the lower byte of the flag | LAHF
at any particular time. <~ Top of Data segments ag = Pipa register
| oe ae 7 | |SAHF none stores AH register to lower byte of the SAHF
ce = ® ee : | oe } flag register

wa 2800, <— Bottom of Data segment — PUSHF none copies the flag register at the topofthe | PUSHF
ae . Ce | stack
3 POPF none copies a word at the top of the stack POPF
te | to the flag register
DS =Q.1000
4. (c) The icontents of diff erent registers
. in 8086 are |
given by CS = a
F000H, Here D stands for ‘nati
destination and S stands for source.
Find a ee saa andES=3000H ee . 5 a D and S can either be register, data or memory address. ee
on - . address of the different segments in the memory. 7) Q. 5. (b) Write an 8086 assembly language program to find the factorial of
FO00H re BIVEN the question contents of different _ the given byte of data using a recursive algorithm. 7 (6.5)
, DS register = 1000H, SS reo; “rent registers in 8086 are CS register = .
Me Riis -eiaas ee re register = 2000H & ES r egister = 3000H “Ans. Program —
be ae:
in the memory, so both will - registers ee
be aeis used to store the base address; of different segments ADDRESS | MNEMONICS COMMENTS
CS memory et mina | Saree Bh 0400 MOV CX, [0500] ! CX <- [0500]
[Jer . = ’ D a : :
3 _ =2000H, & ES memory segment = on Segment = 1000H, SS memory segment | 0404 MON-AE; 0001 | Ae <= 0001
ae : Q. 5. (a) Explain the di ae ao 2 : Sg / eens i ~ 0407 MOV DX, 0000 DX <- 0000
examples for each. aifs ransfer instructions in 8086 giving | 040A = MULCK 3 DEAR S AK CE

a 0410 _| MOV [0600}, AX [0600]<-AX

0414 -~ MOV(0601],DX (0601]<-DX
0418 | HLT : Stop Execution
Va:
 20-2018 Sixth Semester, Mic
roprocessor And Micr
ocontroller
Explanation -—
I. MOV cx, [0500]
loads 050 0 Memory lo
2. MOV AX, 0001 cation content to CX Re
loads AX register wi gister
th 0001© 2018-21
MOV Dx, 0000 loads
wh r
4. MUL Cx D; Dg D;
X and store resultj if DX: D
59. LOOP 040A runs loop AX pair
till CX not equal to Zero
6 : MOV [0600], AX
store AX re gister conten t to memory location 06
1 ; GA
00 mode PA PCu | GBmode| pp
7. MOV [0601], DX store DX re PC,
gister con tent to memor
y location 0601 5
HLT stops the execution of program
.

UNIT-III Always 1 for Group Amode Group A GroupA Group B

//O mode selection bit PortA Port Cu tied Ponte g
Q. 6. (a) How can 8255 be made to work inh 00-Mode 1 Bode L;
input mode and output mode separately.
andshaking mode? Specify the } Re poet eet input | Potnput
01-Mode 2 } 0-Output} [0-Output} |0-Mode 0 0-Output| | 0-Output
Ans. Handshaking refers to the process of comm (8) 1X-Mode 3 1-Mode 1
unicating back and forth betw een
two Intelligent devices. PCu-Port C upper
* 8255 handles handshaking signals a powerful built in 8255 Control Word For I/O mode PC,-Port C lower
features of the 8255.
e Printers are good example for a device with handshaking capabilit I/O Control Word Format
ies,- D, D,, D3, D, are assigned for port C lower, port B, port C upper and port A
respectively. When ‘ieee bits are 1, the corresponding port acts as an input port. For
8255 Printer e.g., if Dy) = D, = 1, then lower port C and portA act as input ports. If these bits are 0,
7
cr
then the convea ponding port acts as an output port. For e.g., if D,= D,= 0, then port B and

Pe pcb, upper port C act as output ports.

¢ D, is used for mode selection of Group B (port B and lower port C). When D, =0,
mode 0 is séleeted and when D, = 1, mode 1 is selected.
° D, & D, are used for mode selection of Group A( port Aand upper port C). The
selection is done as follows:
i D, Mode
s itee

‘| Ppc7 -_& “>| STROBE

0
ST

0
me

0
POG 0 ers ae ey
ee

te? =
2

ACK p
ot:

e
eRe

= 1 xX
igtae er

2
wl grace

o As it is I/O mode, D, =].

a2 ma
Ve

For example, if port B and upper port C have to be initialized as sue ports and
eth Ut

paeates Handshaking Signals

See

_ lower port C and port A as output ports (all in mode 0):

je A

__—« |. Abyte of data is presented to the data bi of the printer. : a

‘1. Since it is an I/O mode, D, =1.
Fa

Se 2. The printer is informed of the eso ofa byte of data to be printed by activating
2. Mode selection bits, D,, D;, Dg are all 0 for mode 0 operation.
STROBE input signal. - 3. Port B and upper port C should operate as Input ports, hence, D,
= D, = 1.
‘8, Whenever the printer receives the dati it informs the sander by activating a 4, Port Aand lower port C should operate as Output ports, hence,
D, ==D)= =0.
t=2
- output signal called ACK (acknowledge). 4
red oper atio n, the cont rol wor d regi ster will have to be loaded
~ Hen ce, for the desi
Input/Output mode: This mode is selected when D, pit of the Control Word Registé at) with "10001010"== 8A (hex).
is 1. There are three I/O modes: \ ; xa 5

Mode 0 - simple YO .
1. Mode 0- Simple /O FPA EY Sa In this mode, the ports can be used for simple I/O operations
without handshaking
| CE pS, - ves of port C can be=
a ‘Mod1e- Strobed I/O a - Port A, port B pro vid e sim ple I/O ope ra tion . The two hal
See Ni can be use d as individual
“3 Mode 2 - Strobed Bidivortional ue. Gener as an add iti ona l 8-bi t port , or the y
e ies be used such that
the two hal ves of por t C are ind epe nde n t, the y may
Control Word format as an inp ut por t whi le the oth er hal f is ini tia lized as an output
one halfis initialized
port.
 22-2018 Sixth Semester, Microprocessor
The input/output features in mo
1. Output ports are latched.
2. Input ports are buffered, not la
3. Ports do not have handshake or
4. With 4 ports, 16 different comb
:
Latched’ : means the bits are
indeterminate.
Mode 0-input mode
. desired port using A, an
d A, lines
The
device via theCPU then issues an RD si
System data bus.
Mode 0-output mode
| In the output mode, the CP
U sends data to 8255 via sy
the external peripheral port
s receive
And Microcontro]]
er
de 0 are as follows:
I.P. University-[B.Tech|-Akash Books
2018-23
1. Two ports t.e. portA and B can be used as 8-bit i/o ports.
tched.
2. Each port uses three lines of port c as handshake signal and remaining two signals
interrupt capability.
can be used as V/o ports.
inations of I/O are
Possible. 3. Interrupt logic is.supported.
i aa
4. Input and Output data are latched.
Input Handshaking signals
1. IBF (input Buffer Full) - It is.an output indicating that the input latch contains
information.
2. STB (Strobed Input) - The strobe input loads data into the port latch, which holds
the information until it is input to the microprocessor via the IN instruction.
3. INTR (Interrupt request) - It is an output that requests an interrupt. The INTR
pin becomes a logic 1 when the STB input returns to a logic 1, and is cleared when the
data are input from the port by the microprocessor.
4, INTE (Interrupt enable) - It is neither an input nor an output; it is an internal bit
| programmed via the port PC4(port A) or PC2(port B) bit position.
- Output Handshaking signals
1. OBF (Output Buffer Full) - It is an output that goes low whenever data are
output(OUT) to the port A or port B latch. This signal is set to a logic 1 whenever the
ACK pulse returns from the external device.
2. ACK (Acknowledge)-It causes the OBF pin to return to a logic 1 level. The ACK
signal is a response from an external device, indicating that it has received the data
. a from the 82C55A port.
| a 3. INTR (Interrupt request) - It is a signal that often interrupts the microprocessor
when the external device receives the data via the signal. this pin is qualified by the
stem data b us and then
|
internal INTE(interrupt enable) bit.
ae Ag | 4. INTE (Interrupt enable) - It is neither an input nor an output; it is an internal bit
programmed to enable or disable the INTR pin. The INTE A bit is programmed using
a rl
a J

Pp by making CS low. It then selects the desired the PC6 bit and INTE B is programmed using the PC2 bit.
eal

port using A, and A, lines.

= aa 4 Mode 2-Strobed Bidirectional Input/Output mode
CPU then issues |a WR si gnal to writ; e data to th | , ie
esi a nal
Only port A can be initialized in this mode. Port A can be used for bidirectio
eight
Bg
data bus. aia.
This data is then received b>y the external : <neerees per na the systema
peripher al device connected to the handshake data transfer. This means that data can be input or output on the same
ining
lines (PAO.- PA7). Pins PC3 - PC7 are used as handshake lines for port A. The rema
alized in
Mode 1-Strobed Input/output mode pins of port C (PCO - PC2) can be used as input/output lines if group B is initi
| | = | . this mode, the
mode 0 or as handshaking for port B if group B is initialized in mode 1. In
When we mah te use port A or port B for handshake (strobed or to transfer
) input or output 8255 may be used to extend the system bus to a slave microprocessor
and handshaking
4 operation, we initialise that port in mode 1 (port A and port B can
be initilalised to | data bytes to and from a floppy disk controller. Acknowledgement
between the data
- operate in different modes, i.e., fer e.g., port Acan operate in mod signals are provided to maintain proper data flow and synchronization
e 0 and port Bin mode a 3
1). Some of the pins of port C function as handshake lines. transmitter and receiver.
(b) In wha t way is the Inte l 8253 timer differ ent from the Intel 8254
Q. 6.
For port B in this mode (irrespective of whether is acting as an input port or output (2)
timer. —
port), PCO, PC1 and PC2 pins function as handshake lines. Ans. Refer to Q. 3. (b) of End Term Examination 2016. | |
| 4
(8251)? (2.5)
| If port A is initialised as mode 1 input port, then, PC3, PC4 and PC5 function as Q. 6. (c) What is the function of data bus buffer in USART
buff er- This bloc k help s in inte rfac ing the inte rnal data bus of 8251
handshake signals. Pins PC6 and PC7 are available for use as input/output lines. a Ans. Data bus
and CPU by
- to the system databus. The data transmission is possible between 8251
The mode 1 which supports handshaking has following features: a - the data bus buffer block.
 Six th Se mest er, Mi cr op ro ce ss or An d Microcontroller
24-2018
command Ww i ae LP. University-(B.Tech]|-Akash Books
ad or wr it e st at us , V 2018-25
D,-D,: 8 bit data bu s us ed to re
ee datafrom op E
the 8251. e s s o r w i t h a c l |
0 8 6 m i c r o pro c ae be any, where between -10V to + 10V. when all the digital inputs are at logic high
will
AC to t h e 8
Q. 7. (a) Interface a D ate a ra m p w a v e f o r m o f T ook ra 7 y
wri t e pr og ra m to gener msec,
ve eh 2 zener is —_ between OUT I and OUT2 to save the DAC from
of 5 MHz an d
Ans. negative transients An operational amplifier is used as a current to voltage converter
:
INTERFACING DIGITAL TO ANALOG CONVERTERS: at the output of AD to convert the curr ent out Pp put of AD t © a proportional output
t bin ary nu mb er int o the ir equiva ler i
cu ae
The digital to analog converters con ver voltage.
Hestivan |
di
The DAC find applications in areas like gitally controlled gains, motors speed oni ee
programmable gain amplifiers etc. me ei tOV +10V
AD 7523 8-bit Multiplying DAC: This is a si on
DIP, wimu
16 pinalon g na
th
ltipl = —
i in’ analog
la dd er for D- A co nv er
conv — , containing R-2R
:
NMOS switches to connect the digital inputs to the ladder. : a i double Arown | 15 14
. |16
Res |
MSB |4 OUT 4
1 16 E
i
Paz
= = iy
OUT, —— 9 e
8255A | aS fe
' Me! mn Kale
) Pay LSB | 11 OUT2
GND sea 3
a6 V+ :
MSB B 13ae i | | Ad7523
2s oS NC

cS
AD 7523
a
5 NC
B, 6

Be 7 pens reer irean =) 5]= |

SS GND
B
~ 10t——_ B. 3
ae 6 Fig. Interfacing of Ad7523
Pin Diagram of AD 7503 |
G E N E R A T O R wi th 80 86 us in g 82 55
oe7 }
RAMP WAVE
:
One ‘Sie

MODEL SMALL
Interfacing.Analo: g to Digital pe
Converters . Data e STACK 100
e DATA |
; Co nt ro l po rt ad dr es s for 8255
CONTROL EQU OFFC6H
O F F C O H; Po rt Aa dd re ss for 8255
PORTA EQU
; Po rt B ad dr es s fo r 8255
PORTB EQU OFFC2 H
C 4 H ; Po rt Cc ga de ce e fof r 8255
PORTC EQU OFF
e CODE Pe
a
| : |
START:
‘I ni ti al iz e D a t a s e g m ent
MOV AX, @DATA;
MOV DS,AX
ee ae

3
s ; <a
Fi
ig. | , “a4

MOV DX, CONTROL

.

;
H In it ia li ze al l p a y as output
MOV AL,80
7
oe: ip ;. mr pin diagram of AD7523 is shown in fig the supply range is fro OUT DX,AL ;Ports
BL an al og eq ui va le nt to 5V
gynue may be any where between -10V to + 10V. The maximum analo me +OV to +16 MOV BL, FFE} ‘Take are
in
aiks | : & yeaa volt
926-2018 Sixth Semester, Microprocessor And Microcontroller

RAMP : MOV DX,PORTB HE: University-[B.Tec

h]-Aka sh Books 2018-27
|
MOV AL,BL ;Copy to AL Data Bus Lines, DB, - DB,
a
OUT DX.AL ;And output it on the port eased ti]] ov ee These are 8 bidirectional d ata bus
lines used to tran sfer the dat
5V is co nt in uo us ly de cr e d a t a to/fro m the CPU.
wave this is used to
DEC BL: To generate ramp CLK: The clock inpu t
generate i svi
| : microprocessor. | internal timing s required by the
JNZ RAMP ; Jump to RAMP if not 0
RESET: As the name Suggests this pin

iS
MOV BL,FFH ; To generate same wave this procedure is repeated is used to reset the microprocessor.

f
-
é
e
CS Chip Select: When this pinpin 1s; set to low, it allows read/wri

a.
JMP RAMP

=>
= ‘
read/write operations, else

=
this pin should be set to high.

ti ra
>

iS
INT 03H |

‘
rete
i -.
5
qn,

=e
A,: This pin indicates the transfer of command/status information. When it is low

«
-
a it indicates the transfer of data.

S
Q. 7.(b) Draw the functional pin diagram of keyboard and displav cani..u__ 4%

spl
play
ay at
controller RD, WR: This Read/Write pin enables the data buffer to send/receive data over the
:
(8279).
5 | (4.5) data bus. | )
Ans. 8279 pro grammable keyb oard /dis
interfaces a keyboard with the CPU. The keyboard
play cont roll er is desi gned by Intel that. IRQ: This interrupt output line goes high when there is data in the FIFO sensor
first scans the keyboard and ide fe
7| : RAM. The interrupt line goes low with each FIFO RAM read operation. However, if the
if any key has been
: pressed. It then sends thei eir relative response of the el Ae
FIFO RAM further contains any key-code entry to be read by the CPU, this pin again
the CPU and vice-a-versa. - : ee ney e
goes high to generate an interrupt to the CPU.
8279 — Pin Description
a 'q
Vg: Voc: Lhese are the ground and power supply lines of the microprocessor.
The following figure shows the pin digesta of 8279 in 2+ ial

A
Ae
. Ht »
SL, — SL,: These are the scan lines used to scan the keyboard matrix and display
the digits. These lines can be programmed as encoded or decoded, using the mode control
,
/ an ,

—
: t
~
A
Ss
Aare a B
we 5
register.
RL, — RL: These are the Return Lines which are connected to one terminal of keys,
while the other terminal of the keys is connected to the decoded scan lines. These lines
are set to 0 when any key is pressed.
in
SHIFT: The Shift input line status is stored along with every key code in FIFO
it is pulled up
the scanned keyboard mode. Till it is pulled low with a key closure,
| |
internally to keep it high
TB - CON TRO L/S TRO BED I/P Mode : In the keyb oard mode , this line is
CNTL/S
as a contr ol inpu t and stored in FIFO on a key closure. The line is a strobe line that
used
has an internal pull up.
enters the data into FIFO RAM, in the strobed input mode. It
The line is pulled down with a key closure.
for blan k disp lay. It is used to blan k the disp lay duri ng digit switching.
BD: It stan ds
- OUTB ,: Thes e are the outp ut ports for two 16x4 or
OUTA, — OUTA, and OUTB,
lay refresh regis ters. The data from thes e lines is synchronized
one 16x8 internal disp
the keyboard.
with the scan lines to scan the display and
:- Ther e are two mode s of oper atio n on 8279 — Input
Operational Modes of 8279
Mode and Output Mode.
| , %
Input Mode | e
gi ve n by th e ke yb oa rd an d thi s mo de is further
This mode deals with the input
classified into 3 modes.
 28-2018 Sixth Semester, Microprocessor And Microcontrolle
r
iP, University-
* Scanned Keyboard Mode- In this mode, the key {B.T ech]-Akash
matrix ¢ an be j inter Books
either encoded or decoded scans, In the encoded scan, an 8x8 key faceed ug 3 2018-29
Xtal
scan, a 4x8 keyboard can be interfaced. The code of key Oscillator
pre
CONTROL status is stored into the FIFO RAM. ned with =
* Scanned Sensor Matrix—In this mode, a se
d Xtal 49 To Peripherals Timer
nsor array can b e interf —» interrupt
processor using aced Wi |
either encoder or decoder scans. In the encoder vy
Serial
sca . port
or with decoder scan 4x8 sensor matrix can be int PD
erfaced. IL To
Strobed Input — In this mode, when the co | : CPU
ntrol linej S set to 0, t
return lines is stored in the FIFO he data nt <|
byte by byte.
Output Mode
8051 Power Control Logic
This mode deals with display-
8051 has two power saving mode,
into two output modes.
¢ Power Down Mode
Display Scan- This mode allo e Idle Mode :
ws 8/16 character
organized as dual 4-bit/sing Difference Between Power Down & Idle Mode
le 8-bit display units.
* Display Entry — This mode As shown in above figure of 8051 power control logic, two control bits axe there, IDL
allow
the right side/left side. and PD, which are used for Idle and Power down mode respectively.
|
In Power Down mode, the oscillator clock provided to system is OFF i.e. CPU and
peripherals clock remains inactive in this mode.
In Idle Mode, only the clock provided to CPU gets deactivated ,whereas peripherals
clock will remain active in this mode.
Hence power saved in power down mode i is more than in idle mode.
Below table shows power supply current required to 8051 family controllers in
Normal (Active), Idle and Power down mode.
Operating
| . Oscillator
Ans. 8051 Assembly Current required in
2 S complement program 8051 Controllers | Frequency] Current required | Current
ORG 0000H | Fosc.. in Normal mode | required in Idle mode| Power Down mode

_ MOV DPTR, #0030H AT89S51 12 MHz 25mA 6.5mA 50uA

P89V51RD2 12 MHz 11.5mA 8.5mA 80-90uA
- MOVXA, @DPTR DS80C323 18 MHz 10mA 6mA 0.1luA for BGR
fee 2 CPLA See ei e ee . enabled.
| 40uA for BGR
ies _ ADD A, #01H disabled.
ae MOV DPTR, #0090H As per above table it is clear that power consumption in power down mode
is less
s MOVX @DPTR, A than in Normal or idle mode.
ol ee
8051 has power control register for power control. Let’s see power contr
__ MOV PCON, #02H
-PCON Register: Power control register
er
=. 9. (a) How can you put the 8051 mi PCON (Power control) register is used to force the 8051 microcontroller into pow
: a *

crocontroller in
e
‘ z

( Se

annidle mode? saving mode bits and

oe Ee

_ Ans. 8051 Power down and Idle mode (3)

Ae
ae . saving mode. Power control register of 8051 contains two power
: »

one serial baud rate control bit. | |

_ Power down and Idle mode features are used to
save Power in micro , Bg tS 4 3 2 $5085
es , a has inbuilt power saving feature which i is useful in embedded mana s051. 4 GF1 | GFo | FD {IDL PCON
SMOD| = | == fot
_con sumption i is main constraint. pnare power 4
 30-2018 Sixth Semester, Microprocessor And Microcontrolle
r
Bit7—S
it 7 —SMOD ? bias -[B.Tech|~Akash
hE; University Books 2018-31
1 = Baud rate is doubled in UART mode 1, 2 and 3 sit ae
an RS1 RSO Register Bank Address
0 = No effect on Baud rate. } | eo Pan j
Bit 3:2 — GF1 & GFO: = j i . eure
| a 08H - OFH
These are general purpose bit7 for user. | | (a 4 1 0 2 10H - 17H
Bit 1— PD: Power Down an 1 1 3 18H - 1FH
1 = Enable Power Down mode. In this mode, Oscillator clock turn, aay oe : Bits of the PSW Register
both CPU and peripherals clock stopped. Hardware reset can eave sda OFF ang Fi Q. 9.(c) What are the ways to mask an interrupt in 8051 microcontroller?
0 = Disable Power down mode. ree a =
Bit 0 — IDL: Idle es : — i: Ans. Interrupt Structure of 8051 2

7 = aes Idle mode. CPU clock turned off whereas internal peripheral Si = | Interrupt Number Interrupt Description Address
such as timer, serial port, interrupts works normally. I Pheral module —
Interrupt and H/W reset can c; : cae aay oe
eee saat: | ; te 1 _ Timer/Counter0 o00B8h
0 = Disable Idle mode. es 2 External INT 1 0013h
|
Q. 99. (b) Write the format of the 8051 processor status word (PSW) 4 001Bh
: :
Ans. 8051 FLAG BITS AND THE PS | 2 ‘
| Lhe
— see
‘RE SET’ all the int errupt s get dis abl ed, and the refore, ali aan es
Upon if anyone or all are activated,
i errupts, , if
OVOLIS
ster. In this: section we discuss variou©s bits of _
| nust be enabled by a software. In all. these five int
re. All these interrupts
Best interrupt flags as shown in the figure.
‘hi ~ a 7 nding
OE : 7
of how itheis altered. jue ecahe a in some special function register that 1s Interrupt Enabled

Th —— st it Maire ae : TE), and this in turn depends

TB) | | which is executed by IP interrupt priority
on | the priority,
ihe program
the flag ae : registeri is an 8-bit
acre ee register register. It is also refe penises. High priority
: | | :
8051. :The two unused bits are ee oe ” only 6 bits of it are used by th IE register IP Register went
anesnal flags, meaning that| they
conditio enable lags,conditio
indicate = someags. F Four nsof the gs are calle d
eae flags |
on 1s executed. These four are CY (carry), AC ( resuit afte
OV (overflow). 70 A\ auxiliary carry), P (parity)
. | ic Sc

_ used to change the bank registers Tc ne esi HSI, respectively,ire and are‘Ss INT1 1 it interrupt
| and PSW.1 bits are general-purpose status flag bits and
E
oC ies section. The PSW.5
ale .
tA
,
Foley
for any purpose. In other words, they are user definable © usec! by the programmer Trim 3
| _ [ey [Ac [Fo |Rsi[RS0 [Ov |-|p 3
CY -~—s PSW.7 Carry flag. =
re oo a PSW.6 Auxiliary Carry flag Low Priority
tar ie: FO. te PS5W.5 Available to the user for general ae
aces
ee ver, oa 1 PSW.4 Register Bank selector bit1, re |
_
ee ~RSO
ea PSW.3_ Register
) Bank
: selector bit 0 0.
ector bit Sapa upt structure of 8051
tae mi microc onkrolie®:
:

fe. PEW. User-definable bit. sane a (T™ ' ‘pit addressable register in which EA must fe p©articular
‘Interrupt Enable bles na
. disabling the intermuP™ Thea ¢corresponding bit in this register e
Bea Parityateflag.
PSW.0 _ indic Set/cleared by hardware each ing, a for enabling inte rrup ts.
an odd/eyen number of 1 bits in the nue men eyele to,
ator, umul a argon

7 4
Ave
’ &) .
; ; _ > af
™ » | pee
re tae ce \
‘ pin
32-2018 Sixth Semester, Microprocessor And Microcontroller

interrupt like timer, external and serial inputs. In the below IE register, bit COrreg itp - :
to 1 activates the interrupt and 0 disables the interrupt.

EA ES | ET1 | Ex1| ETo| Exo

FIRST TERM EXAMINATION [FEB.
KA.7 IE.7 Disables all interrupts. If EA = 0. no interrupt w; ee = SIXTH SEMESTER [B.TECH] 2 0 1 9 ]
If KA = 1, interrupt source is individually ana a acknowledge iad
MICROPROCESSOARNSD MICRO
or clearing its enable bit, Sabled by Set
sectumm, CONTROLLERS [ETEE-310
-
- IE.6
IE.5
Not implemented, reserved for future use*.
Not implemented, reserved for future use™,
i) )
a. M.M. : 30
ES IE.4_ Unable or disable the Serial port interrupt. Note: Attempt all questions. Internal choice has been
ae Identify the t . indicated net
ET1 .1. (a)
IE.3 Enable or disable the Timer | overflow interru t 2: ypes of addressing modes for the following instructions

ite tamcenc caren

of s06s. er
EX1 IE.2 Unable or disable Interna] intemipt 1. a al
(2)
ee M (ii) LXIH, 16 bit add.
(iii) ADI 06H_— (iv) CMA
nal Interrupt 0. Ans. (i) Register Indirect addressing mode
sites (ii) Immediate addressing mode
Interrupt Enable (IE) Register ae (iii) Immediate addressing mode (iv) Implicit addressing mode
‘Sa i Q.1. (b) Discuss the functions of following signals of 8086.
(2)
INTR, NMI, TEST AND BHE
Ans. INTR: It is available at pin 18. It is an interrupt request signal, which is
sampled during the last clock cycle of each instruction to determine if the processor
considered this as an interrupt or not.
NMI: It stands for non-maskable interrupt and is available at pin 17. It is an edge
triggered input, which causes an interrupt request to the microprocessor.
TEST : This signal is like wait state and is available at pin 23. When this signal
is high, then the processor has to wait for IDLE state, else the execution continues.
BHE : BHE stands for Bus High Enable, it is available at pin 34 and used to indicate
the transfer of data using data bus D8-D15. This signal is low during the first clock
cycle, thereafter it is active. |
Q.1. (c) Explain the flag registers or PSW of intel 8086. (2)
Ans. Flag Registers: It consists of 5 flip flop which changes its status according to
the result stored in an accumulator. It is also known as status registers: It is connected
to the ALU. |
There are five flip-flops in the flag register are as follows:
1. Sign (S) 2. Zero (z) 3. Auxilliary carry (AC)
4. Parity (P) 5. Carry (C) |
The bit position of the filp-flop in flag register is: |

Dy | Ds | Ds | Ds | Ds | De | Di | D |
SAleZ ee PAC Bp E Fe CY
All of the three flip flop set and reset according to the stored result in the accumulator.
1. Auxilliary carry (AC)- If any carry goes from D3 to D4 in the output then it is set
otherwise itis reset. | Be
in its final
2. Carry (C) - If the result stored in an accumulator generates a carry
output then it is set otherwise it is reset. |
. If lower order
3. Parity Flag (PF): This flag is used to in dicate the parity of result
and for odd
8-bits of the result contains even number of I's, the Parity Flag is set to one
number of 1’s, the Parity Flag is reset /.e. zero.
is set to one; if the resu It of ar it hm et ic or logical operation is
4. Zero Flag (ZF): It . eee
zero else it is reset. |
for mat the sign of number 1s indicated by
5. Sign Flag (SF) : In sign mag nit ude
one.
MSB bit. If the result of operation is negative, sign flag is set to
 ee

2-2019 Sixth Semester, Microprocessors and Microcontrollers

Q.1. (d) Identify the contents of accumulator and pie L.P. University-[B.Tech|-Akash Books
‘lag Stat us “8 faliga. | 2019-3
instructutions are exce cute d.
Wing Timing Diagrams for MVIB, 05H. As sho e ructi
wn in Fj g., the inst ,
MVIA, 7F H — &)
.
ORA A cycles. The first machine cycle is Opcode fetch. It takes 4 T-states 4 ae, 2 caer e
es ructionou se
CPIA2H :
seco hinees. cycle is a memory read which takes 3 T-States. . Tel£en i Instie
macstat
‘gidnd 7-T
cycl
Ans. MVIA,7FH; <A=7FH
ORA A; A=FEH Here 1s | description of what happens in the s ystem bus until the instructi
CPI A2H; A=5CH MVIB, 05H is executed (again I will explain a generic microprocessor rather than Saag.
Content of Accumulator = 5CH & Fla g status CF=0; AC=0 eeey a * The Program Counter loads the memory address 2000H into the address b ,
Q.2. (a) Write an ALP to find the : AUS, Pal, S20 eae T1 of the Opc ode mac hine cycl e. 2
given senee | dur ing
5D and 6E. oe
| : ee : °« The address decoding system locates and identifies the memory location
Ans.
2000H.
Label Instruction Comments a | e At T2, the Timing and Control unit produces the MEMR-signal (Read) which lasts
cea | Opcode 3EH from
at : SEH ; -Loads Accumulator with 9FH during T2 and T3. During this window of time the memory places the
Loads register B with 5DH Boe
ic ODH ; location 2000H into the data bus.
ster then into
| ¢ The operating system places the Opcode in the Instruction Regi
CMP B Pee. Loads register C with 6EH 2 des the Opeode it feeds
JC jumpl: ; Compares BwithA the Inst ruct
the decoded
ion
sign
Deco
al
der.
into the
Whe
Tim
n the
ing
Inst
and
ruct
Cont
ion
rol
Deco
Unit .
der
The
deco
fetc h operation is completed
ae
Moves content ofB to A in TS.
jumpl: | CM
|
Be
ac jumpe:; Compares C with A Ay ° The Program Counter is incremented to 200
finds
1H.
out that a seco nd byte which contains
oe no carry Jumps to jump2: ak e During T4, the Timing and Cont rol unit
MOVA,Cne : _ Moves content | of C toA | ae
oat the data needs to be read (i.e. address 2001
H).
jump2: | STA 4200H; eo a || is Mem ory Read cycle.
Stores cont SNe Peter
4200H at ° The seco nd mac hin e cycl e
the address 2001H
HLT; the of
TermSeeinates ent prog to menon
A ra jocotee cycle the Pro gra m Coun ter load s
e At the T1 of the 2nd machine
Q.2. (b) Exp lai n the vari w e
€ various hardware interrupts of intel 8085 microp A
into the address bus. mory location
oa the me
-t\

rocessor, an d id en ti fi es
ots

lo ca te s
e. The address decoding system
2001H. :
ME MR sig nal whi ch lasts during T2
unit produc es
Q.an 2. (a) Drraaw and explain th e At T2 the Timing and control ced int o the data bus then into
e timingadiagram of MV e the dat a 32H is pla
IB 05H and T3. During this window of tim
the MPU. ea.
= “ (Opcod
, e fetch) the data 32H is sto red int o the accumulator.
| 24
| a (Memo tr e During the rest of TS, dat a is tr an sf erred into
2 T; Ty the RIM ins tru cti on 69 H
T;
aT. — q; ~ Q.2. (b) If after executing fer ent sig nal s. (2)
mulato r, the n ind ica te, the status of dif
the accu
Ans.
RIM Instruction >

elses bees!
0, 9, D, Dd, D, 9%
2D, 2,

Mask status of 3
RST $3.5 Bx
‘ |
Mask status of (2 =
crsal Input Data 2¢
RST 65
,
Interrupt. pending > Mask status of }* 4
Kpenae sy —o
Peerrupt 1s not ponding

status of RST? 5
Interrupts are enab
Interrupt pending

Interrupt pending lntertupt by

status af RST 6.5 Enable Flag fo= Innerrupts are disab
Interrupt pending
status of RST $.5
—— =
 4—2019 sixth Semester, Microprocessors and Microcon trol!
ers
RIM=69H =01101001
| a
SID=0, I7.5=1(Pending), 16.5=1(Pending), 15.5=0, IE=1(Intepp
i ~niversity-(B Tech} Akach Books
M7.5=0(unmasked), M6.5=0 (unmasked), and M5,5 FAX: 2019-5
=1 (masked) UPts arg enaby
| . GST % CX
Q.2. (c) Sive two examples each of One )
Byte, Two Byte ang
Instructions. SS DX
Ane. Three p_
ove | DS
ag toe_| BX es + No 0 DI DISPLACEMENT|
.
3 | 2 8-BIT DISPLACEMENT
Groupipi
ngng ofof j instructions of 8085 accord _| FS BP
Seing to length ae |
. am | GS | SI
LET
ae |a Ex: : MO
MOV AX, [S
[SI+
I+08
08H]
H
a ADD DX, [DI+1006H]
| ‘One Byte
instruction 28 Based-indexed Addressing Mode
(ne word)
7 :
acai a | | eo Displacement — Points to first address of
ode .
ae : _ data (Constant)
O lt’ ee
operand both os eS ' byte
s
.- ne

ini byte © Opcode ig jst byte | —_Base Register > Contains Matrix column
bytelocne * sh Operand ig 2nd if 3rd ;
| Number (Variable)
erally 8-bit byt Ralls 423 ee |
Eo: MOY AR ae p Ta demenetorat
ADD w data)
| 3
Le (generally 16-< Index Register + Contains Matrix Row
TESS Ordaigyaame = Number (Variable) =
Eg: AD
: I 881 oe | Se |
Eq: Te rr Regardless of 2
SUI FcH : a using SI or DI
eee | . When Base Register is BX
Q.3. (a) Explain B
Mi
. ased, Ind
“roprocessor with Su a
ae PA == DS: He. BX + (SI. or Dl) + Diaie splaceme
} nt
itab® le ¢ €xed, Ba -
Sed-Indexeg addressing : -
Ans. Base Resi ples modes of 80 ;

*In base ; ter Address £ Mode

PA~= Segment base: Base + index + Dispiacoment
Part of instruction “ 6 Mode, Contents off
an = Hae
* It is simi] ae eerie addres, | Pe aoe 08 |. | ax #4 St\, } Sdit displacement
Si fae aSe register is added to address These are default segments and .
ex © addressi:ng Mode except 3th |
e répist . ae|
Segmen
, :
t-Ov a
erride Prefix Changes t em = =aeee et
© The
base egis: ter hold the beginn; te
ax er
On ae :
* The address Part of instruction
h uate addres
Ex: MOV AX, [BX+SI+08H]
. Offset remains Same, the hecte ds the offset ADD DX, [BP+DI+1006H]
|
* 16) RAM with system li; nes of 8086
Q.3. (b) Connect 128K word = (128K
* When the offset ig added to the eae 16
location where the operand will be | microprocessor, Assume suitable address.
ay nebisler the Tesultant number ;
Ex: MOV Ax, [BX+08H] Sate ae |
= : Ans. Memory capacity = 128 K word = 256K B
yte
=
srs the men
ADD DX, (BPs 100657 128 K by te for even Memory Bank
ie _ Index addressing Mode: 128 K byte for Odd Memory Bank.
|" | + Address Decoding Table
Total Total | Even | : Binary Address
| -
|
‘*uction is presen, BLELESI] memory
256 K
ee necro ta AisiAis Aig Ais Ang Aig Aig Ay Aigo Ag Ay Ap Ag A; A, Ay A, ALA)
00,000000000000
0000 010!
ned by adding rpnemory location fa yi g [P OH ]
"hree contents ; ) 0 0 0 m
|srFFFP,|3FFFE,|] ° |
|RAM 0 0 eeeeS tS
bt 2-8 70
4
; rere auc
|
=

Decoded A, to An address pin of memory

for X
6-2019 Sixth Semester, Microprocessors and Microcontrollers
L.P. University-(
B Tech} Akash
Books
Aug

Avg ”
Following figure shows the interna] block di
agram of 8036 microproce
The 8086 CPU is divided into two inde penden ssor
t functional parts, the bu
anit or BIU, and the execution unit or BY. s interface
=. CSE
a CSO 5
ye” e—RD SHE —

The Execution Unit: The execution unit (EU) tells ¢ . ,

A,=.
-A.g) TWOK*S
EVEN A pee
=A »| 128Kx8
ODD _. ) 3 vee
or data from, decodes instructions, and executes insthe ions.where to fetch instructions
ructBIU
pint a microprocessor BANK —- The functional parts of the execution unit are control circui
MICTOPrOCeSsor 4
instruction
try or system,
nit —WRe decoder, and Arithmetic logic unit (ALU).
Control circuitry to perform various internal operations. A decoder in the EU
D,-D Fie translates instructions fetched from memory to-generate different internal or external
control signals that required performing the operation. The EU has a 16-bit ALU, which
X is decoded with A, to generate CSE (chip select logic for even bank) and Kies can perform arithmetic operations such as add, subtract etc. and logical operations
decoded with BHE to generate CSO (chip select logic for odd such as AND, OR, XOR, increment, decrement etc.
bank) toe zs = Q.3. (b) Compare Procedures and macros using asuitableexample. (4)
- ¢
a de
Af

. oe

Q-3. (a) With the help of block diagram explain the t i

- DF ams
OR e = 2
ae ee

of Intel 8086 Microprocessor. xptain the two modes of oP a , Procedure Vs Macros

Ans. The 8086 Microprocessor- Internal Archit _ Procedures Macros

ecture: The Intel 8086 isa1 6- mY, Accessed by name given to macro when
at microprocessor intended to be used as
the CPU in a microco mputer. The term “16-
,
"EDBy hme
Ae, Accessed by CALL and RET mechanism
it’ means that its arithmetic logic unit, in — during program execution. | defined during assembly.
ternal registers, and most of its instruct
are designed to work ions :
16-bit binary words. It has 16-bit databus and 20-bit addr Machine code for instructions only putin | . Machine code generated for instructions
ess bus.— memory once | each time called.
ry locations. If the first byte of awo
¥ >

rd i”
fe
< : .

Parameters are passed in registers, _ Parameters passed as part of statement

memory locations or stack. which calls macro.
Procedures uses stack Macro does not utilize stack
A procedure can be defined anywhere in - A macro can be defined anywhere in
| |program using the directives PROC and - program using the directives MACRO
ee ee re | ree ae ee ee am em Lee eee a:
and ENDM.
| code is very huge if macro’s are
Lengofth
: = : , 5 :
ENDP.
“ae
Procedures take huge memory for
galled for more number of times.
'
;
CALL(3 bytes éach time CALL is used)
i
“5 :
Instruction
4
5 :
Stream instruction. RT I Ae
f
>

Byte
4

4‘
+s

~ Queue
.

biel
ll

hi

PSP 2 ee oe es on
:

4
\

4
eins

fl4
eS
wr:
:
f=

Fy

—
i voy
rpom r wr rrr
‘+
4%.

rrr
:

rw ew wwe er ee eK
4
Domes

*
a
Pi

agw
-
=

a EU
”
?

oot Toe
pat)

“a
ae

awert
z

VT
Bs

ee j. , re ; ; -
SE ICO Ee EEE
z ; s
ST
:
OE PE +
We we we we we ge oo :

_ 8086 Internal
Block Diagram ~~~~>~~-~---
7 ~ a, A ofC
- a

(at Reais
 END TERM EXAMINATION [May
LP. University-[B.
Tech} _Akash Books
3 It has built in baud r 2019-9

SIXTH SEMESTER [B.TECH] 2019)

ate generator.
4. It supports standard synchronous protoc
ol with -
MICROPROCESSORS AND MICRO e 5 to 8 Bit character format.

CONTROLLERS [ETEE-310) e
e
Internal or external character synchronization
Automatic sync insertion
Time : 3 hrs. e Baud rate from DC to 64 Kbhaud
Note: Aiiempi five questions in all incl
ee uding Q.No. 1 which is eo mpul MM, ; 15 5. It allows full duplex transmission and reception.
from. each unit. Assume missing data if any. soy, §
%. Select o 1 Question 6. It provides double buffering of data both in the transmission section and in the
Q.1. (a) Is there some mini
mum pulse width re qu receiver section
case of 8085 microprocess ired for the INTR sia al in
ors? Explain with reason
. 7. It provides error detection logic, which detects parity, overrun and framing errors.
(3) |

~~
8. It has Modern Control Logic, which supports basic data set control signals.
9. It provides separate clock inputs for receiver and transmitter sections, thus
: providing an option of fixing different baud rates for the transmitter and receiver
oper
u8at
58 . ed at 3 MHz : clock f
requency, then the INTR puls section.
|
e must remain sta tes. If 8085 tS
high for at least 10. It is compatible with an extended range of Intel microprocessors.
Q.1. (b) Explain how man
y umes the following | 11. It is fabricated in 28 pin DIP package and its all.inputs and outputs are TTL
LXI B, 0008H § !00p will be executed (3)
LOOP: DCX B- compatible. Se ae ee
. emperature-.
p a
JNZ LOOP 12. It is available in standard as well as extende
Ans. 7 times | Q.1. (f) What are the
.
different i
operating des
modes of 8255 Programma i)
Q.1. (©) Write a pro al Peripheral Interface?
microprocessor Gram to generate a delay of 1 milli-second in 8086| Ans.
a5 ae to a 1.(c), End Term Examination 2018
. (Page No. 9-2018) Fa ( "
; xplain the usefulness of TE
< ST ae aan 8255 PPI MODES OF OPERATION
microprocessor | LOCK ’ instructions in 8086 | CONTRO WORD OF 82554
Ans. LOCK : Its an active low
| | ee : Di Do
D? D6 Ds no
rc O/1-
{BSR MODE |
: |For Port C :
Q.1. (e) Write the ‘mportant features of82ading ed
:
internal!| lly
51 IC ce the clock |NoEffect | Mod :
Ans . Features of 8251 Microcon
trolley
SART) (3)
On VO Mode Simple - vo

2. It supports standard asyn ee ie ate 0 or

in mode
chrono
© 65 to8 Bit character format
* odd, even or no parity genera used for
tion and | detection
- © Baud rate from DC to 19.2 Kb oy . 7 handshake __|
aud ©
* False start bit detection
=
* Automatic break detect and
handling
* Break character generation. Mode 0 (BASICle YO) output capabilities using each of the three po
ee t an d
~
° Provides simp inpu
a
 10-2019 Sixth Semester, Microprocessors and
Microcontr
o lleng
* Data can be.simply read from and LP. Universit
written to ¢] 1e y-( B ‘Tech Akash Books
respectively, after appropriate initialization, input and Output | yO Mode Con
trol Word re 2019-11
* No Handshaking is required. Port, | gister
CONTROL WORD arts

PA}——PAG-PA7 | PA |-—>pa
y --> PC4-PC7
wr M
aN

GROUP B \
825SA :
PCL | ~~ *PCO-PC3 8255 PORT C tower: PC 4g PCy
Les
: PCL 77 . * foe Inout

| PR > PBO-PB7 0 for Cutpus

PORT 2
PB > PBO-PRZ
beste
n
1 £6 inget
tem
9 for Sutgut

Signals in MOD Linde Selseson tor Par g

Mode 1 (Strobe V/Q) Qfortiede 9

° This functional conf e Flor lode 4

iguration provides a
means fi 5

GROUP A
and Port B PORT< (Upper! PC 5 «PC 5

“handshaking” signals use the lines on Port C to senerate or accept th ese T for input
0 for Output

: fom PALO: 7] oe oe PORTA

1 OF Input
9 for Output

PCS }——>IBF(A [AL et htode Selection

ntmA
aca LiPBIO:7) OL
re 99 for Meda 6
* ST Rehiodet

8255A Pc3 [-~>INTR(A) laa ts fer ode 2

10:7] | 82550 lens PB[O:7}

p pone . a) ia 28 ;
1 for
vo Mods

= isséd;«t
G tor BSR Mode
< a Pc2 |" OBF(B)[AL]
a L
Pco [~~ INTR
C6, leo
ces oe
O/P-
PCr ["" ACK(B)[AL)
aPco | ~*INTR (B): :
7
a
mode CWR Dy

*Thi s — Bidirectionaliv Bus 1/0) = ies

are
;
ae | Port C bit Set / Reset
peripheral cae tos i Provides a meang fi 0 c % 7
_-— Pog Cit select me
ao= Set
Sat } seats 9 ae ake Don'ttcare
data (bidirectiona] bus VO). See 8-bit bus for both ai eee eae eae yesSe ie i =ak> eA > 0] Bio
Hoo" se “Handsha4 kin. e signal : : an pete
9 4] Bit
similar|
manner to MODE 1. 8 are provided
provi AS Bit2
+
to maintain Proper bus flow disc; lit oa git3
| | Isciplineina Bit4
e e * Interru pt generation
i and enable/d , |
isable functions a “4
| Bits
| Bit6
connie ne 0 B80 available ae . -pacasag) Bit7
. pe eontrol word format used
- - 808|1
in :
aaa -and logical instructions
Q.1. (g) 7 hat the diffe

| a roup of
_ Ans. Logical period ctions: The ~ Ee AND, OR, XOR, a NOT , Rotate, Clear
bit-by-bit basis.
ae

ogical oper
instructions, which perform '0e™*" alie™ on Byt es of data on
"med
ce
ehte ish>
r nfsabis

l instructions are as follows:

perform
and Swap. Logical instruction+h are Logica
ate
Spay
Ea
295

Mnemonics associated with coil @ ORL

syd eerSeslg
ae
ye

e ANL pe eae © CLR

hie

°*XRL - GSR gig _ .eRL

“
hos eae
+
=
s

CPE res ie eRR

ow
«a

* RLC + SWAP
POR
P
ee
ry}
=

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.
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on

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ay .

ay | y

x
’ , = * fi

Ts Reece Nita ars a a cin tanta ctatieitan dia.si

 12-2019 Sixth Semester, Microprocessors an
d Microconty Ollllerg
LP. University-[B.Tech]-Akash Books 2019-13
UNIT-I
et _ MUdnessing Mode Taree Qg
A.#Data | , 8085 has fetched the machine code located at the memory location
linmediate | Fp (5)
ALRn A © AAND Rn Q.2 (a) sity the contents of the Program Counter.
Register — = |e
A. Direct A € A AND (Direct) Dire oo Lali 905 B, spe tent of program counter depends on the size of the instruction. If it is 1Byte
| A@Ri | A € A AND @Ri indir ee
f — oe — . Ne
ADS: an PC=2060H after machine code fetching, for 2Byte instruction. PU=206 1H
Dire#Data_
. |_A| (Dir
Diect)
eis acseee ose ee

€(Direc
re€ct (Dire
)t)c)ANDAND#Dat
A a| rege
ndiréct ; Ks

| _.|__Ditect, | Direct instru Byte ‘nstruction PC=2061H

pe
and fOr ) What are the different control signals and status signals in case of -
ORL (5)
A, #Data
Aka
A © A OR Data Immediate 5 Fes vc oprocessOrnt Explain the function of each one.
| A € AORRn Register 308
A. Direct A € AOR Wireci) _Direct
AGRI ab le si gn al . It go es hi gh du ri ng first T state ofa
_A © AOR @Ri Indirect ae _ It is an Address Latch
En
e is 1 otherwise
8_ bi ts of th e ad dr es s, if its va lu
oS (Direct) © (Direct) OR A Direct nine cycle and enables the lower
Direct. eData__| Direct) € (Direct) OR sata Direct
is a c tivated.
H dat a bu s
de te rm in es wh et he r th e addr ess is for input-
: os A © AXRL Data lmmediate ~P - I t i s a s t at . signal which
us input-output
. 10/ M s on th e- ad dr es s bu s i
is s fo r
E 1) the | ad dr es
A.A Tract
Direc AS A XRL Ra
A €AX RL (Direct) Register
Direct output or me m or y . W h e n 1
n th e ad dr es s bus is for the memory.
re Paigddress-0
e7
teat ioral i es of operations
ices. When it is low(0) oe
SoAFData._ || (Direct
_@) ir € Dire the various typ
eec)t)
€ Direct) XRT KREA
a] | pc
mer Ls aD era eae oa <1 - These are status signals. They ri TATUS
h DO it. reading, instruction fetching or writing.
such a8 So - DATABUSS
Soe = So OH = 10/M 2 i Opcode fetch
Sea ae ae 0 i 0 Memory read
0 1 1 Memory write
0 0 0 I/O read
RLC A
: Se
| Rotate ACC Left through Carry
EOL
:
=
= 1 aes — | WOwrite
1 Interrupt acknowledge
: = - Rotate ACC Right] “1 0
1 A 0 . Halt
RRO | A Te ee
7 Qe ee : e sele cted memory
operation. When it is low the
aa al to control READ
° RD - It isa sign a: : } | :
Q.1. (h) Write the main drawback : =e or input-output device is read. ration. When it goes low the data on the
Micr Pp ;
[etic EC pee , Bi
S of microprogra ae
z —™ =
o-F rogrammed Contro] Unit: In th W" ee i tion. a
ee One WR It
° WR - ees is a signal to control
TRACT ons stor * 4 the mi . ae | selecte d memory or /O localio™ data or not. If READY
ed in a mem ory calle ater “To pro gra mme d cont rol unit, —
machine instruction,
a set of a Microj r o l1. memory.7 In a resp data bus is written into the a peripheral is ready; to transfer
ssor W aits till it goes high.
fap ; E
microinstruction will gener ate onse toa | ae pe ae Sis ready. Ifitis low(0) the microproce
, whether
eae ; a set Se aetio : Nn c ei cuted by which ea
macroinstructions will resemble the of the contro] si a's 1. ch —
€. exec is high(1) the PY . ort address?
2 : €xecution of ution of a set 0
Sat ‘< useful for | an output t po port have the same P (2.5)
A micro instruction consists of: S Pro gram.
a = Can an input port and
__ 1. One or more microinstr ee
uction to be execute

-—

3. Easier decoding and sequenci

ng can be done. | Q.3. (a)
_ 4, Easier to handle complex instructio
n sets. data bytes
5. It requires a less chip area.
sum. (The sum from 2060H to
Disadvantages of micro programmed | ‘on
cpntnel unit; pointer to trans?
ry location 9100H.
. - >

hardwired
|
- ’
control unit because the micrcinstructions are to
+) is j

| _ memory which is time-consuming,

| ote f

| | be fet
Ans. Let us taSUPP
; a
OS®
re t o b e a d
a s
j
2064H. These d
an
 14- 2019 Si|xth Semester, Microp
rocessors and
Program Code: [.P. University-[B.Tech|—-Akash Books
LXI D, 2060H 2019-15
XCHG F DB ODh, 0Ah, 24h ;Carriage Return, terminator BYTE
MVI C, 04H CRL _ The DW directive is used to declare a WORD type variable -A WORD
MOVA,M DW |
‘ s 1 6 bits or (2 BYTE).
UP: socupie
a t i o n e x a m ples:
INX D peclar
XCHG
ADDM - Word2 DW 65535; OF FFFh, (the max. possibile for a WORD)
DER C e
3 DD - The DD directive is used to declare a DWORD -—A DWORD double word is
BYTE. |
nade up of 32 bits =2 Word’s or 4
Declaration examples:
Dword1 DW 12345678h
Dword2 DW 4294967295 ;OFFFFFFFFh.
ate wi |
Ans Refer Q 3 (b) First Te th the help of examples nterrupts in 4. STRUCT and ENDS directives to define a structure template for grouping data
rm Examination 2018. (Page N items.
a ed
: | 0. 4 (1) The STRUCT directive tells the assembler that a user defined uninitializ
(a) Explain thec regist ee ng oo oe data structure follows. The uninitialized data structure consists of a combination of the
ae© in- 8086 micropro £ister addressi m 1 a
three supported data types. DB, DW, and DD. The labels serve as zero-based offsets
With the help ihe. de and immediate addr Spe
Ans. The Way of s ae
essing into the structure. The first element's offset for any structure is 0. Astructure element
“ay . Pecilying xample,
addresgj
It also ee This specifies that a.” be Operated by. ans. a is referenced with the base “+” operator before the element's name.
€S whether the © Sven data is n Instruction is knee é A Structure ends by using the ENDS directive meaning END of Structure.
Types of
Regist er
addressin
ad
g a es: © OPerand . isregister or register e
or “imediat data
pair or an a direes
re 8s, Syntax:
STRUCT
are registers dressing mode ~ In th Ss a Structure_element_name element_data_type?
Ex ample: 'S type of3 addr ssing mode bo tan 6ws
l. MOV AX, BX - operands
Re
= XOR AX, DX
ENDS —
Immediate es (OR). oe.
mode on - | “: . ‘ek
or 16 bit, data Destinati on type of dre Ssin se STRUGs224 |
_data_type?
Structure_element_name element
Example: | Perand can never = Ode the Source =
3. MOV AX 2090 MMediate data | and is a8 bit
~ MOV CL, 0A oe
_ 8. ADDAL, 45 ; ENDS — |
oo 0000 DECLARATION: —

Note that to init; alize th | 2 OTRUO TA

Bytel DB?
MOV AX, 2000 © value of segment regis Byte2 DB?
~.
532-04MOV Cs, ax
. &): | | exeo “ester jg required ~ Word1 DW?
Word2 DW?
ae e the functions the different Classificat; |
Fe oe Pertormed?e rie ations Dword1DW?
ns. Data
eer Ans | of— asg,,—"*©mbloa»
bler 3: apes “al| Dword2 DW?
declarat
di ion directives. ai ee directives based a der of items
id Z; DB - The D

a
a

5a (4.5) 9 Use OF STRUCT: Th directive en ab le s us Tie

to cheat
an ge th e
oe
or
Made up of 8 bits °° #8 Used to declare a BYTE a e STRUCT d@ shuffle the data. Shuffle the da
= <= | Declaration examples:
3
in the struct ur e wh en ref
, we
orm
w e
a
|
fileS
he
the
e
al "
sequ
ect
"ee of data declarationin the; STRUCT
i er and reformat
file head at pr oc eser is necessary
se s the file head
we wr it e th
DB an. ., hs | 3 ca, ae No change in the code
_Byte2 ae aan
eat
nts

DB 255 ; OFFh, the max. possible for a BYTE d to give name to

rep
re

ae sa th e pr ogram, it wul
.

gi ve n na
.

me s 1p
the assembler finds the
; ,
w+.

ene
ae,
p

ou Ss no
 16-2019 sixth Semester, Microprocessors and
Microcont ll
Tollerg
the name with the value or a symbol. The valu
e can be in the
it can be another Equate declared anywhere above or range throy -
Thecogi
follee
owi operators can also be used to declareoe
an Equate: on 6559
I.P. University-[B.Tech]|_Akash Books 2019-17
e and f oFFSET: It is an operator which tells
the assembler to determine the offset
THIS WORD eer ) is cement of a named data item from the start of the segment which contains it.
THIS DWORD oe | | | or disP 7 to load the offset of a variable into a register so that variable can be
accessed
A variable — declared with: a DB, DW, or DD directiy Iris use
qith one © f the addressed modes.; Example: when the assembler read MOV BX.OFFSET
space reserved at that address forj
address. or space reserved tin the .COM file. But © ~ has an addr
| for it‘ee in the RICES, 1it willwil dete
determine the offset of the prices.
:
-COM file. an Equate €Ss a a, | ROUP : It can be used to tell
does Not hay CT Ae the : directive into one logicathe assembler to group the logical segments
l group. This allows the contents of all
Example: | i nae ents to be accessed from the same group. Example: SMALL-SYSTEM GROUP he
A~ByteEQUTHISBYTR | en | segCODE, DATA, STAC
ey 19° Sh - = ACK- SEG
K-SE G.
<a ae THIS WORD
| | CO g.4. (c) How many bytes of storage do the following
EPROM = memory |
oo
eC. tain? (i) 2716 (ii) 2764 | 3 ts)
A_dword EQU T . aie Ans. 2708 (1K *8) =1024 bytes
DD 4294967295 aa
er Size EQU 1024 |
2716 (2K*8)=2048 byte
See 2732 (4K*8)=4096 bytes
aa DB1024DUP()
uffed_ptr EQU $ - ac —— 2764 (8K*8)=8192 bytes
Se » actual] cae 16k*8)=16384 bytes |
nara, 27128 (161 )
are] someE*e™ : assem
other Ibis used
b] to tell the aer *yte after the; 1024th byasgaseen
am 04. idee
. the microprocessors? (2)

eee ice ata dit y mod

e ee aoxamnl e:; ame or label f
that then
|
is because when micreprocess
Ans. It is becau 5a Se : gay fatecrupt tignal from
fee oe calla proces Wing the peripheral(s) which are Rae t execution and program
© assembler that th @¢ which containg th ie AEE anal and after executing
int a e proc
Code file so that the i e CALL trol is transferredSeento a sub-routine
1S external the assemble r contro l is m controi i isis transferred to main|
Instructions sub-routine by generating RET oe: ee = rograae receives interrupt signals, it
ample : an connect the two module together program from where it had pe a the peripheral which is
PROCEDURE -HERE SEGMR requesting for its service
sends an ace I a nt conditional transfer instructions in 8086. (7)
EXTERN SMART-DIVIpp. FAR
@(7) OCE DURES- HERE ENpgNDS U4 i the segment ; PROC] CEDURES | 05 Oe ae ies instructions in 8086 microprocessor
GLOR AL: 7
HE Pn ce eseo
Program execuutio
tion ntrans transferi
r ins‘cuctio ns are simil ar uctio
to a different instr to branc hing nceinstasruct
n seque
d
ions 0 and
a result
4 name defined ; ae : CLOBAL directive N be used
the symbo] available oe ~ssembly module: t sarin3+. Place ee cin refer to the act of anes aay oa ie |
of P UBLIC directiy re - executing a branch instruclion- ecution transfer instructions
GLOBAL pry to the
SOR. other mod
odules. » the e.CLOBAT
Exampl dina recticpve
a are:
is used to a
make | two ttypes
The two ype of program ex Rie
2. Conditiona l
type of word whi ‘OR: WORD tells th et 1. Unconditional «on
| |
his in anoth © assembler th Transfer Instructions — These instr uction
ot
(8) SEG
ae to the the Se lis c y Oy modu le o; EXTE JIVISOR is
sed i Indicate the start of a. RN.
u * 5 : &
a variable} ‘1. Uncondit‘tion
io al Program Execution
- }
aE
a always =
us — a0

OPERAND|
k

€ start of logical Segment EXPLANATION :

3
Plle: the code Segment ; 2 fogical segment. Itis
(9) PROC: (PROCE te the name
n 1S used to indicate to the asse | OPCOD callsretur
mble CALL address a a subro utiness and
n addre saves
on the stack “CALL
CALL 2050
Afte the aathe Procedur. e. )Itis Used to ide nti ly the startoe of a Proce
si Seas
dure. It follo
a returns from the subroutine to
RET =. {°8 one the main program e RET
ple:
ast Pie: SMAR|
oa 4 a =.
;| transfers the con trol o SOA
JUMP | = aacrrne aceeution to the specified address JUMP 2050

| 1-ess. _| loops through a sequence :

LOOP acre of instructions until CX=0 LOOP 2050
3 eT ified directly or indirectly.
Here the qearens <A? be a Transfer Instructions : These instructions only
:
Ct ODE a tbeOPER
speciAND|
fied condiEXP
tion LAN
1a true.
ATION | _ PaEXAOAEG
MPLE
Ce, address juifmp CF =1
Gees
JNC | address Jju
i
ifmpCF = 0. JINC
JZ 2050
2050
JZ address jump if ZF =
 Microprocessors and Microcontrollers
Si‘<xthth sSeemes
ter,
18-2019 ee : I.P. University-[B.Tech]-Akash Books
2019-19
————
JNZ
T addres
;
s |7 jumpifZ i'=0
‘amp if OF = 1
INZ 2059 INC SI; Point to next location
ddress jump JO 2 050 |
JO a Ss ‘ump if OF =0 JNO 205 ADD AL, 01H; Add 01 with the AL
5 address J 0 MOV [SI],AL; Store second number into memory
oN address PF ==01
Jjump if¢ PF INP 2050
JP 95 MOV CX, [600H]; Take the limit of the sequence
JP
JNP
© Jan
aduress
1
AN ; if PF = 1
ae
JPR aan SUB CX, 0002H; Remove 02 from limit
address =_—* 1 2050 L1: MOV AL, [SI-1]; Take the last stored value into AL
a address
‘ump
yay
if PF = 0 JPO
: 99 50 ADDAL, [SI]; Add current value with AL
JPO
is0 address jump if SF = 1
: “4 e 0
JS 2050
, i
iNC SI; Point to next location

INS
JA | address
address | pif
— CFO
ager and ZP=0
om
AA 2050 uh
MOV [(SIJ, ALI; Store AL content into memory
LOOP L1; Loop to L1 until counter becomes 0

JNBE | address jump if CF=0 and ZF=0 — JNBE 2050 | HLT; Terminate program
‘JAE 2050 | Flow Diagram
JAE address jump if CP=0
JNB address jump if CF=0 JNB 2050 |
JBE address jump if CF = 1or ZF=1 JBE 2050 | ;
JNA | address jump if CF = 1 or ZF = 1 JNA 2050 |
JE address jump if ZF = 1 3 JE 2050 | a eT
JG address jump if ZF = 0 andSF =O IG 20507 i. SS eo ferieh prs algo es a oh a

JNLE address jump if ZF = 0 and SF = OF JNLE 2050 — f |

JGE address jump if SF = OF JGE 2050 |
JNL address jump if SF = OF JNL 2050 |
JL address jump if SF != OF | JL 2050 i” *
JNGE | address jump if SF != OF JNGE 2050 | |
JLE address jumpifZF=lorSF!=OF ‘SLE 2050 7
JNG address jumpifZF=lorSF!=OF — JNG 2050 |
eCke 5. {address jump if CX= 0 e JOXZ 2050 |
LOOPE | address loop while ZF = 1 and CX=0 | LOOPE 2050 |
cad

AL= Pla oe
ties Pal Mente Memory
LOOPZ | address | loop while ZF = 1 and CX =0 — LOOPZ 2050 ; )
LOOPNE) address loop while ZF = 0 and CX =0 LOOPNE 2050 fs
LOOPNZ! address loop while ZF = 0 and CX = 0 LOOPNZ 2050) i
(A=
es 2
; <a
ic}
=
agmea
.
teh
~
se
e
ee a E
~)
aa fi

2. <19.e
b

Here the address can be specified direct

— . “
oe

ly or indirectly.

ZF is zero flag ig
OF is overflow flag
PF is parity flag
SF is sign flag
CX is the register
Q.5. (b) Write| an 8086 assembl i bonacc
| ; : language Program to generate the ma
series using a recursive anceh
Ans. To : | PGE a ay emcee
AL = AL + elemento
34

Sequence, we are putting the 00H and 01H into m

4 a ii ars Fv si e: 75

at first. Then “a ae
2 at first 8 the limit from location offset 500. The limit is decre 7 OP '-- T=
5a Vite
fi
Py2 be

Ut De: eee W
Ft ae
‘ taril iNet!
; TT iY p
Bee
Pome2\ | VR Se
eee
ath a :
TNE!
so} i a

: ; Load “41
—
MOV SI, 500H: Ping ith OOH
: » Foint to offset
500
MOV (SI),AL; S
tore first numbe
r oot memory
 20-2019 Sixth Semester, Microprocessors and Microcontrolleng
. “™ ‘. . * e M

Output Univers; IP.

as Jniversity-(B.Tech}-Akash Books
Address Data 2019-21
. | ¢
i whe 7- The system consists of 16 numbers of hexa-
segmetit LEDs 6a be tnd ey acs exa keys and numbers of 7 -segment LEDs.
600 oF
00 a de splay eight-digit alphanumeric character
601 01 Be shown* The 8279mapped.
is I/O can be either memory
a mapped or /0 mapped
mapped |
in the system. In the circuit
602
a. } ;: | °
a
pr ‘aaes 1j
line Al of the system is used as AO of 8279.
ie He a ond * bird
Ihe CeIn
clock signal thes for 8279 ej obtained
i ividi
steht by dividing the : PCLK (peripheral clock) of
605
608 0805 .
| e
aa en
j is
chip select signals, for I/O mapped devices are generated
by using a 3-to-8
607 OD. ee 4
608 | pee | 4 : * The address lines A5, A6 and A7 are used as input to decoder.
- 609 99 / —e * The address line AO and the control signal M /1O (low) are used as
60A 37 enable for
"4 a decoder. The chip select signal IOCS-3 is used to select 8279.
60B | 59 | |a * The I/O address of the internal devices of 8279 is
shown in table.
60C ee 90 a Be | , _Binary Address
60D E9 ; na Internal ‘Decoder Input to Decoder Hexa
zs, He ie? ‘ee e Device — input address pin of 8279 enable (| Address
- _ UNIT-IT } | Ay Age Ay Fe eae eee
LEDQ.6. (a) How will you
Display anhiga' Prag: interf | P e n t r e | ae 4 1 Ay
aha Pushbutton keyboard and a Seven-segr, Data register |0 1 1
= Re x x x 0 0 60
| ammable Peripheral Interface (PPD)? Illus i «| [Control register |0 ED eee es 1 0 62 |
Ans. | es | <a a | Note: Don’t care “x” is considered as zero. .
INT
NTERFACIN G | 8279 WITH 8086 |PROCESSOR + Seia ¢ The circuit has 6 numbers of 7-segment LEDs and so the 8279 has to be
programmed in encoded scan. (Because in decoded scan, only
4 numbers of 7-segment
and F 8086
;
bas ed Ee
system is shown. “iD display interfac ing circuit usinegg9| LEDS¢ canInencod
be interfac ed):
| eae rey Se ed scan the output of scan lines will be binary count. Therefore an external,
: — 3-to-8 decoder is used to decode the scan lines SLO, SL1 and SL2 of 8279 to produce
nh, AD, aan a | | eight scan lines SO to S7.
| 0gs cr Ay, es ¢ The decoded scan lines SO and S1 are common for keyboard and display.
mg uss au o : pe ¢ The decoded scan lines S2 to S5 are used only for display and the decoded scan
+ Bhp D,-B, e lines S6 and S7 are not used in the system. 3 ,
5 ORT We ) er ~ ete iegana 0: 4 -e Anode and Cathode drivers are provided
to take care of the current requirement
a lO
RESET}> io Pg ey Gna’ baa vé
| Bos wd ———|— of LEDs. |
1 Pee PORE ees tera 5 Be OU as .
Clock fins | : = ; AONE oc pe ne ne _ The pnp transistors, BC 158 are used as drivereae transistors.
isto a
eg Peltor aes Oey SE gazg | ISPTAL es ao ee eee ee - . e The anode drivers are called segment drivers and cathode drivers are called digit
{a9 «Pics, A PORE con en A ee drivers. : |
ae i feea | ee {tee ¢ The 8279 output the display code for one digit through its output pore (END
a vpocss [7 Wes Tt tote AG) he eee A to OUT A3 and OUT BO to OUT B3) and send a scan code through, SLO- : as
1OATTS: - ¥ o> ge fg en ee | ¢ The display code is inverted by segment drivers and aN to segmen a ai
BL, Inc Ta . , te. ; :
ee ht io pe es et Ie a | | | sai
ON the corresponding
oie | " ¢ The scan code s aes Ne " Se aay’ After a small interval (10
Me esi. |. | sd (AIBISIEISIGE driver. Now one digit of the pane’ ned OFF (ie., display
is blanked) and the above
Ss ee par 2 ti bane S13 hh ie St — _ milli-second, typical), the display "Thus multiplexed display is performed by 8279.
SI POR AS Le [a T- EES 300, i ae process is repeated for next = , *
the “ne
return lines, RLO to RLS of 8279 as
Sm 8 irttedee LS pe,
pd [PT pwn.
foyer ha | | eetae * The matrix
keyboard ma is- formed using at nem,
se : Pee _ ©olumns and decode: ee +nt of each row and column.
A key press
rNCee . * Ahexa key
. is placed at ; the allcrossing p®
the column and TOW line ine Wi will be high.
Fig. Keyboarg are | 1 eae _ Short the row and column. Normally
“IsPlay interface with 8085 using 6279. ohne a
 22-2019 | Sixt| h Semester, Micropro
cessors and Microe 0
* During scanning the 82
Ntrolle
79 wil] output bina LF, University-[B.Tech]-Akash Books
by decoder to make a row as i 2019-23
zero. When a row }
there is a key press then thé
corresponding 1 MHz
* If8279 detects a key press
column wil] be zero ie = 1000
then it wait for deb Ounce 1 KHz
columns to generate key co time a Nda Code SEGMENT
de. |
ASSUME CS : Code
MOV AL, 77H.
OUT 86H, AL // Initialize Control word = 0111 0111
Back: MOV AL,OOH ~
OUT 82H,AL // Lower byte of BCD count
MOV AL, 10H
OUT 82H, AL // Upper byte of BCD count
HLT
Code ENDS
END
Q.7. (a) What are the different priority modes available under software
control in 8259 Programmable Interrupt Controller? Briefly explain all. (6)
Ans. Fully Nested Mode: This is the default mode of operation of 8259A. IRO has
the highest priority and IR7 has the lowest one. When interrupt requests are noticed,the
highest priority request amongst them is determined and the vector is placed on the
‘ord m data bus. The corresponding bit of ISR is set and remains set till the microprocessor
2. z The initinialitial count Zee written before the Initial count is issues an EOI command just before returning from the service routine or the AEOI bit
significant byte o |
vere JOllow the count format ¢ | is set. If the ISR (in service) bit is set, all the same or lower priority interrupts are
inhibited but higher levels will generate an interrupt, that will be acknowledged only if
the microprocessor’s interrupt enable flag (IF) is set. The priorities can afterwards be
changed by programming the rotating priority modes.
End of Interrupt (EOD): The ISR bit can be reset either with AEOI bit of ICW1 or
| _ by EOI command, issued before returning from the interrupt service routine. There are
two types of EOI commands specific and non-specific. When 8259A is operated in the
modes that preserve fully nested structure, it can determine which ISR bit is to be reset
on EOT. When nonspecific EOI command is issued to 8259A it will automatically reset
the highest ISR bit out of those already set. When a mode that may disturb the fully
nested structure is used, the 8259A is no longer able to determine the last level
acknowledged. In this case a specific EOI command is issued to reset a particular ISR
bit. An ISR bit that is masked by the corresponding IMR bit, will not be cleared by a
non-specific EOI of 8259A, if it is in special mask mode.
; Q6. (c) Set up 8254
imput frequency to 8 aS a square- Automatic Rotation: This is used in the applications where all the interrupting devices
254 is equal to 1 oe are of equal priority. In this mode, an interrupt request (IR) level receives lowest priority
Ans. Assume selected co epperator With alm S
for counter 1 is 82 H i unter-], after it is served while the next device to be served gets the highest priority in sequence.
Eee Once all the devices are served like this, the first device again receives highest priority.
- Calculation of CWR.
Automatic EOI Mode: Till AEOI = 1 in ICW4, the 8259A operates in AEOI mode.
In this mode, the 8259A performs a non-specific EOI operation at the trailing edge of
CWR is (77H) the last INTA pulse automatically. This mode should be used only when a nested
Calculation of count: multilevel interrupt structure is not required with a single 8259A.
Specific Rotation: In this mode a bottom priority level can be selected, using L2,
L1 and L0in OCW2 and R =1, SL = 1, EOI = 0. The selected bottom priority fixes other
ea N = —/put clock frequen priorities. If IR5 is selected as a bottom priority, then IR5 will have least priority and
Output required freques— These
IR4 will have a next higher priority. Thus IR6 will have the highest priority.
the rotate on specific
priorities can be changed during an EO! command by programming
*
;
ig

EOI command in OCW2 -

 peaSpecial Mask Mode: : in
In special mas . :
ee further interrupts at that level mi aah a mask bit is Set in OCW) ae aaa A ereany
aah is fer
re not masked, errupt from Other ] it : : allows the
| y ° 829 8254 has a powerful called R READ BACK , command, which
command called
Edge and Level Tri beat “vels, Which
be edge triggered or cet tecien ae ore : ecides whether the Interrupt ot. ae ; ie a “ ee ee rent
otherwise the interrupts are level triggered.Re 3 ICWI = 0, they are edge . “should ae eae is
internal registers of 8259A ee Ted. heading 8259 Status T "I88ered, 8254 Pin Description: Here is the pin diagram of 8254.
€ status of the

Poll Comman . IR
though it functions halen i olled moda, |
a wee The poll tor by masking INTs
a2 ae _ using software exe 1 in OCW3. The aoead of
roe e 8259A treats the ad of the requests 3 9A ig
es A a a is set an interrupt acknow\aial

than 64 on to data bus rity level] 1S read and oe |

and th Priority levels. Note that this h ; nd may give ee
ee Priorities _ | 86 interry hit: more
ered Mode: Wh . Pl structure
en the 8259A 1s used in the as
are used on data bus
es ystems where bus dri |
The
e 8 8259A sends buffe ving buffers
: rs exists
couhters placed on the bus
ncluding all the

253/54 areas follows a In the above figure, there are three counters, a data bus buffer, Read/Write control
Cena Be logic, and a control register. Each counter has two input signals - CLOCK & GATE, and
_ | one output signal - OUT.
‘a Data Bus Buffer: It is a tri-state, bi-directional, 8-bit buffer, which is used to
| interface the 8253/54 to the system data bus. It has three basic functions.
a .© Programming the modes of 8253/54.
if - ° Loading the count registers.
|a ¢ Reading the count values. .
eZ Read/Write Logic: It includes 5 signals, i.e. RD, WR, CS, and the address lines A,
__| &A,. In the peripheral I/O mode, the RD and WR signals are connected to IOR and IOW,
MEMW.
a = respectively. In the memorymapped I/O mode, these are connected to MEMR and
| - Address lines A,& A, of the CPU are connected to lines Ay and A, of the 8253/54,
counters are selected
and CS is tied to a decoded address. The control word register and
according to the signals on lines Ay & A,.

a y | 0 0 Counter 0
4 0 1 . Counter 1
: ef 0 Counter 2
1

Control Word Register

4 s

ie 1 ST pic
xX . | x a No Selection -
a
ars | be ti
Control Word Register: This register is accessed when lines Ay & , are ee :
a e | oe : i
ME
Ree : | cm ag | Sgt: oe.
ue «ti —
a command‘+o word, which specifies the counterto be used, » itits mode, and
Deemeh in;
| aan an ueed 2 eee table shows the result for various control
re ad or wr it e op er at io n. Following
Seed either a
“puts, ?
>9
 LP University-[B. Tech]-Akash
Books 2019-27
4, Communication: Cell Phones, Tele
phone Sets, Answering Machines etc
5. Office Equipment: Fax, Printers ete.
|
6. Multimedia Application: Mp3 Player
, PDAs etc.
7. Automobile: Speedometer, Auto-break
ing system etc.
Pee Mes How many 16-bit timers does an 8051 microcontroller
have? Also
explain the different operating modes for
the timers of 8051 microcontroller. (5)
| Ans. Timer: 8051 has two timers Timer0 (TO
) and Timer! (T1), both are 16-bit
wide. They can be used either as timers or as counters.
Both timers fe 16 bits wide
Since 8051 has 8-bit architecture, each of these is accessed
by two separate 8-bit fogistera
as shown in the figure below. These registers are used to
load timer-count. ;
THO |
TLO

pee Tee EN. & B72

D15 b14 | p13 D122| p11;14 | D10| Do! os | pz be |; os | ot | [ 03 | be oz}ant 01 | vo |r
TH1

B15 | B14} p13.) D12| p14| D10/ po | os | pz | vs! ps | ps | 3 | po | Dt | De | r1

z f

805] has Timer Mode Register and Timer Control Register for selecting a mode of
operation and controlling purpose.
Let’s see these registers,
TMOD register: TMOD is an 8-bit register used to set timer mode of timer0 and
timerl.

Timer 1 Timer 0

Gk 6 5 : 4 3 2 1 0

GATE C1/T1 _ M1 MO GATE corto M4 Mo TMOD

Its lower 4 bits are used for Timer0 and upper 4 bits are used for Timer]
Bit 7,3 - GATE:
1 = Enable Timer/Counter only when the INTO/INT! pin is high and TRO/TR1
»is set. |
0 = Enable Timer/Counter when TRO/TR1 is set.
Bit 6,2 - C/T(Counter/Timer): Timer or Counter select bit
1 = Use as Counter
| |
0 = Use as Timer
& 1:0 - M1 :M 0: Ti me r/ Co un te r mode select bit
Bit 5:4
Ti me r/ Co un te r mo de sel ect bit as per below table
These are |
8. Medic ical Instruments: ECG Machine, Accu-Check ete } | de | Operation
) at ; 0 (18-bit timer mode) 13-bit timer/counter, 8-bit of THx
& 5-bit of
| | el o ;? ae
TLx =
 28-2019 Sixth Semeste r Microprocessors and Microcontrollers |
oks -| 2019-29
| University-[B.Tech]-Akash Bo
?

LP.
16-bit timer/counter, THx cascaded with Th
0 1 1 (16-bit timer mode)
: ee
2 os(8-bit auto reload mode)| 8-bit timerr/coun ter (auto reload mod 8), T
-bit time imer Mode 3: :
O an d THO act as two =
; - heave reload with value held by THx each time te | Sp li ts in to tw o 8- bi t co un te r/ timers. TL
Mee 0 re sp ec tively.
overflow | tt in g the TFO an d TF 1
Split 16-bit timerx into two 8-bit time, i: timers with overflows se
Mt timer mode) in mode 3 ):
- Timer 1 (when timer 0 is
Sena: THx and TLx like two 8-bit timer ms
* Counter stopped if in mode 3 9
. . : >
| |
|
;

Timer Modes: Timers have their operation modes which are selected in TMop * Can be used in mode 6, 1, or
register using M0 & M1 bit combinations. (INT1) and ext ern al inp ut (T1), but no fla g or interrupt.
* Has gate
|
Timer Modes Timer Mode 0 (13-bit Timer): ° May be used as a baud rate generator.
- Timer high-byte (THx) is cascaded with the 5 least-significant bits of the timer
low-byte (TLx) to form a 13-bit timer, where x = Qorl. Timer
- Upper 8-bits of TLx are not used. clock
- Overflow occurs on the 1 FFFH-to-0000H and sets the timer overflow flag. |
- MSB is THx bit 7, and LSB is TLx bit 0. | Timer TFO Interrupt
- MOV TMOD, #00H; setting both timers to mode 0 clock ]5 Overflow flag
MAES Bee

‘clock bits Interrupt

+12 F,,..
0 49 7 Overflow | | == Overflow flag
Timer Mode 1 (16-bit Timer): . ues
| aepad in 80 51 for the di vi si on of tw o 8-b it nu mbers. (3.5)
- Same as mode0 except that it is 16-bit. Timer high
Q.8. (c) Write a program this 8051
“

io n to divide tw o 8- bi t nu mbers using

timer low byte (TLx) to form| a 16-bit timer, where x=0Oor
gh-byte (THx) is cascaded the_y | de op
A ns. The divi er at
1. | hi } ‘sterA and B will be used in. thisi opera tion. No other registers
microcontroller. Te orbs result of the division has two parts. The quotient part and
Ie

bea” | Leer
_~ Clock is applied to the combined high and low-byte

2h
»
timer registers. ee G oy
: Overflow occurs on the FFFFH-to-0000H and sets the timer overflow flag. Se can be used Tor (oy RegisterA will hold Quotient, and register andB will21H,holdAfterRemainder.
dividing
- MSB is THx bit 7, and LSB is TLx bit 0. eee ar ee two number0EH and 03H at location 20H
= eg ;
: LSB toggles at clock frequency/2! will be stored at location 30H and 31H.
and MSB at clock frequency/216 the caput
| Address Value
i “

Timer
20H | 0EH
ate

clock Interrupt
03H
4

21H ;
f :
1

: a Pa ‘Overflow
a _ Timer Mode 2 (Auto-Reload): | )
30H 00H
Bx ee aS: 4. | Me 31H | 00H
| Al = oe (TLx) operates as an 8-bit timer while the timer high -byte (THx)
| es ee

a _. _ -When the count | e | ! Program

cov — 0, #20H;set source address 20H to RO
the value in THx is loa
ry

og

x MO V RI. 430H;set destination address 30H to R1

2g eS toe A
mith easeetees vA, @RO;take the first operand from source to regis
em es im a. Point to the next location

we
> *
 30-2019 Sixth Semester, Microprocessors and Microcontrollers ].P. University-[B.Tech|~Akash Books 2019-31
on
INC R1; Increase Ri to point to the next locati ++ 0 — EXO: Enable External0 Interrupt Bit
MOV @R1, B; Store Remainder to 31H F 1 = Enable External0 interrupt
HALT: SJMP HALT ;Stop the program 0= Disable External0 interrupt
8051 provides DI VAB instruction. By using this instruction, the division can be
done. In some other microprocessors like 8085, there was no DIV instruction, In that Interrupt priority
| ned by using interrupt priority register (IP)
rrupt can be assig
ity to the intest
microprocessor, we need to use repetitive Subtraction operations to get the result of the prior!
division. prio rity after Reset:
{Interrupt
When the denominator is00H, the overflow flag OV will be 1. otherwise it is
Interrupt source Intr. bit/ flag
the division.
0 for Priority
External Interrupt 0 INTO
Output 1
Timer Interrupt 0 TFO-
Address Value 9
aa
3 External Interrupt 1
ais
20H 4 Timer Interrupt 1
OEH ( }
5 Serial interrupt eS reset are shown. As per 8051 interrupt
0V* hed with
upts priorities upon 1 anocontrolleris finishe
_In the ae Tie ‘dared are not served Sea are microcontroller queues
priorities, ‘ori
lowe see
es. a case when two or more interrupts
higher priority on
a c c o r d i n g to p r i o r ity.
them
: Explain the interrupt enable regi
Q.9. (a)
ster and interrupt priority control joritpy a regis‘5 teralso -ority lev/e els
possible to: change the priority jority
register in case of 8051 microcontr IP Register: Interrupt Ra
oller, | iori ister ;
bi ‘+ in the Interrupt price
|
pe clearing the corresponding
of theinterne
interrupts Dy §
t h e fi gure. . Thi11s S
s h o w n 1D
(IP) register as ty interrupt bu -annot be int err upt ed. I f these ininterrupt
t
the high-pr ority 1
ex ec ut es 10 pr ed ef in e d manner and
mi la rl y, th e hi gh -p ri jor
or ityity in ma ter™ ™ o ller
register, bit corresponding in te rr up t. Si , e m i c ro tr
c o n
ogra m m e d th
the interrupt. - priorities are not pr T 1 , T F 1 , a n d SI.
to interrup
IE register: Interrupt Enable | r is I N T O , T F O , I N : ri or it y s
Register its orde gi ster to o o : P
IE register is used to enable in te rr upPpt priority re
3
/disable interrupt sources. 8051 has 1n x0 IP
PX1 PTO P 5
7 6 win S : :
6 5 7 : PTi
4 3 2 . pS
1 0
EA — — ES ET1
—

EX4 ETO
—

EXO
Bit 7 - EA: Enable All Bit bits.
-/ IE
? i 5- Reserved te a
1 = Enable al] interrupts
. ees ae
| erafee Serial Interrup‘oritt y to s
0 = Disable all interrupts
Bit 6,5 - Reserved bits low priority to ser-oritialy Bi oe
_ Bit 4- ES: Enable Serial Inte ten pe
me r! In t Prio
terrupty nty Ee
rrupt Bit i
Bit 3 es pT 1: Ti
oan high priori to Timer
| 1 = Enable serial interrupt
0 = Disable seria] interrupt . . Bit “

st 3 _ Bit 3-ET1: Enable Timer

0

Interr pt 1 Priority
Interrupt Bit . External e r r upt.
peasy 1 = Enable Timer1 interrupt «Bit 2- PX p r i o r i t y t o Extern a l 1 i n t
h
1 = Assign hig
0 = Disable Timer1 interrupt
ore. Bit 2 ~ EX1: Enable External
hae ee

] Interrupt Bit
jae 1 = Enable External] interrupt
_-- -., 0 = Disable Extern
a

al! interrupt
i iy i Bit 1 - ETO: Enable Timer0 Interrupt
Bit
1 = Enable Timer0 interrupt -ority to External0 interrupt
0 = Disable Timer( interrupt - to External0 interrupt:
 s an d Mi cr oc on tr o ll er s
Sixth Se me st er , Mi cr op ro ce ss or
32-2019 pores dio “dais
addressing: mo 7
w e e te r indirect
Q.9. (b) Differentiate be t r o c o n tr ol le r (b y g i v i n g s u i t a b l e
d d r e s s i n g m o d e u s e dBy byB O
80S E
51 : m i c
: mmediate a (5.5)
examples of both).
Ad dr es si ng mo de s of 80 51 )
Ans.
mo de : In th is ty pe , th e op er and ae in Noe
1. Immediate ad dr es si ng
e op co de . In si mp le wa y, it me an s da ta is pr ov id ed 1n instruc on
instruction along with th
| ee |
itself.
V A, #0 5H -> Wh er e MO V st an ds for mo ve , # re pr es en ts im me di ate data.
Ex: MO
05h is the data. It means the immediate date 05h provided in instruction is moved into
A register.
2.Register addressing mode: Here the operand in contained in the specific register
of microcontroller. The user must provide the name of register from where the operand/
data need to be fetched. The permitted registers are A, R7-RO of each register bank. Ex: .
MOY A,RO-> content of RO register is copied into Accumulator. ai.
3. Direct addressing mode: In this mode the direct address of memory location is
provided in instruction to fetch the operand. Only internal RAM and SFR’s address can. 7
4
be used in this type of instruction. |
Ex: MOV A, 30H => Content of RAM address 30H is copied into Accumulator.
4. Register Indirect addressing mode: Here the address of memory location is
indirectly provided by a register. The“@’ sign indicates that the register holds the add
ress
of memory location i.e. fetch the content of m emory location whose address is
provided, :
in register. | | :
Ex: MOV A,@RO => Copy the content of memory location whose addr
ess is givenin -
RO register.
9°. Indexed Addressing mode:

Ex: MOVC A,@A+DPTR => here ‘C’ means Code. Here

with content of DPTR and the resultant is the address
the data is copied to A register.