Experiment 2

Aim: To design all the logic gates using VHDL language in Data flow style of
modeling.

Software Used: Xilinx ISE

Theory : Logic gates are the basic building blocks of any digital system. It is an
electronic circuit having one or more than one input and only one output. The
relationship between the input and the output is based on a certain logic.
Based on this, logic gates are named as AND gate, OR gate, NOT gate etc.

Code For Logic Gate

1. OR Gate
Program :

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity or1 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end or1;
architecture Behavioral of or1 is
begin
c <= a or b ;
end Behavioral;

Truth Table:
a b c
0 0 0
0 1 1
1 0 1
1 1 1

RTL Schematic:

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 Behavioral Waveform:

2. AND Gate

Program:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity and1 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end and1;
architecture Behavioral of and1 is
begin
c <= a and b ;
end Behavioral;
Truth Table:
a b c
0 0 0
0 1 0

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 1 0 0
1 1 1

RTL Schematic:

Behavioral Waveform:

3. NOT Gate

Program:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity not1 is
Port ( a : in STD_LOGIC;
b : out STD_LOGIC);
end not1;
architecture Behavioral of not1 is
begin
b<= not a ;
end Behavioral;
Truth Table:
A b
0 1
1 0

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 RTL Schematic:

Behavioral Waveform:

4. NAND Gate

Program:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entitynand1 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end nand1;
architecture Behavioral of nand1 is
begin
c <= a nandb ;
end Behavioral;
Truth Table:
a b c
0 0 1

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 0 1 1
1 0 1
1 1 0

RTL Schematic:

Behavioral Waveform:

5. NOR Gate

Program:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entitynor1 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
endnor1;
architecture Behavioral of nor1 is
begin
c <= a nor b ;
end Behavioral;

Truth Table:

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 a b c
0 0 1
0 1 0
1 0 0
1 1 0

RTL Schematic:

Behavioral Waveform:

6. XOR Gate

Program:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.

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 --library UNISIM;
--use UNISIM.VComponents.all;
entityxor1 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
endxor1;
architecture Behavioral of xor1 is
begin
c <= a xorb ;
end Behavioral;

Truth Table:
a b c
0 0 0
0 1 1
1 0 1
1 1 0

RTL Schematic:

Behavioral Waveform:

7. XNOR Gate

Program:

library IEEE;

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 use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entityxnor1 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
endxnor1;
architecture Behavioral of xnor1 is
begin
c <= a xnorb ;
end Behavioral;

Truth Table:
a b c
0 0 1
0 1 0
1 0 0
1 1 1

RTL Schematic:

Behavioral Waveform:

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 Experiment 3
Aim: Design a half adder and full adder using VHDL language in Data flow
style of modeling.

Software Used: Xilinx ISE.

Theory:

An adder is a digital logic circuit in electronics that implements addition of

numbers. In many computers and other types of processors, adders are
used to calculate addresses, similar operations and table indices in the ALU
and also in other parts of the processors. These can be built for many
numerical representations like excess-3 or binary coded decimal. Adders
are classified into two types: half adder and full adder. The half adder circuit
has two inputs: A and B, which add two input digits and generate a carry
and sum. The full adder circuit has three inputs: A and C, which add the
three input numbers and generate a carry and sum. This article gives brief
information about half adder and full adder in tabular forms and circuit
diagrams.
1. Half Adder
An adder is a digital circuit that performs addition of numbers. The half
adder adds two binary digits called as augend and addend and produces
two outputs as sum and carry; XOR is applied to both inputs to produce
sum and AND gate is applied to both inputs to produce carry. The full
adder adds 3 one bit numbers, where two can be referred to as
operands and one can be referred to as bit carried in. And produces 2-bit
output, and these can be referred to as output carry and sum.
Now it has been cleared from truth table of half adder that 1-bit adder
can be easily implemented with the help of the XOR Gate for the output
‘SUM’ and an AND Gate for the ‘Carry’. When we need to add, two 8-bit
bytes together, we can be done with the help of a full-adder logic. The
half-adder is useful when you want to add one binary digit quantities. A
way to develop a two-binary digit adders would be to make a truth table
and reduce it. When you want to make a three binary digit adder, do it

DER (EEE-6TH) 12
 again. When you decide to make a four digit adder, do it again. The
circuits would be fast, but development time is slow.
Program:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity hafadder1 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
s : out STD_LOGIC;
c : out STD_LOGIC);

end hafadder1;
architecture Behavioral of hafadder1 is
begin
s <= a xorb ;
c<= a and b;
end Behavioral;

Truth Table:

a b s c
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
RTL Schematic:

Behavioral Waveform:

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 2. Full Adder
This adder is difficult to implement than a half-adder. The difference
between a half-adder and a full-adder is that the full-adder has three
inputs and two outputs, whereas half adder has only two inputs and two
outputs. The first two inputs are A and B and the third input is an input
carry as C-IN. When a full-adder logic is designed, you string eight of
them together to create a byte-wide adder and cascade the carry bit
from one adder to the next.
With the truth-table, the full adder logic can be implemented. You can
see that the output S is an XOR between the input A and the half-adder,
SUM output with B and C-IN inputs. We take C-OUT will only be true if
any of the two inputs out of the three are HIGH.
So, we can implement a full adder circuit with the help of two half adder
circuits. At first, half adder will be used to add A and B to produce a
partial Sum and a second half adder logic can be used to add C-IN to the
Sum produced by the first half adder to get the final S output.
If any of the half adder logic produces a carry, there will be an output
carry. So, COUT will be an OR function of the half-adder Carry outputs.
Take a look at the implementation of the full adder circuit shown below.
The implementation of larger logic diagrams is possible with the above
full adder logic a simpler symbol is mostly used to represent the
operation. Given below is a simpler schematic representation of a one-
bit full adder.
Program:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating

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 ---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity fuladder1 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
cin : in STD_LOGIC;
s : out STD_LOGIC;
cout : out STD_LOGIC);

endfuladder1;
architecture Behavioral of fuladder1 is
begin
s <= a xor bxorcin ;
cout<=( a and b) or (b and cin ) or (cin and a);
end Behavioral;

Truth Table:

a b Cin sum cout

0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
RTL Schematic:

Technology:

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 Behavioral Waveform:

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 Experiment 4
Aim: Design half subtractor and full subtractor using VHDL language in Data
flow style of modeling.

Software Used: Xilinx ISE.

Theory:
1. Half Subtractor
A combinational circuit which performs the subtraction of two bits is called half
subtractor. The input variables designate the minuend and the subtrahend bit,
whereas the output variables produce the difference and borrow bits.

Program:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity hafadder1 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
D : out STD_LOGIC;
Bo : out STD_LOGIC);

end hafadder1;
architecture Behavioral of hafadder1 is
begin
D<= a xor b;
Bo <= not a and b;
end Behavioral;

Truth Table:

a b D B
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

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 RTL Schematic:

Technology:

Behavioral Waveform:

2. Full Subtractor
A combinational circuit which performs the subtraction of three input bits is called
full subtractor. The three input bits include two significant bits and a previous
borrow bit. A full subtractor circuit can be implemented with two half subtractors
and one OR gate.

Program:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.

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 --library UNISIM;
--use UNISIM.VComponents.all;
entity hafadder1 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
D : out STD_LOGIC;
Bout : out STD_LOGIC);

end hafadder1;
architecture Behavioral of hafadder1 is
begin
D<= a xor bxorc ;
Bout <=((not a) and b) or (b and c ) or (c and (not a));
end Behavioral;

Truth Table:

a b c D Bout
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

RTL Schematic:

Technology:

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 Behavioral Waveform:

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 Experiment 5
Aim: Design 4:1 Multiplexer and 1:4 Demultiplexer using VHDL language in
Data flow style of modeling.
1. 4:1 Multiplexer

Program:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity mux1 is
Port ( asl : in STD_LOGIC;
bsl : in STD_LOGIC;
A : in STD_LOGIC;
B : in STD_LOGIC;
C: in STD_LOGIC;
D: in STD_LOGIC;
Q: out STD_LOGIC);

end mux1;
architecture Behavioral of mux1 is
begin
Q <= (not(asl and bsl) and A) or ((not asl) and bsl and B) or (asl and (not bsl) and C) or (asl and bsl
and D);

end Behavioral;

Truth Table:

B(slt line) a(slt line) D C B A Q(op)

0 0 x x x 1 1
0 1 x x 1 x 1
1 0 x 1 x x 1
1 1 1 x x x 1

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 RTL Schematic:

Technology:

Behavioral Waveform:

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 2. 1:4Demultiplexer

Program:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entitydemultipx is
port (p : in std_logic;
q : out std_logic_vector (3 downto 0);
r : in std_logic_vector (1 downto 0));
enddemultipx;

architecture Behavioral of demultipx is

begin
process(p,r)
begin
case r is
when"00"=>
q(0)<=p;
when"01"=>
q(1)<=p;
when"10"=>
q(2)<=p;
when others=>
q(3)<=p;
end case;
end process;
end Behavioral;

Truth Table:

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 RTL Schematic:

Technology:

Behavioral Waveform:

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 Experiment 6
Aim: Design RS and JK flip-flops using VHDL language in Behavioral style of
modeling.
1. R-S Flip flop:

Program:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entityff_rs is
Port ( R : in STD_LOGIC;
S : in STD_LOGIC;
clock : in STD_LOGIC;
clr : in STD_LOGIC;
preset : in STD_LOGIC;
Q : out STD_LOGIC;
Qbar : out STD_LOGIC);
endff_rs;

architecture Behavioral of ff_rs is

begin
P1: PROCESS(clock,clr,preset)
variable x:std_logic;
begin
if(clr='0')then
x:='0';
elsif(preset='0')then
x:='1';
elsif(clock='1' and clock'event)then
if(S='0' and R='0')then
x:=x;
elsif(S='1' and R='1')then
x:='Z';
elsif(S='0' and R='1')then
x:='0';
else
x:='1';
end if;
end if;
Q<=x;
QBAR<=not x;

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end PROCESS;

end Behavioral;
Truth Table:

Behavioral Waveform:

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 Technology:

Waveform:

2. J-K Flip flop:

Program:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entityjkff is
Port( clock: in STD_LOGIC;
j: in STD_LOGIC;
k: in STD_LOGIC;
reset: in STD_LOGIC;
q: out STD_LOGIC;
qbar: out STD_LOGIC);
endjkff;

architecture Behavioral of jkff is

signal state: std_logic;

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signal input: std_logic_vector(1 downto 0);
begin
--combine inputs into vector
input<= j & k;
p: process(clock,reset)is
begin
if(reset='1') then
state<='0';
elsif(rising_edge(clock)) then
--compare to the truth table
case(input) is
when"11"=>
state<=not state;
when"10"=>
state<='1';
when"01"=>
state<='0';
when others =>
null;
end case;
end if;
end process;
-- concurrent statements
q<= state;
qbar<= not state;
end Behavioral;
Truth Table:

Behavioral Waveform:

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Technology:

Waveform:

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 Experiment 7
Aim:To design an encoder and a decoder using VHDL language in behavioral
style of modeling.

1. Encoder:
Encoders are digital ICs used for encoding. By encoding, we mean generating a digital
binary code for every input. An Encoder IC generally consists of an Enable pin which
is usually set high to indicate the working. It consists of 2^n input lines and n output
lines with each input line being represented by a code of zeros and ones which is
reflected at the output lines.

Program:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity encoder is
Port ( i : in STD_LOGIC_VECTOR (07 downto 0);
en : in STD_LOGIC;
o : out STD_LOGIC_VECTOR (02 downto 0));

end encoder;

architecture Behavioral of encoder is

begin
process(i)
begin

if (en='1') then
case (i) is
when "00000001"=>o<="000";
when "00000010"=>o<="001";
when "00000100"=>o<="010";
when "00001000"=>o<="011";
when "00010000"=>o<="100";
when "00100000"=>o<="101";
when "01000000"=>o<="110";
when "10000000"=>o<="111";
when others=>o<="---";
end case;
else

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 o<="---";

end if;
end process;
end Behavioral;
RTL Schematic:

Technology:

Waveform:

2. Decoder:

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 Decoders are digital ICs which are used for decoding. In other words the decoders
decrypt or obtain the actual data from the received code, i.e. convert the binary
input at its input to a form, which is reflected at its output. It consists of n input lines
and 2^n output lines. A decoder can be used to obtain the required data from the
code or can also be used for obtaining the parallel data from the serial data received.

Program:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity decoder is
Port ( i0 : in STD_LOGIC;
i1 : in STD_LOGIC;
i2 : in STD_LOGIC;
en : in STD_LOGIC;
y : out STD_LOGIC_VECTOR (07 downto 0));
end decoder;

architecture Behavioral of decoder is

--signal i0bar,i1bar,i2bar:std_logic;
begin
process(i0,i1,i2)
variable i0bar,i1bar,i2bar:std_logic;
begin
i0bar:= not i0;
i1bar:= not i1;
i2bar:= not i2;
if (en='1') then
y(0)<=i0bar and i1bar and i2bar;
y(1)<=i0bar and i1bar and i2;
y(2)<=i0bar and i1 and i2bar;
y(3)<=i0bar and i1 and i2;
y(4)<=i0 and i1bar and i2bar;
y(5)<=i0 and i1bar and i2;
y(6)<=i0 and i1 and i2bar;
y(7)<=i0 and i1 and i2;
else
y<="00000000";
end if;
end process;
end Behavioral;

RTL Schematic:

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Technology:

Waveform:

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