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Course Curriculum
FPGA/CPLD BASICS
Part I & Part II

1
FPGA Basics
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FPGA/CPLD BASICS – PART 1

Introducton to FPGA
FPGA Architecture
FPGA Working
CPLD
CPLD Architecture

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FPGA/CPLD BASICS
Who should use FPGA /CPLD
• Students & Researchers
• Industry professionals
• Amateur designers
Why use FPGA/CPLD (ADVANTAGES)
• Re-Programmable
• Quick Design Implementaton
• Cheap (ASICs are cheaper if produced in bulk)
• Flexible & afordable
• Small Design over-head
• FUN to design with and use

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FPGA/CPLD BASICS
Where FPGA /CPLD can be used
• Embedded
• Defense, Research and Aerospace
• Biomedical Applicatons
• Automobiles
• Small Projects
• Communicaton
Prerequisites for using FPGAs
• Verilog HDL or VHDL
• Digital Design Basics

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FPGA/CPLD BASICS
Slides Organizaton:

Session 1 – FPGA

Session 2 – CPLD

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FPGA BASICS

Session 1

FPGA
Field Programmable Gate Array

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FPGA BASICS
• Idea Behind FPGA
select

0
1
1
0 MUX
1 FF
0
0
Simplifed view 1
Programmable
Memory

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FPGA BASICS
• Idea Behind FPGA
• the output functonality is stored in LUT
• the Multplexor selects LUT output
• another multplexor selects the output to be
combinatorial or sequental

• Distributed memory elements store the interconnect

confguraton informaton
• This confguraton controls the interconnects among
wires and the confgurable logic/arithmetc blocks

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FPGA BASICS
• FPGA Internal Architecture View(General)

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FPGA BASICS
• Inside FPGA

• Basic Components
• LUT (look-up-table)
• Flip-Flops
• Multplexors
• I/O Blocks
• Programmable switch matrices
• Interconnect
• Clocks

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FPGA BASICS
• Xilinx - Logic/Arithmetc Consttuton

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FPGA BASICS
• Xilinx FPGA Internal View

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FPGA BASICS
• Xilinx FPGA CLB (Confgurable Logic Block)

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FPGA BASICS
• Xilinx FPGA - CLB inside, the pair of slices

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FPGA BASICS
• Xilinx FPGA - CLB Detailed view

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FPGA BASICS
• Xilinx FPGA - CLB I/O connectons

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FPGA BASICS
• Xilinx FPGA -CLB I/O connecton detailed

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FPGA BASICS
• Xilinx FPGA - Switch Matrix
programmable switch
element

turning the corner, etc.

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FPGA BASICS
• Xilinx FPGA - I/O block

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FPGA BASICS
• Example - LUT – Luck-Up Table
The functon is stored in RAM like a Truth Table

LUT for Sum: Adder Truth Table

input[0:2] 0 MUX confg_out

1
1
0
1 output
0
clock 0
1
confg_in

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FPGA BASICS
• Example - Modulo-4 Counter

Logic
State Diagram Implementaton

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FPGA BASICS
Xilinx FPGA - CLB inside, the pair of slices

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FPGA BASICS
• FPGA Selecton

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FPGA BASICS
• Variatons
Xilinx Spartan II Altera Stratx

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CPLD BASICS

Session 2

CPLD
Complex Programmable Logic Device

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CPLD BASICS
• CPLD Architecture - General Internal View
Altera MAX CPLD
I/O Cell
LAB (Logic Array Block)

LAB LAB
LA

•••
LAB LAB (local
array)
LAB LAB

Macroccell
Chip-wide
interconnect Each LAB contains
16 macro-cells

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CPLD BASICS
• Xilinx CPLD architecture

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CPLD BASICS
• Functonal Architecture
90 product terms
5 per macro-cell
Product-term allocators

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CPLD BASICS
• CPLD Macro-cell

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CPLD BASICS
• CPLD I/O block

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CPLD BASICS
• CPLD Selecton Comparison

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FPGA/CPLD BASICS
• FPGA v/s CPLD
FPGA CPLD
1. FPGAs can be used in various 1. Implement random glue logics
applicatons: prototyping, or Replace circuits previously
FPGA-based computers, on-site implemented by multple SPLDs
hardware re-confguraton, DSP,
logic emulaton, network 2. Circuits that can exploit wide
components, etc. AND/OR gates, and do not need

Gate Count 10,000 ~ 10,00,000 a very large number of fip-fops

and above
are good candidates for
implementaton in CPLDs.

Gate Count 200 ~ 12,000

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FPGA/MC BASICS
• FPGA v/s Microcontroller
Micro-controller
Meant to perform only control
routnes for other h/w
Well defned hardware and
connecton
FPGA
Can perform virtually any digital
logic/arithmetc operaton, even a
uController or uProcessor
Operaton is hardware
reconfgurable

Less fexible and can normally Although rest of the hardware is

perform one type of functon at a somewhat well defned but
tme. connectons are not well-defned.

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FPGA/MC BASICS
• FPGA v/s Microcontroller ….
Micro-controller
Operaton is based on instructons
and the instructons are executed
one afer the other
Generally, moderately fast
FPGA
More fexible and can be
confgured so that diferent blocks
perform diferent functons
Generally, very fast.

Consumes less power Consumes comparatvely more power

Are readily available for many Development tme is quite long

applicatons so the tme for
development is very short

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FPGA/ASIC BASICS
• FPGA v/s ASIC ….
ASIC FPGA
Highly efcient in terms of area- Less efcient in terms of area-
power-performance power-performance
High cost when NOT produced in bulk. Cost could be high if compared with
Cost can be signifcantly less if made in bulk ASIC producton.
Very large quanttes. Otherwise, it is cheaper.
Can not be re-programmed Re-programmable:
100,000 tmes for the fash memory
1 million tmes for nand FPGA without
error correcton.
More than 1 million tmes for nor FPGA

without error correcton.

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FPGA/ASIC BASICS
• FPGA v/s ASIC ….
ASIC FPGA
Highly efcient in terms of area- Less efcient in terms of area-
power-performance power-performance
High cost when NOT produced in bulk. Cost could be high if compared with
Cost can be signifcantly less if made in bulk ASIC producton.
Very large quanttes. Otherwise, it is cheaper.
Can not be re-programmed Re-programmable:
100,000 tmes for the fash memory
1 million tmes for nand FPGA without
error correcton.
More than 1 million tmes for nor FPGA
without error correcton.

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FPGA/ASIC BASICS
• FPGAs/ASIC
Cost

FPGA FPGA FPGA

Cost Advantage
Cost Cost Advantage
Advantage ASIC Cost
ASICAdvantage
Cost Advantage
Production Volume

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FPGA BASICS
• FPGAs Evoluton - What has happened

• In the beginning FPGAs were mere logic gates, multplexers and

reconfgurable interconnects.

• Over tme, numerous additons has made it a heavy-weight on

steroids.
-Dedicated Memories & clock management
-Hard Cores
-I/O blocks
-Dedicated Signal Processing Cores
-Advanced CMOS manufacturing

• And now, we have FPGA chips in market performing at par with

ASICs

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FPGA/CPLD BASICS
• FPGAs Future

• FPGA CPUs – Acrhonic Intel Confgurable Atom processor!

• Massive arrays of FPGAs to implement supercomputers
• FPGAs for reconfgurable GPUs
• Large Embedded Systems
• Reconfgurable network felds

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References
• Some graphics from “ELEC 311 Digital Logic and Circuits”
ppt’s, Dr. Ron Hayne The Citadel Department of Electrical
and Computer Engineering.
• “FPGA Architecture: Survey and Challenges” by Ian Kuon,
Russell Tessier, and Jonathan Rose, now Publishers Inc.

Books

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Disclaimer

All the copyrighted graphics are the property of their legal owners.

Some graphics from The Citadel Department of Electrical and Computer

Engineering.

Other images Courtesy, John F. Wakerly and Prentiee-all

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