Professional Documents
Culture Documents
Fall 2015
Executive Summary
In this report a partially existing On Board Controller (OBC) for a Cubesat is reevaluated
with concern to choice of microcontroller and external memories. As a first step toward
this, a strategy for documentation of various specifications for the satellite is presented
and a functional requirement as well as a non-functional requirement specification for the
On Board Computer is created and discussed. Various microcontrollers are then evaluated
for the OBC and the currently used UC3-family microcontroller is deemed as the most
appropriate as it has no critical shortcomings and offers the shortest time to completion
due to the already implemented code base. The author therefor recommends that the main
microcontroller is not changed unless the bus interface does. The author does also argue
for replacing the SRAM of the OBC with a more radiation resistant MRAM.
The paper then discusses how the functional requirements can be satisfied, and presents
a software architecture for this purpose. The service contract of the OBC should be out-
lined in order to further establish the way other satellite systems can interact with the OBC.
The report ends with a general discussion of the work that has been done, the lessons
learnt, and what the future might hold for this project.
i
Problem
The current focus of the NUTS project is to finish the design and build hardware for an
integrated engineering model. Through this project, the student should focus on the top-
level system design in general, with particular focus on the choice of Microcontroller Unit
(MCU) and its software for the on-board computer subsystem.
The OBC is one of the principal components of the satellite, and is able to control the
rest of the system by granting or denying subsystems access to power and the databus.
Other OBC tasks include logging of system parameters in addition to preparing and read-
ing data transmitted to and from the communication systems.
The OBC must be designed to be reliable, as maintenance is impossible after launch. Chal-
lenges due to the space environment, such as temperature cycles, radiation environment
and vacuum must be identified and discussed. In areas where mitigation of such problems
is possible, solutions should be presented. Whether the solutions be implemented should
be based on a cost/benefit analysis.
ii
Table of Contents
Executive Summery i
Problem ii
Table of Contents iv
List of Tables v
List of Figures vi
Acronyms vii
1 Introduction 1
1.1 Project Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 The NTNU Test Satellite . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.3 The Purpose of the OBC . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.4 The Approach Taken in this Report . . . . . . . . . . . . . . . . . . . . . 3
2 Background 4
2.1 Reliability Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1.1 Reliability, Failures and Errors . . . . . . . . . . . . . . . . . . . 4
2.2 Space Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2.1 Space Radiation . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2.2 Total Ionizing Dose . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2.3 Single Event Effects . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Earlier Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 Requirement Specification 11
3.1 What Are Requirement Specifications and Why Are They Important? . . 11
3.2 Satellite Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3 NUTS Specification System . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3.1 Creating a Requirement Specification . . . . . . . . . . . . . . . 12
iii
3.3.2 Naming Convention . . . . . . . . . . . . . . . . . . . . . . . . 13
3.4 OBC Functional Requirements . . . . . . . . . . . . . . . . . . . . . . . 15
3.4.1 Satellite Initialization . . . . . . . . . . . . . . . . . . . . . . . . 15
3.4.2 Satellite Housekeeping . . . . . . . . . . . . . . . . . . . . . . . 15
3.4.3 OBC Executables . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.4.4 Satellite Executables . . . . . . . . . . . . . . . . . . . . . . . . 17
3.5 OBC Non-Functional Requirements . . . . . . . . . . . . . . . . . . . . 18
3.6 Determining the Complexity . . . . . . . . . . . . . . . . . . . . . . . . 18
3.7 Estimating the Size, Weight, and Power . . . . . . . . . . . . . . . . . . 19
5 Software Architecture 34
5.1 The Software Frameworks . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.2 The Software Architecture . . . . . . . . . . . . . . . . . . . . . . . . . 35
6 Reflections 36
6.1 Further Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Bibliography 37
iv
List of Tables
v
List of Figures
vi
Acronyms
vii
SEGR Single Event Gate Rupture.
SW Software.
viii
Chapter 1
Introduction
In this chapter, the reader will be introduced to the Norwegian University of Science and
Technology (NTNU) Test Satellite project, as well as the scope of this report.
1
• Payload Camera
• Communication subsystem
• Antenna
• Mechanical Structure
The EPS is connected to solar panels and batteries, and is responsible for supplying the
power bus with enough electrical power to drive the satellite. The ADCS is entrusted
with the de-tumbling and pointing of the satellite. A communication subsystem is im-
plemented as a backplane and is used as a power and communication bus so that module
cards easily can be plugged in an out without disassembling the whole satellite. The satel-
lite is equipped with both a UHF radio and a VHF radio so that failures in one radio will
not cause a mission failure. When it comes to the mechanical structure, this project has
decided not to use the standard aluminium frame but rather aims to utilize composite ma-
terials (carbon fiber/epoxy). Although some minor components have been made of carbon
fiber in the past, launching a CubeSat with an all-composite primary structure has not yet
been done. As a gateway between the radios and the satellite bus, is the OBC.
2
level, and sets the satellite state appropriately. In addition to this the OBC also acts as
a gateway between the satellite bus, and the radio link to ground station. The satellite is
designed as a distributed system with redundant functionalities implemented in different
modules. The OBC has a sister microcontroller at the UHF Radio module, with a very
similar hardware and software setup. OBC functionalities are therefore also implemented
in the UHF Radio module. The two modules rely on cold redundancy, meaning that only
one of the modules will take the role as an OBC at a time. Both UC3 microcontrollers
are connected to a Joint Test Action Group (JTAG) standard bus, and have the ability to
reprogram the other MCU if necessary.
A software architecture that might satisfy the requirement specification will be presented
and the service contract it will conform to, for the rest of the system, will be presented.
Lastly, a reflection chapter is added to reflect on what has been done and what is next for
this project. The road map can be seen below.
3
Chapter 2
Background
This chapter aims at presenting some of the terms and definitions that will be used when
discussing reliability and space radiation effects on electronics throughout this report.
There is also included a short summery of the most notable contributions to the OBC in
order to give the reader an understanding of what work already has been done concerning
the OBC.
Reliability is by Randell et al. defined to be a measure of the success with which a system
conforms to some authoritative specification of its behavior [9]. For a satellite launched
into orbit, reliability is of particular importance as repair after launch will not be feasible,
or at least not economically within the budgets for the NUTS satellite. Before proceeding
to how reliability may be achieved, it is important to define some further terms as to avoid
any misconceptions or misunderstandings.
4
Figure 2.1: The fault, error, failure, fault chain
The relationship between fault, error and failure can be seen in Figure 2.1. In addition to
these terms it is common to distinguish three types of faults; permanent, intermittent or
transient [10]. These terms are defined as below:
• Permanent describes a failure or fault that is continuous and stable; in hardware,
permanent failures reflect an irreversible physical change. An example is a bitflip in
the program memory, a broken wire or a software design.
• Intermittent describes a fault that is only occasionally present due to unstable hard-
ware or varying hardware or software states (e.g. as a function of load or activity)
• Transient describes a fault resulting from temporary environmental conditions. It
only remains in the system for a limited period of time before disappearing. They
can be dormant during all their lifetime (which means that they do not generate an
error), or can activate at some point (inducing an error). An example of such faults
is a bit-flip in a RAM memory.
The different categories of faults and their origins can be seen in Figure 2.2.
Figure 2.2: Sources of errors and service failures as presented in Reliable Computer Systems [1].
5
2.2 Space Environment
This section aims to give the reader a short introduction to some of the important concepts
and definitions concerning space radiation and the effects space radiation can have on
electronics.
Radiation in space is produced by particles emitted from either the sun (solar radiation) or
from outside of the solar system, Galactic Cosmic Rays (GCRs). Radiation effects from
these solar and galactic emitted particles can not only cause degradation, but can also cause
failure of the electronic and electrical systems in space vehicles or satellites.
The two most common metrics used when talking about space radiation and electronics are
the effect of the radiation, and the absorbed radiation dose. The effect of the radiation can
be expressed by it’s Linear Energy Transfer or LET, which is expressed in M eV ·cm2 /mg.
The radiation LET describes how much energy an ionising particle transfers to the material
transversed per unit distance [13]. The material in question is usually Si for MOS devices
[14].
When it comes to the absorbed radiation dose, this is usually expressed in rad, where
one rad is equal to 0.01 joule per kg matter. The material is always specified in parenthe-
ses, e.g., rad(Si). However the international system of units (SI) uses gray ”GY”, where
1 GY = 100 rads. Due to the repeated use of rad(Si) in the bibliography for this paper,
rad(Si) will be used as the main metric for absorbed radiation.
6
One can by investigating the radiation toughness of components get an understanding
of the failure rate one might expect. When categorizing components base on radiation
tolerance, three categories are usually used; commercial, rad tolerant, and rad hard. The
characteristics parented in the list below are all gathered from NASA [15].
Commercial:
• Process and Design limit the radiation hardness
• No lot radiation controls
• Hardness levels:
– Total Dose: 2 to 10 krad (typical)
– SEU Threshold LET: 5 MeV/mg/cm2
– SEU Error Rate: 10−5 errors/bit-day (typical)
• Customer performs rad testing, and assumes all risk
• Customer evaluation and risk
Rad Tolerant:
• Design assures rad hardness up to a certain level
• No lot radiation controls
• Hardness levels:
– Total Dose: 20 to 50 krad (typical)
– SEU Threshold LET: 20 MeV/mg/cm2
– SEU Error Rate: 10−7 - 10−8 errors/bit-day
• Usually tested for functional fail only, risky
• Customer evaluation and risk
Rad Hard:
• Designed and processed for particular hardness level
• Wafer lot radiation tested
• Hardness levels:
– Total Dose: >200 krad to >1 Mrad
– SEU Threshold LET: 80-150 MeV/mg/cm2
– SEU Error Rate: 10−10 - to 10−12 errors/bit-day
NUTS, as most CubeSats mostly apply commercial of-the-shelf (COTS) components and
thus faces some serious risks of various radiation induced errors. A short introduction to
the most common effects will now be presented.
According to NASA the expected radiation levels in Low Earth Orbit for higher incli-
7
nations (20-85 degrees) is to be about 1 − 10krad(Si)/year [15], and typical total dose
failure levels of microprocessors at 15-70 krad(Si) [12]
Name Effect
Single Event Transient (SET) Soft intermittent fault Propagating through cir-
cuit.
Single Event Upset (SEU) Soft transient fault State change on latch or
memory.
Single Event Latchup (SEL) Apparent short circuit Can be mitigated with
power cycling Can cause destructive thermal
runaway.
Single Event Gate Rupture (SEGR) Permanent failure.
Single Event Burnout, SEB Permanent failure.
material of the radiation that will trigger SEU events. The energy of most comic rays
range between 100 − 10000M eV · cm2 /mg [17], and as seen earlier the expected SEU
error rate for COTS in LEO is by NASA estimated to be around 10−5 error/bit per day.
This s of course a rough number as it doesn’t even mention for what type of memory it
is applicable. It does however give some understanding to in what magnitude errors can
be expected. If we assume this error rate is correct, a 128 kB of RAM would for instance
experience around 10 errors accumulated per day in orbit [12].
8
Memory management and error handling in FreeRTOS for a CubeSat project - Diaa
Jadaan
Jadaan explains the different memory management schemes in FreeRTOS, as well as how
stack overflows can be detected. The paper also investigates how an exception handling
framework, Exceptions4c, can be used for exception handling in POSIX-based systems.
Jadaan states that in order for this to be useful in FreeRTOS porting is needed, but that this
is a complicated task that he was not able to finish within the timeframe given. The paper
also states that RAID 4 techniques can be used for error detection for embedded systems,
and a small demonstration is written in C++.
Implementing CSP over I2C for the new repository on the NTNU Test Satellite -
Erlend Riis Jahren
Jahren imports the Cubesat space protocol library into the NUTS project and implements
the NUTS Reliable Protocol on top of it. He also tests the various functionalities rather ex-
tensively and discusses the results. Jahren states in the report that ”almost all of the mem-
ory is already used in the FreeRTOS, CSP and NRP implementations, leaving only the
leftover memory available to be used in testing”[18]. He attempted to solve this by trying
to move the heap into an external SRAM, but it was never completed successfully. Despite
this he was however able to prove that most of the NRP functionalities were succesfully
implemented, where as the only exception was that of multiple concurrent streams, as a
server was not able to receive concurrent streams from two clients.
Mission Event Planning & Error-Recovery for CubeSat Applications - Magnus Haglund
Arnesen and Christian Elias Kiær
Arnesen & Kiær presents the most important system level mission event plans. Their pa-
per investigates the battery charging and discharging and presents a power budget, and a
design for an external watchdog is presented and tested.
Error Detection and Correction for Low-Cost Nano Satellites - Kjell Arne Ødegaard
Ødegaard evaluates low-cost measures for dependability and robust Error Detection and
Correction for use in applications such as nano satellites. Different methods are evaluated,
9
with the main result being the mitigation failures due to bit-flips in system memory by
using BCH codes [19]. An implementation is then made, tested and the result is discussed.
As can be seen form the theses presented above, there has been written multiple papers
on how reliability can be assured for the OBC through the use of various software tech-
niques. This paper therefor focuses on the implementation design of the actual OBC, using
the already documented research of the former theses as a starting point. Before an archi-
tecture can be decided upon, one has to create a requirement specification to ensure that
one solves the correct problem. This will be presented in the next chapter.
10
Chapter 3
Requirement Specification
In this chapter, the requirements imposed upon the OBC will be analysed and discussed.
A functional, as well as a non-functional requirement specification for the OBC will be
presented. After the specifications have been formed, the complexity of the OBC will be
determined and a size, weight and power budget will be estimated.
The NUTS satellite has an official mission goal list that has been used as guidelines to
what is to be implemented. In addition to this, Arnesen and Kiær presented a functional
requirement specification for the satellite in the paper ”Mission Event Planning and Error-
Recovery for CubeSat Application” [12]. These are however not made with consideration
to each other and are partially redundant. This chapter will therefor first unify the differ-
ent functional requirement specifications for the satellite before also constructing one for
the OBC, as up until now there has been none. In addition to this, guidelines on how to
document requirement and design implementations for subsystems of the NUTS satellite
are also proposed.
11
3.2 Satellite Requirements
A functional requirement specification specifies the general demands that are to be sat-
isfied by the system. The specification should be general and should not entail details
of how the system is constructed [21]. Though there are no official satellite requirement
documentation, a general list of requirements was proposed by Holmstr{om in 2012 [22],
in addition to one posted inside the NUTS private Wiki pages. These two lists now form
the basis for the new satellite functional requirement documentation that can be seen in
table 3.1. The requirement specification has been designed to entail all higher order de-
mands imposed upon the satellite. An effort has been made to exclude any demands that
are means to higher goals or are only valid under certain implementation choices. Like-
wise, non-functional requirements such as reliability and error handling are not included,
as these are considered to be means towards a goal, rather than a goal on their own.
ID Description
R01 Deliver a tested satellite according to mission specifications.
R02 Transmit a beacon signal receivable for radio amateurs.
R03 Confirm successful de-tumbling.
R04 Establish two-way communication and receive full telemetry.
R05 Test the payload camera.
R06 Initiate camera pointing.
R07 Initiate camera sequencing to capture meaningful images
R08 Receive a valid series of images
12
course the one that should be described in the design specification. Whenever a design
choice is made, new requirements are often introduced to the system as a consequence of
the design choice. These sub requirements should be documented as well by referencing
the design choice that introduced them.
The naming convention is perhaps best explained though an example requirement spec-
ification such as this: R04-OBC-LOG-001: The OBC must keep a log of various house-
keeping data.
• R04 - The requirement is a sub requirement for ”R-04: Establish two-way commu-
nication and receive full telemetry.”
• OBC - The name of the satellite module the requirement is imposed upon (see list
of names further down).
• LOG - This is just a sub module, all requirement IDs containing this keyword will
be concerning the logging feature.
• 001 - This is the unique number of the ID differing this ID from the IDs of other
requirements in the same sub module.
The rules abstracted from the examples above will now be presented for a more general
case. A specification ID is composed of:
• Three digit code linking the spec to the grander scheme of the satellite goals. Made
up of:
– One letter referencing whether the spec is concerned with a system require-
ment (R), or a design choice/implementation(D).
– Two digit number for the grander requirement the spec is contributing to sat-
isfy. If the spec is concerned with the satellite in its entirety, the 00-number
can be used.
• Two digit number for the grander requirement the spec is contributing to satisfy. If
the spec is concerned with the satellite in its entirety, the 00-number can be used.
• Three letter code indicating the module.
• As many additional three lettered codes as needed to properly describe the spec.
• A unique number in the range 0 to 999
13
Proposed names for the top modules:
• ADC - The Attitude Determination and Control System (ADCS)
• CAM - The camera module
• COM - The Internal satellite communication bus
• EPS - The Electrical Power System
• OBC - The On Board Computer
• UHF - The Radio OBC module containing the Happy Gecko and the UHF radio
14
3.4 OBC Functional Requirements
As earlier work associated with the OBC has been concerned with reliability rather than
functionality, no OBC requirement specification has been articulated. The author thus
presents a functional requirement specification in the following section.
R00-OBC-INI-000 INI=INITIALIZATION.
The OBC must run an initiation of the satellite upon de-
ployment
R00-OBC-INI-001 The OBC must issue an antenna deployment signal
R00-OBC-INI-002 The OBC must start beacon transmission from the radios
R00-OBC-INI-003 The OBC must issue a de-tumble command to the ADCS
upon initial deployment
R00-OBC-INI-004 The OBC must enter normal operation mode
15
R04-OBC-HKP-000 HKP=HOUSEKEEPING.
The OBC must monitor and maintain the health of the satellite.
R00-OBC-HKP-001 The OBC must periodically check and act upon its own integrity.
R00-OBC-HKP-002 The OBC must periodically check and act upon the health of
other modules.
R04-OBC-HKP-003 The OBC must keep a log of the satellite’s health
R01-OBC-EXE-000 EXE=EXECUTABLES.
The OBC must be able to execute commands on demand
from ground station
R01-OBC-EXE-CMD-000 CMD=COMMANDS.
The OBC must support a set of commands.
R00-OBC-EXE-CMD-001 The OBC must be able to perform a full, and/or partial
reset of the satellite.
R01-OBC-EXE-TIM-000 The OBC must be able to schedule commands to be exe-
cuted later.
R01-OBC-EXE-TIM-001 The OBC must keep track of time.
R01-OBC-EXE-TIM-002 The OBC must be able to set alarms to schedule future
executions.
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3.4.4 Satellite Executables
For the OBC to be of any use to the satellite, it must be able to interface with other satellite
systems. One of the most important of these systems, is the radio, as without control over
the radio no contact can be made with Earth. The first interface requirement for the OBC
is thus that it must interface with the radio. For any other functions that involve other
satellite modules, the OBC must be able to interface these as well. Each module has been
given a separate keyword so that all interface requirements related to that module can be
grouped under this ID.
R04-OBC-EXT-000 EXT=EXTERNAL.
The OBC must interface with the other modules
R04-OBC-EXT-RAD-000 The OBC must interface with the on-board radio
R03-OBC-EXT-ADC-000 ADC=Altitude Determination and Control System.
The OBC must be able to configure and control the
ADCS.
R03-OBC-EXT-ADC-001 Module reset, module power down.
R03-OBC-EXT-ADC-002 Start de-tumbling.
R03-OBC-EXT-ADC-003 Stop de-tumbling.
R03-OBC-EXT-ADC-004 Point in a given direction.
R07-OBC-EXT-CAM-000 CAM=CAMERA PAYLOAD.
The OBC must be able to configure and control the cam-
era.
R07-OBC-EXT-CAM-001 Module reset, module power down/up, request statistics.
R07-OBC-EXT-CAM-002 Schedule image capturing
R07-OBC-EXT-CAM-003 Retrieve images, and send to ground station
R08-OBC-EXT-CAM-004 Retrieve thumbnail images and send to ground station
R08-OBC-EXT-CAM-005 Delete images
R07-OBC-EXT-CAM-006 Set; gain, frame rate, frame size, and exposure time.
17
3.5 OBC Non-Functional Requirements
Nonfunctional requirements specify system properties, such as reliability and safety [23].
Table 3.6 shows the top-level non-functional requirements for the OBC. The requirements
are still quite general and generic, and are expected to grow in details as the design process
matures.
ID Description
R00-OBC-NON-DUR-000 DUR=DURATION
Mission operation is 3 months.
R00-OBC-NON-AVA-000 AVA=AVAILABILITY
The mission capable rate should be ass high as possible, and
should not be less than 50%
R00-OBC-NON-AVA-001 The OBC must be able to handle multiple concurrent requests.
R00-OBC-NON-SUR-000 SURVIVABILITY
The OBC must survive its natural environment (space)
R00-OBC-NON-REL-000 REL=RELIABILITY
The OBC mean time to failure (MTTF) should be greater than
the duration of the space mission.
R00-OBC-NON-REL-001 No single failing task or component shall end the satellite mis-
sion.
R00-OBC-NON-REL-002 The OBC must be able to recover from failures.
R00-OBC-NON-REL-003 Execution of less-important tasks shall not affect the timeliness
of higher-prioritised tasks.
R00-OBC-NON-TES-000 TES=TESTABILITY
A formal test procedure with measurable results must be enun-
ciated and performed.
R00-OBC-NON-MAI-000 MAI=MAINTAINABILITY
Code and documentation must be made easy to understand
The OBC does not need to be capable of image processing, as it is sufficient to simply
relay packages from the camera module. Due to the use of E-fuses to cut off power in
the event of SELs, there are no hard real time demands for the NUTS satellite. The most
18
resource exhaustive tasks of the OBC then seems to be the error checking itself. Ødegaard
argues that the best way to mitigate SEE caused bit flips is by using BCH codes which are
rather resource exhaustive [19]. BCH codes can be implemented in many different ways,
but as an example a BCH decoder can be implemented using tools such as pruned Fast
Fourier Transform (FFT) and gaussian elimination [24]. This warrants a microcontroller
capable of some more advanced mathematics and perhaps added hardware support for dig-
ital signal processing (DSP) or floating point calculations. The author therefor categorizes
the complexity as normal; some expensive processing is to be done, but there are no hard
real time demands for them to finish within.
To estimate the size, weight and power requirements for the NUTS OBC one can inves-
tigate the already made hardware and use these measurements as preliminary metrics for
the estimation of size and weight. The volume is found by measuring the circuit board and
multiplying the width and length with the height (measured as the distance from the top
of the tallest top-side component to the top of the tallest component on the bottom-side).
As the OBC module measures 9x9x1.3 cm, the volume is 105.3 cm3 . The weight is found
to be 28 grams by weighing with a kitchen scale. Volstad measured the worst case power
consumption of the initial OBC version to be around 150 mW. He does not mention at
what frequency the OBC is running, which is unfortunate as this is one of the main factors
in the power consumption. In order to get more confidence in the power consumption esti-
mate, the theoretical power consumptions of one of the highest preforming candidates (to
be presented in the next chapter) is used. That is the SAM E70, and running at 300 MHz,
with all peripherals except USB and Ethernet MAC enabled. The typical power consump-
tion then adds up to 116 mA or 382 mW [25]. With the added power consumption found
in the datasheets of the components used for the original OBC the estimated peak load is
set to be 550 mW.
19
Chapter 4
Determining the Components
In this chapter, the different hardware possibilities and restrictions for the OBC will be
discussed. Various microcontrollers and external memory will be presented and compared
against each other and the requirements of the OBC.
4.1 Overview
The originally presented OBC in Volstad’s thesis of 2011 consisted of a 32-bit MCU
(At32UC3A3256), a NAND flash memory for housekeeping logs, an static RAM (SRAM)
memory for processing variables, an one time programmable (OTP) memory for safe stor-
age of module firmwares, USB interface and a wireless intra-satellite communication mod-
ule (NRF24LE1)[26]. Volstad wrote drivers to test both SRAM and the NAND-flash and
measured the maximum power consumption to be around 45 mA or about 150mW. The
design also included a sister module with the same microcontroller and a very similar hard-
ware setup, enabling for redundant functionalities implemented in the two modules. Since
the original design, the OTP memory has been replaced by ferroelectric RAM (FRAM)
memory. The work on the intra-satellite communication module has been discontinued
due to lack of interest/workforce. It has therefore been removed from the design. The
USB connector has also been removed from the design. Unfortunately, though all of these
choices probably have been discussed thoroughly, they are only sparsely documented. As
Volstad’s thesis focuses on many aspects of the satellite, specific hardware choices are not
always adequately discussed. Most of the OBC hardware setup is therefor without argu-
mentation or justification and in need of reviewing. The current OBC setup will therefore
be explored and discussed in the next chapters. This is done to enforce that all design
choices are traceable, well thought-out, and made on the right premises. This ensures that
later revisions can easily incorporate or justly replace any component of the design, creat-
ing new revisions, instead of unnecessarily scrapping previous designs and starting from
scratch multiple times.
20
Figure 4.1: OBC Hardware Modules
The latest list of the parts that makes up the OBC can be seen in the list below and in
figure 4.1, which also displays the interfaces of the microcontroller.
• At32UC3A3256
• 4 Mbit FeRAM B85R4001
• 16 Mbit SRAM IS61wv102416BLL-10TLI
• 32 GB NAND FLASH (MT29F16G08ABACAWP-ITZ:C)
• JTAG bus
• I2 Cbusinterf aceother
As this paper is written, there is being made an attempt to replace the I2 CbuswithaControllerAreaN etwor
21
to be 3.205 W, while the combined satellite power consumption was estimated to reach as
high as 8.791 W [12]. A maximum power consumption for the OBC module (MCU plus
memories) has been estimated to 550 mW, however the average power consumption must
be much lower if the batteries are not to be drained out. For the initial mode, when the
satellite has been released, but not yet started detumbling, the instantaneous power con-
sumption is estimated to be 3025 mW (only 180 mW less than the average charging power)
[12]. This estimate assumes an average power consumption of the OBC MCU and mem-
ories to be 330 mW. The satellite power consumption is expected to increase as normal
mode is engaged, and it is therefor imperative that a good trade/off between computation
power and power consumption is found for the OBC.
Another criteria that will be used to evaluate the microcontrollers is the practical issue
of complexity and implementation time. The NUTS project demands a fully functional
implementation, and whatever work is done by the author will be left behind for another
student to continue. It is thus essential that the work is easily comprehensible and as com-
pleted as possible. It is for this reason bare-bone microprocessor-solutions are not con-
sidered. Also, when considering different ARM Cortex-M microcontrollers, when similar
processors are employed by different vendors, the author will favor those from Atmel due
to Atmels involvement in NTNU and the students familiarity with Atmel development
tools.
New in the latest design revision of NUTS is the switch from I2C to CAN bus as the
22
internal memory bus. There is therefor a demand that the microcontroller can interface
with the CAN bus either through an external CAN controller (e.g. via SPI) or preferable
with an internal CAN controller. Microcontrollers with inherrent support for CAN will
therefor be preferred, but are not imperative as external controllers can be used.
For space legacy reasons, and for it’s low power consumption the MSP430 will be consid-
ered. ARM Cortex-M microcontrollers are becoming more and more popular and might
also be considered viable options. The Cortex-M family is a product line of microproces-
sors especially designed for microcontrollers and these will therefor be evaluated. A table
23
of the different Cortex-M processors can be seen in table 4.1. The performance efficiency
is measured in CoreMark per MHz, and the Cortex-M1 is not included as this is designed
specifically for implementation in FPGA. From table 4.1 one can see that if low power con-
sumption is important the M0+ might be a viable option, however if computation power
is emphasized, one could go with the higher order cortexes such as the Cortex-M4 or the
Cortex-M7.
Lastly, the current OBC microcontroller AT32UC3-family should be compared to see if the
benefits of changing the microcontroller outweighs the additional implementation costs.
The MSP430 has proved it’s reliability through numerous space missions and has one of
the lowest power consumption as well. However its maximum CPU clock frequency is
24 MHz and it only uses a 16 bit instruction set. It has a low power consumption, but at
the expense of the computational power. This means that for computationally expensive
tasks the microcontroller will have to stay in active mode a lot longer than it’s competi-
tors in order to finish the calculations. This may in turn raise the power consumption and
although the maximum power consumption still is lower, the total power consumption
might be more, depending on the task. There is however one flavour of MSP430, nam-
ley the MSP430FR which is of special interest to space missions. The MSP430FR uses
FRAM memory instead of flash for non-volatile storage, and as FRAM is inherently more
radiation resistant than flash [32], this makes for safer storage of program code as well as
24
Characteristics MSP430 SAML21 SAM4E SAM E70
Frequency [M Hz] 24 48 120 300
Flash [KB] 128 (FRAM) 256 1024 2048
SRAM [KB] 2 40 128 384
External memory bus no no yes yes
Power Consumption Active [mA] 2.2 3.5 44 100
Power Consumption Sleep [µA] 0.32-285 1.2-185.5 2-10000 5.8-24000
application data. However as the maximum available memory size is 128 KB and there
is no external memory interface [29], this might cause some serious memory constraints
on the application, as we could see from the constraint section above. In addition to this,
the MSP430s only have a 2KB SRAM, though any unused FRAM can be used as volatile
memory, it is unlikely that there will be any FRAM leftover memory for this. The fact
that none of the MSP430 support any external memory bus puts them at a disadvantage.
A solution might be to interface external flash through SPI or to implement a bit-bang
external parallel memory bus, however a microcontroller with a bigger program memory
or at least an external memory bus interface would be preferable as SPI flash suffers from
slower speed, and bit-bang parallel buss from added complexity.
The SAM L21 features an ARM Cortex-M0+ and has a power consumption compara-
ble to the MSP430. It has up to 256 KB embedded Flash and 40KB SRAM. However,
none of the Cortex-M0/Cortex-M0+ microcontrollers support external memory bus nor
have support for CAN. The power consumption restriction of maximum average of 100
mW turns out to leave quite some room for the power consumption of the microcontoller
and can be satisfied by using the higher order arm cortex-M as well.
If CAN controller and external memory bus is emphasized one can consider SAM4E
(Cortex-M4) or SAM E70 (Cortex-M7). The SAM E70 can be run at a much higher
frequency (300MHz compared to SAM4E’s 120MHz) and has support for additional fea-
tures. The downside is the added power consumption. However as SAME70 inherently
supports Error Correcting Codes (ECC) in both data and instruction chaches, as well as
memory Integrity Check Monitor (ICM), it seems the better option for space applications.
SAME70 is therefor considered the best candidate as a replacement for the currently used
UC3A3. In addition to this another member of the UC3 family with a larger non-volatile
memory and support for CAN will also be evaluated. The UC3C is quite similar to the
UC3A3, and most of the code written for either device is easily ported from one version
to the other. Since current development on the back-plane may warrant CAN support, and
the fact that the UC3C has double the non-volatile memory and support for hardware ac-
celerated fixed point calculations makes it an appealing candidate. The next section will
therefor investigate the pros and cons of these two UC3 microcontrollers to that of the
SAME70.
Comparing the SAM E70 to the UC3 currently being used in the OBC, one can see that
25
though memory checking already is implemented for the UC3 there will be no additional
implementation cost by switching to the SAM E70 as the Integrity Check Monitor can be
used for memory checking. In fact, using the ICM will be more power efficient as ICM
uses DMA, hashing functionalities and other hardware implemented functions decoupled
from the CPU. The SAME70 therefore seems a viable option as the microcontroller for
the OBC. The table below sums up the advantages and disadvantages of using the UC3s
versus the SAM E70.
Value UC3A3 UC3C SAM E70
Frequency [M Hz] 84 66 300
Flash [M Hz] 256 512 2048
SRAM [KB] 64+64 64 384
Power Consumption Active [mA] 40 40 100
Power Consumption Sleep [µA] 31-100 31-100 5.8-24000
ECC implemented in HW and SW Only SW Only HW
Mem. Integrity Check SW SW HW
From table 4.3 one can see that the SAME70 indeed is a viable option, however the fact
that the SAM E70 does not have any boot-pins means that it must boot from the same place
in memory each time. If a radiation induced bit flip incurs in this section, the microcon-
troller will be put into an eternal failure state. This means that there will be a single point
of failure in this memory. The likelihood of such a critical error to occur is hard to accu-
rately predict, yet still the next section will try to explore this in order to say something
about the risk involved.
The typical error rate for COTS in LEO is said to be 1/100000 per bit per day [15]. This
is a rough number, but will be used for this probability calculation. If more accurate num-
bers are found later, they can easily be applied to the formula that is being deduced in this
section, in order to find more accurate estimates. If we now assume constant failure rate,
z(t) = λ, the probability of a failure will grow exponentially so that the probability of a
failure having occurred after a long time will be large [21]. The mean time to failure will
then be given by:
R∞
MTTF = 0
tf (t) dx
1
For constant failure rate of λ = 105 per bit per day, this evaluates to a MTTF for one
single bit to be:
R∞ R∞
MTTF = 0
tf (t) dx = 0
e−λt dx = 1
λ = 105 days.
If we now assume that the failures are independent of each other (correlation equal to
zero), we can estimate the mean time to failure (due to radiation induced bit flips) for a
26
program residing in memory based on it’s code size. First we can calculate the probability
of one or more bit flips in a memory section after (τ ) days:
1 1 1
MTTF = λ = P (Section compromised) = 1−(1−κ)η )
Let’s now investigate the MTTF for a two stage bootloader scheme, where the first stage
is to fetch a program image from external, safer memory, while the second stage is to run
the fetched code. In this scheme only the code for the first stage is stored in internal (en-
dangered) memory, we assume the external memory is perfectly safe. However, one single
bit flip in the first stage of the bootloader will cause the complete and permanent failure of
the entire system. If we assume that the size of the first stage bootloader is the same as the
size of the ProgramLoader implemented in the current OBC. In Marcadellas master thesis,
he states that the ProgramLoader is less than 2Kbit. This gives:
1 1
MTTF = 1−(1−κ)η ) = 1
1−(1− 100000 )2000 )
= 50.5 days.
This means that a design with a two stage bootloader (with no error correction) is likely to
fail catastrophically in less than two months. A plot of the MTTF as a function of program
memory size can be seen in below.
250
200
MTTF in days
150
100
50
0
0 1,000 2,000 3,000 4,000 5,000
Code size in bits
27
As re-programing already is implemented for the UC3s [11], the UC3s do not have this
single point of failure, as a redundant microcontroller can reprogram a defect one if a bit
flip should occur in the boot section. Unfortunately the bit bang JTAG that has been im-
plemented is rather undocumented and device dependent and thus not easily ported. It is
likely that this would add greatly to the expected implementation time. This, in addition to
the Cubesat Space Protocol already being ported and tested on UC3 but not for SAME70,
results in the expected implementation time with SAME70 to be longer than that with
UC3. Also the fact that the UC3 is currently being used in commercial product lines of
GOMSpace, speaks at least somewhat to the expected radiation hardness of the device. As
Cortex-M7 microprocessor for space missions is unheard of to the author, not much can
be said for the radiation toughness.
If time to completion is emphasized, the least expected time comes from continuing with
the current OBC MCU, the UC3A3. It is uncertain whether the non-volatile memory of
256 KB will cause complications as the code size grows. As the UC3 series are so alike
and code easily can be ported from one device to another, the author recommends the
switch to the UC3C0512C microcontroller which is the biggest of the UC3C series. This
is mainly due to the added CAN and floating point support, but also in order to minimize
the chance of running out of internal program memory.
28
the OBC since the initial thesis of Volstad [26]. A proper discussion for the choices of
types and sizes for the OBC memories has thus not been made, and an attempt will be
made in the following section.
numbers are gathered from data published by NASA [33]. In this comparison MRAM
seems attractive for its unlimited endurance, unlimited retention, radiation hardness, and
low standby power. The MRAMs biggest shortcoming is its limited density, where NAND
Flash is the clear winner. And for ultra-low-power applications FRAM seems to be a good
solution.
The characteristics of the currently used FRAM can be seen in the table 4.4. It is clear
that the microcontroller must have non-volatile memory to load it’s program code from.
For reliability purposes this program image should also be stored in a memory that can be
considered to be radiation tolerant. The FRAM seems adequate for this purpose as well
as for storing flight critical data. However, with it’s limited size it might pose a problem
concerning the log that needs to be kept. It is not known how many log entries the log must
be able to contain, and for this reason a larger memory is needed for the log. As the log
is not crucial for the operation of the satellite, the previously proposed NAND flash may
be adequate for this purpose. Different flash memories for NUTS have already been dis-
29
cussed by Marcadella [11], and will therefor not be included in the discussion of external
memories in this report.
Parameter Value
Memory Type FRAM
Size 4 Mbit.
Bit configuration 524,288 words x 8
Interface Parallel 8-bit
Power Consumption standby 50 µA
Power Consumption operation 15 mA
R/W Endurance 1010 .
R/W Speed 150 ns / 150 ns
All current wildly used memory technologies (e.g. SRAM, SDRAM) are prone to radiation
effects [35]. As a straight forward solution, some OBCs were built to utilize only (non-
volatile) Magnetoresistive random-access memory (MRAM) as system memory which is
inherently immune to SEUs and therefore allows OBC engineers to bypass additional in-
tegrity assurance guarantees for RAM [32].
30
and is currently not available in sizes larger than 16 Mbit.
From the table presented in the last section, one could see that MRAM is inherently both
SEU and SEL immune. However, this might be misleading, though the memory elements
are immune, the necessary CMOS control circuitry surrounding the memory are indeed
susceptible to radiation effects[37].
Heidecker, Allen and Sheldon characterized a 1 Mbit MJT MRAM for total ionizing dose
(TID) and single event latchup (SEL). Their results indicate that these devices show no
single event latchup up to an effective LET of 84 MeV-cm2/mg and no bit failures to a
TID of 75 krad (Si)[38].
While Nguyen and Irom concluded that the Freescale MR2A16A was sensitive to SEEs,
and that SEL could be observed as low as 7 MeV-cm2/mg. The devices could however
withstand effects of TID up to 60 krad(Si) with only a few read errors [39]. Similar find-
ings was made by Elghefari and McClure, who concludes that the MR2A16A is very
sensitive to SEL with LET latchup threshold at room temperate of 10 MeV-cm2/mg [40].
Both these tests however tested the system as a whole and did not differ errors in CMOS
control logic from errors in memory blocks. The author has unfortunately not been able
to find any tests of the SRAM family used for the OBC. However both RAMs have been
used in other satellites. EstCube-1 uses the exact same SRAM as the one used for NUTS,
while the SpriteSat used the MR2A16A MRAM from Everspin (earlier Freescale).
31
Parameter SRAM MRAM
Size 16 Mbit 16 Mbit
Bit configuration 1024K words x 16 1024K words x 16
Interface Parallel 16-bit Parallel 16-bit
Temperature range Industrial (-40 to 85) Industrial (-40 to 85)
Power Consumption standby 30 mA 9 mA
Power Consumption operation 85 mA 106 mA
R/W Endurance unlimited unlimited
R/W Speed 8ns (125 MHz) @ 3.3v 35ns (28 MHz) @ 3.3v
There is an issue with MRAM known as write soft error (WSE). WSE is a type of disturb
error, meaning the errors arise in cells neighboring the targeted cell, not the targeted cell
itself. The rate at which WSE is significant, and is the reason why MRAM chips have ECC
built in. The current generation of toggle-based MRAMs are less susceptible to write dis-
turb phenomena thanks to ”Savtchenko switching”[41]. However the soft error rate is still
not low enough to warrant removing the ECC [42]. Despite this, NASA encourages the
evaluation of MRAM for space missions by stating: ”Missions in the planning or design
phase may want to seriously consider using MRAM”[33]. The fact that the MRAM has
low-voltage inhibit circuitry to prevent writes with voltage out of specification [43] is also
considered to be a plus, as this may give some shielding against radiation induced currants.
The characteristics of the currently used SRAM and the potential replacement MRAM can
be seen in the table below (FRAM is not being considered due to it’s limited endurance
and size).
For comparison, the internal flash has a access time of 30 ns (33 Mhz). So changing to
MRAM would require one wait state when running faster than 28 MHz, this is much like
the speed of running from the internal flash.
Numbers are based on the the respective datasheets for the SRAM [44] and the MRAM
[43]. One can from this table see that the devices are comparable, and while MRAM has
a higher power consumption when in use, it has a much lower power consumption when
in standby. A simple rough estimate for the total power consumption can be obtained by
using the formula below:
By the use of this formula one discovers that the MRAM uses the least power for duty
cycles smaller than 50%, while SRAM has the lowest power consumption when the de-
vice is on for more than half of the time. One must however note that since the SRAM
read and write speed is almost 5x faster than the MRAMs, it is likely that a microcontroller
using SRAM will finish faster than the MRAM and thus have a shorter duty cycle resulting
in more time kept in the low power mode for the same amount of workload. However as
the expected duty cycle of the OBC is much smaller than 50%, the MRAM will deliver
the more energy conserved performance.
32
4.3.3 Common Cause Failures and Risk Reduction
Consider a system of two components, A and B. One way of formulating dependency
stems from the idea that the components are susceptible to some common stress that causes
simultaneous failures. The event in which common stress occurs and both A and B fails,
is often referred to as a Common-Cause Failures (CCF) [45]. The more similar A and B
are, the higher will the dependency be, and thus also the likelihood that some common
stress may cause them both to fail. When using redundancy it is therefore important that
the chances of CCFs occurring is small, and thus advantageous if different components
are used in the different modules. This way, if one of the components has a weakness, it
will most likely not be in the other one, and operation can continue with the functional
component. With this in mind, the author thus suggests that the traditional SRAM is kept
in one OBC, while the MRAM is used in the other.
4.3.4 Conclusion
The memories included in the current design are sufficient to satisfy the requirements of
the OBC, however they may not be optimal. After discussing the strengths and flaws of dif-
ferent memories the author suggests that one of the SRAMs is to be replaced by MRAM,
more specifically with the 16Mbit 16-bit I/O Parallel Interface MRAM MR4A18B from
Everspin. The main arguments for this is the added protection against radiation, the low-
ered power consumption when not in use, as well as the added possibility of using parts
of the chip as non-volatile data storage. The cost of this switch is the implementation time
for the new connection routing, and the fact that wait states may have to be implemented
at high frequencies. These costs are however considered to be outweighed by the added
reliability offered by the MRAM-cells. To minimize risk the author also proposes different
memory setups for the two sister OBCs, where as one uses SD-card for logging, while the
other uses regular Flash. Likewise while one uses the conventional SRAM the other will
instead utilize the newer MRAM technology. This way redundancy is achieved also in
hardware and system failures due to common component faults are minimized.
33
Chapter 5
Software Architecture
In this chapter, the initial plans for a software architecture are presented.
34
Figure 5.1: The software architecture of the OBC
35
Chapter 6
Reflections
In this report the major NUTS OBC requirements have been explored and a functional as
well as a non-funtional requirement specification has been presented. The microcontroller
for the NUTS OBC has been evaluated and it’s external memories has been reviewed and
discussed. The SAM E70 was found to be a capable replacement for the currently used
OBC, though the reduced time to completion of continuing with a UC3-family controller
resulted in the author recommending future development to incorporate the UC3C0512C
microcontroller as the OBC. After discussing the alternative RAM solutions the current
memory setup was deemed sufficient, though the author recommends that the SRAM in
one OBC is replaced by MRAM.
The report has then suggested a software design that aims to satisfy the functional re-
quirements with the evaluated hardware. The blue print for the service contracts the OBC
will conform to have been included and can be seen in Appendix A.
Discussions have been made under each chapter, where relevant data has been presented
and compared. The OBC is entrusted with many tasks and is dependent on many factors.
This makes for a complex system that is not easily comprehensible and the author there-
for believed it to be necessary to structure the rapport so that individual discussions are
made for each problem, rather than one huge discussion section at the end of the report.
The focus of this report has been rather wide. This has been on demand from the NUTS
administration due to dependencies to other modules that are currently being worked on.
The most time has been spent on information gathering, planning and coordinating with
other NUTS system developers, as well as with management.
Lessons learnt:
• The importance of detailed specifications and interfaces
• Dependencies complicates system design, and circular dependencies can be espe-
cially challenging.
• Number of code lines written or hardware produced are easily conceived steps of
36
progress, sometimes stressing the importance of taking a step back to establish spec-
ifications may not be perceived as progress from outsiders or the boss’s boss. Stress-
ing their importance is still crucial.
• Revision history can be challenging, especially for documentation.
37
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41
Appendix A:
OBC Service Contracts
42
Interface for the Logger
The logger is the software service responsible for maintaining the log. It is implemented
as a single thread with one listening socket, LOGGER SOCKET RX. The logger will be
the only task that has direct access to the hardware keeping the log (i.e. flash memory) and
will act as a server, responding to logging requests of the rest of the system. The calls it
shall respond to can be seen in the table below.
Call Parameters Reaction
PING RSVP SOCKET Send PONG to RSVP SOCKET
PONG NONE Register response
LOG ADD log t log, time t time Write the log entry into the log.
LOG GET RSVP SOCKET, int Send the N last log entries to
N RSVP SOCKET.
LOG DEL N LAST NONE Delete the N last log entries.
LOG INIT NONE Initialize the LOG, any old log en-
tries will be deleted.
43