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Defect-oriented cell-aware ATPG and fault simulation for industrial cell

libraries and designs

Conference Paper · December 2009

DOI: 10.1109/TEST.2009.5355741 · Source: IEEE Xplore

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 Defect-Oriented Cell-Aware ATPG and Fault Simulation for Industrial Cell
Libraries and Designs

F.Hapke1, R.Krenz-Baath1, A.Glowatz1, J.Schloeffel1, H.Hashempour2, S.Eichenberger3, C.Hora2, D. Adolfsson2

1 2 3
Mentor Graphics NXP Semiconductors NXP Semiconductors
Tempowerkring 1B Prof. Holstlaan, HTC-46 Gerstweg 2, FD3
21079 Hamburg 5656AA Eindhoven, 6534AE Nijmengen,
Germany The Netherlands The Netherlands

Abstract
Industry is facing increasingly tougher quality
requirements for more complex ICs. To meet these
quality requirements we need to improve the defect
coverage. This paper presents a new methodology to
significantly increase the defect coverage of the test
patterns generated by ATPG tools. The fault model
used during the ATPG is enhanced to directly target
layout-based intra-cell faults. In contrast to previous
techniques, such as Gate-Exhaustive, N-Detect, or
Embedded-Multi-Detect, which either are too complex
for real-world designs or merely improve the
probability of detecting intra-cell defects, the new
approach targets the actual root causes of intra-cell
defects. The newly proposed Cell-Aware-methodology
has been evaluated for 90nm and 65nm technologies on
1671 library cells and on 10 real industrial designs
with up to 50 million faults. The experimental results
show an average increase of 1.2% in defect coverage
and a reduction of 420ppm in escape rate for a 50mm2
design.
Methods to specifically target cell-internal defects have
been proposed in numerous publications. Techniques
such as N-Detect [3], Embedded-Multi-Detect (EMD)
[6], or Gate-Exhaustive testing [7] have shown
considerable success to cover those un-modeled
defects. However those techniques are either too
complex for real-world designs or merely improve the
probability of detecting cell-internal defects.
The contribution of this work is the introduction of a
new methodology to directly target library cell-internal
defects. This new method we call Cell-Aware (CA).
The paper presents the general flow of the new
approach and discusses individual components in detail.
The new method has been evaluated on a large number
of 90nm and 65nm library cells and on various
industrial designs with up to 50 million faults. The
results have been compared to previous state-of-the-art
techniques. The experimental results underline the
significant increase of test quality enabled by this new
technology.

1 Introduction The remainder of the paper is organized as follows: The

To achieve today’s quality requirements on large
Systems-on-Chips (SoC) we need to obtain high defect
coverages with our test patterns. This is achieved by the
creation of test patterns based on wide range of
methods and fault models. Commonly used are for
example Stuck-At (SA), Bridging [1][2], Inter-Cell-
Opens [3] and Transition-Faults [4]. All these state-of-
the-art fault models share the assumption, that a fault
only occurs between library cell instances, at the ports
of library cells, or outside of library cells between the
interconnect lines of the library cells. State-of-the-art
ATPG tools apply those standard fault models and do
either assume no faults within the library cells, or
consider faults inside the library cell based on the gate
model used by the ATPG. These gate models are well
suitable for propagating fault effects through the library
cells. Furthermore they are useful for injecting faults at
the cell ports or at the ATPG primitives. However these
gate models are not suitable for modeling real layout-
based defects inside library cells.
objective of Section 2 is the discussion of previous
work in this area. In Section 3 the new CA
methodology is introduced and the individual
components are described in detail. Experimental
results we achieved with the CA methodology are
presented and discussed in Section 4. The achieved
impact on production testing is described in Section 5.
Section 6 gives an outlook on possible future work.
Section 7 concludes the paper.
2 Previous Work
The problem of defects not covered by standard fault
models, and techniques to target them has been the
objective of numerous publications. Methods such as
N-Detect [3], Embedded Multi Detect [6], or Gate-
Exhaustive [7] test strategies have been successfully
applied to deal with those uncovered defects.

Paper 1.2 INTERNATIONAL TEST CONFERENCE 1

978-1-4244-4867-8/09/$25.00 ©2009 IEEE
In N-Detect testing, the chance of detection is improved
by targeting the same fault multiple times under
different conditions. However, this typically also
increases the pattern set by a factor N and therefore
makes the test costly. The concept of the EMD ATPG
technique addresses this increase in pattern count and
has been initially proposed in [6] and the achieved
results have been presented in [9].
The major contribution of the EMD-based approach
was to increase the defect coverage by exploiting
unused bits in existing patterns, instead of adding
further test patterns as proposed by methods based on
N-Detect. The major disadvantage of methods like N-
Detect or EMD is that there exists only a probabilistic
relation to actual defects. A technique to quantify this
relation has been proposed [8], in where a Bridging
Coverage Estimate (BCE) has been introduced based on
the assumption that there exists a 50% probability,
when the Stuck-At fault at the victim node is detected
and the corresponding aggressor node is in the right
state to activate the bridge defect. An extension of this
technique is presented in [10]. Since the relation is only
probabilistic, it is difficult to quantify the additional
defect coverage and to predict the benefit for future
designs.
In order to find an explicit and deterministic method to
cover those un-modeled defects, the results of over one
million tested devices of an NXP design have been
discussed and analyzed in [9] to identify the defects
found by EMD test patterns. This analysis has shown
that a significant number of defects, which are only
detected by EMD patterns, are intra-cell defects not
covered by the Stuck-At fault model. The extraction of
intra-cell defects has been the objective of several
publications [12], [13], [14].
The application of Gate-Exhaustive testing to detect
intra-cell defects is the objective of [7]. The paper
compares the efficiency of methods based on N-Detect
and Gate-Exhaustive testing w.r.t. the detection of intra-
cell defects. Furthermore, the paper demonstrates the
capability of addressing all gate-input combinations by
the ATPG to find missed defective devices. In practice
this method seems to be not applicable for industrial
circuits, because there is a high probability in
generating a high number of additional patterns and
consequently higher test costs.
Another major gap in using this method is the missing
relation to real potential defects. The used metric based
on all gate-input combinations can provide a number to
quantify the generated patterns, but without a relation to
defects. The method proposed in [11] directly targets
intra-cell defects which have been extracted from the
actual layout representation of the design.
Paper 1.2 INTERNATIONAL TEST CONFERENCE
Unfortunately the proposed flow including layout
extraction, netlist manipulation and the subsequent test
pattern generation is not applicable for large designs.
3 A new Cell-Aware Methodology
The objective of this section is a detailed introduction
into the new defect-oriented Cell Aware methodology
proposed in this paper. Firstly we provide an overview
describing the general flow. This is followed by a
detailed description of the individual steps.
The flow starts with the Layout Extraction step,
followed by an Analog Fault Simulation, and a
synthesis step to create the CA library models. Finally
these CA models are used by the CA-ATPG to generate
high quality test pattern to significantly reduce the
Defect Level of delivered ICs. The complete flow as
shown in Figure 1, is a mixture of state-of-the-art
functions/tools and new functions and algorithms that
we developed for this new methodology.
F2
Layout Analog
F1
Extraction Fault Simulation
Library cell
layout data F3
F4
TC % Cell Aware Cell Aware
F5
Test ATPG Synthesis
Coverage
Figure 1: Cell-Aware methodology flow
The flow starts with the layout extraction, which
extracts a transistor netlist and a list of possible defects,
based on the layout data of the individual library cell
contained in file F1. The results of the layout extraction
operation are the extracted transistor netlist in F2 and
the list of defects of the particular library cell in F3.
Next, for each of the previously extracted defects an
exhaustive analog simulation is performed in order to
determine the complete set of cell-input combinations
which detect the defect. The resulting detection matrix
for the particular library cell is contained in F4.
The following “Cell Aware Synthesis” function
optimizes the previously generated detection matrix in
order to ease the subsequent CA-ATPG and to generate
the corresponding CA library view stored in file F5. For
each cell-internal defect file F5 contains one or more
alternative conditions for detecting the corresponding
2
defect. Note that all previous steps are a one-time effort and the cell-outputs are contained in the defect lists for
for a specific library. each cell as well.

The final Cell-Aware ATPG step generates the high 3.2 Analog Fault Simulation
quality test patterns based on the earlier generated CA This step in the flow simulates the extracted netlist of
library view. Current results achieved by this new CA each cell in presence of its defects. As an example we
methodology show a significant increase of the defect consider again the 3-to-1 multiplexer described in the
coverage. previous section. The extracted netlist is shown in
Figure 3.
3.1 Layout Extraction
The base of every layout extraction is the actual layout P8 P54

view of the library cell under investigation. As an

P24 P38

S0
example we consider the cell MUX31X4 from a 65nm N8
P23 P34
P48

library, representing a 3-to-1 multiplexer. The

corresponding layout is shown in P31
P63

Z
Figure 2. D2 N28 N63

D1
D0
N23 N32 N41

P60

S1 N24 N33 N57

N60

Figure 3: Extracted Transistor Netlist

The extracted netlist, including its parasitic objects, is

Figure 2: MUX31X4 layout
From this layout data, in our case gds2, we extract the
corresponding netlist of circuit elements. The netlist
includes transistors as well as parasitic elements, like
capacitors. For this part of the flow we used a state-of-
the-art commercial EDA extraction tool.
The extracted netlist is used as input for the next step in
the flow where defects of interest are extracted. In this
paper we focus on cell-internal short/bridge defects.
Please notice that the whole Cell-Aware methodology
is capable to deal with many other defects as well, i.e. it
is just the question of extracting the defects of interest,
like e.g. opens. But in this paper we concentrate on
bridges only, thus for these kinds of defects an effective
method to identify realistic locations is based on
capacitors in the extracted netlist. The two nodes of the
capacitor are assumed to be shorted in the presence of a
defect. The individual specification of the bridge
resistances is part of the subsequent analog fault
simulation. Note that Stuck-At faults at the cell-inputs
used as input for the analog fault simulation, which
simulates the effect of each potential defect for all
possible input combinations. Additionally, each cell is
exhaustively simulated without defects in order to
determine the golden voltage at the cell outputs for
every cell-input combination. The simulations are
Analog DC-analysis simulations which determine the
steady state voltage of the cell output(s).
A defect is considered detected if at least for one input
combination the cells output voltage deviates from the
golden voltage by more than 50% of the supply voltage.
The deviation threshold however, can be specified by
the user. The simulations are automated by a set of
scripts around a state-of-the-art analog simulator.
The resulting defect matrix summarizes the detection
results for each cell. In such detection matrix rows and
columns refer to input combinations and defects,
respectively. A ‘D’ indicates that the input combination
detects the corresponding defect.
For further details please consider the MUX31X4-cell
as an example. The cell contains a total of 48
capacitors, where each capacitor can be shorted in order
to model a potential bridge defect. The list of 48
potential defects for this cell is presented in Figure 4,
where the capacitor terminals indicate the (potentially)
shorted nets.

Paper 1.2 INTERNATIONAL TEST CONFERENCE 3

d1 = S0N, gnd d17 = D0, gnd d33 = net38, D1
3.3 Generation of the Cell-aware Models
d2 = S1N, gnd d18 = vdd, gnd d34 = net81, D0 The following paragraph describes the computation of
d3 = net65, gnd d19 = Z, net65 d35 = net38, D0 an optimized set of input assignments required to detect
d4 = net57, gnd d20 = S1, S0N d36 = S1, S0 individual cell-internal faults. For every fault the
d5 = net19, gnd d21 = S1N, S1 d37 = D2, S1 algorithm extracts necessary constrains from the
d6 = net81, gnd d22 = net65, S1 d38 = S0, D1 detection matrix and maps those onto the corresponding
d7 = net38, gnd d23 = S0N, S0 d39 = vdd, S0N
function implemented by the library cell.
d8 = net85, gnd d24 = net81, S1 d40 = vdd, S1N
d9 = net35, gnd d25 = S1, net38 d41 = vdd, net65
d10 = net31, gnd d26 = D2, S1N d42 = D0, S0 The new technique is specifically tuned to deliver only
d11 = net69, gnd d27 = net81, S0 d43 = net38, vdd necessary input-assignments. This is an essential
d12 = Z, gnd d28 = net65, D2 d44 = vdd, Z property of the algorithm since it significantly relaxes
d13 = S1, gnd d29 = net38, S0 d45 = vdd, S1 the subsequent pattern generation process.
d14 = S0, gnd d30 = S0N, D1 d46 = vdd, S0
d15 = D2, gnd d31 = net81, D1 d47 = vdd, D2
d16 = D1, gnd d32 = S0N, D0 d48 = vdd, D1
Generate F from truth table 
For each d∈ D 
Figure 4: List of Defects of MUX31X4    Rd = emtpy set; 
   gd = OR1≤ i ≤ 2n ti if ti detectes d, 0 otherwise; 
From this list of potential defects in cell MUX31X4 we gdF = AND(gd, F);  
derive 48 additional netlists (hence 49 netlists including
gdF’ = AND(gd, F’); 
the golden netlist), where the targeted capacitors are
replaced by a resistor (one per netlist). Each of the 49 Rd = Rd  ∪ derive_prime_cubes(gdF’); 
netlists is simulated applying all 32 possible input Rd = Rd ∪ derive_prime_cubes(gdF); 
patterns, which results in a total of 1568 simulations. End 
The outputs are processed and defect detections are // Compression stage 
recorded for all input combinations. The final results P = emtpy set; 
are stored in the defect matrix of the cell. The table M = emtpy set; 
below in the Figure 5 shows a fraction of the defect For each Rd 
matrix generated for the cell MUX31X4:  For each q ∈ Rd 
   If ∃ pi ∈ P pi == q 
stimuli d1 d2 d3 d4 ... d41 d42 d43 d44 d45 d46 d47 d48
     M = M ∪ d;  // where d = M|i| 
00000 - - - - - - - D - - - -
00001 D D - - D D D - D D - -    Else  
00010 - - - - - - - D - D - -      P = P ∪ q;  // where q = P|P| 
00011 - D - - D - D - D - - -      M = M ∪ d;  // where d = M|M| 
00100 - - - - - - - D D - - -        End 
00101 D - - - D D D - - D - -
00110 - - - - - - - D D D - -
     End 
00111 - - - - D - D - - - - - End
01000 - - - - - - - D - - - D
... Figure 6: Proposed algorithm
11111 - - - - D - - - - - - -
The proposed algorithm, shown in Figure 6, works as
Figure 5: Defect Matrix follows. Assuming a detection matrix D generated w.r.t.
some n-input library cell C implementing the
For example the row describing stimuli ‘00001’ detects, combinational Boolean function F.
among others, defect d41 which is a short between the For every fault d specified in D the algorithm generates
internal net65 and vdd. a detection-function gd(). This detection-function
incorporates all fully defined input-assignments,
Through out this paper, we focus on CA-detectable meaning input assignments without don’t-cares, which
defects. Those defects, that are not detected by any would be required to detect d. Next every detection-
single-cycle input pattern are not considered in further function is combined with function F and its inverse F’
steps of the flow. Therefore all detection figures are in order to find the corresponding output assignment for
normalized with respect to the CA detectable defects. every cube contained in gd(). After that all prime cubes
of the resulting functions gdF() and gdF’() are collected
in the set Rd.

Paper 1.2 INTERNATIONAL TEST CONFERENCE 4

Finally the algorithm compresses identical cubes w.r.t.
all sets Rd and the corresponding fault information in
two sets P and M, where P denotes the final set of
primes cubes (the union of all prime cubes contained in
all sets Rd, d member of D), and M denotes a set of sets
containing every fault d detected by the corresponding
prime cube. The mapping between some element of P
and a set in M is defined via their indices. This means
that the cube Pi detects all faults contained in the set Mi.
Note that the described algorithm can be easily
extended to handle sequential detection matrices.
significant portion of cell-internal defects. The third
step is the evaluation of the Embedded Multi Detect test
patterns. As shown in [6] applying EMD test patterns
result in an increase of the defect coverage compared to
traditional Stuck-At tests. Furthermore these results
have been confirmed by experiments [9] during actual
IC production. The fourth step evaluates the coverage
gain of CA patterns w.r.t. previous methods such as SA
and EMD. For this additional pattern generation step
we use a newly developed CA-ATPG engine as
described below.

The major difference between the pattern generation for

3.4 Cell-Aware Pattern Generation and Fault a CA fault and a Stuck-At fault is the modeling of the
Simulation fault. To demonstrate those differences, we use the
already discussed 3-to-1 multiplexer and assume it is
To demonstrate the impact of the proposed cell-aware
somewhere instantied in the design.
fault model, we have set up a CA-ATPG flow, which
compares the defect-coverage achieved by previous
methods with the new approach. The investigation
incorporates the traditional SA model as well as the
EMD-based approach described in [6] and is performed
on a large number (1671) library cells and on 10
industrial designs implemented in 90nm and 65nm
technology. The flow is depicted in the figure below:

Fault Simulation FC % Figure 8: ATPG process

of SA pattern
In Figure 8 we show how the SA-ATPG will generate a
Design Fault Simulation FC %
test for detecting a port fault e.g. a stuck-at 0 fault at the
Compilation of EMD pattern cell-input D0. In a traditional Stuck-At ATPG engine
netlist the fault position (initial D-frontier position) and the
Cell Aware
condition for the fault excitation is predefined for every
FC %
ATPG ATPG-primitive. In this example the SA-ATPG would
Cell Aware justify D0=1, S0=0, and S1=0. The other inputs are not
library models required. The generation process of the CA-ATPG for
the same multiplexer is shown in Figure 9 below. In
Figure 7: Defect Coverage evaluation flow for all this case we assume an intra cell bridge between two
library cells and industrial designs nets A and B as indicated in the layout.

The evaluation flow starts with the design compilation

using the Cell-Aware models.

The number of CA-faults is always larger than the

number of faults considered using the traditional SA
model. This is because in the proposed flow, we
additionally consider the layout-based cell-internal
faults. The second step in the flow is the verification of
a set of SA patterns with respect to the CA fault model.
This evaluation is accomplished by a fault-simulation
of the SA-patterns on the corresponding design
considering the cell-internal defects. This fault Figure 9: TPG for an intra cell bridge fault
simulation typically results in a fault coverage drop
(compared to the known Stuck-At coverage) and clearly The initial D-frontier position of a CA fault is always at
shows that SA patterns are insufficient to address a the cell output port. The condition for the fault

Paper 1.2 INTERNATIONAL TEST CONFERENCE 5

excitation and it’s propagation to the cell outputs is
fully disconnected from any predefined ATPG
primitive. It strictly applies the necessary conditions at
the input-ports of the library cell as defined by the
corresponding CA model.
Algorithm: CA-ATPG
Given
f // actual fault
Sf // List of condition sets of fault f. In difference to a
// Stuck-At fault where the excitation condition are hard
// coded and bounded on the fault location, an intra cell
// fault is defined with the D-frontier position and a list
// of alternative excitation conditions. These conditions
// have been generated such that the TPG engine will
// have the the maximum flexibility to reach the highest
// coverage with the minimum number of test patterns.
Considering the bridge B1 in the above example, the
necessary assignments at the cell inputs are D0=1,
D2=0, S0=0 and S1=0. Meaning the CA-ATPG is
forced to assign an additional cell-input, in this case
D2, in order to detect the bridging defect B1. As
described earlier a traditional SA-ATPG would only be
forced to assign one data input. In other words, in
contrast to previous approaches the CA-ATPG
deterministically applies the conditions to detect intra
cell faults.
To guarantee a very compact set of test patterns, the
CA-ATPG algorithm makes use of all possible
conditions, given by the CA fault definition for
detecting a certain defect.

Initialization
4 Results
sf := undetected // status of f
i := 0 // actual index of Sf In this section we first present the results of our
C0 := Sf (i) evaluation of all combinational library cells from a
90nm library, followed by the evaluation results from a
// Select the D-frontier position for the fault propagation. 65nm library. And finally we present the results that
// The position defined for a intra cell defect on a cell output. were achieved by evaluating 10 real industrial designs
Define D-frontier position of f with up to 50 million faults.
if D-frontier definition failed then
4.1 Results for 90nm library cells
sf := redundant
end if The CA defect coverage for all 1220 cells of the NXP
standard cell library from a 90nm process technology
while sf = undetected are shown in the diagram below:
// We now using set C i to do the fault excitation. These
// conditions are on the cell inputs and have to be justified
100%
// by the TPG engine.
add condition set C i
90%
apply TPG to do fault excitation and propagation
80%
if TPG failed then
// The TPG did failed. If there are further condition sets,
70%
// we will continue the while otherwise we leave the
// loop with fault status redundant.
60%
sf := redundant
i := i + 1
50%
if Ci ∈ Sf then 0 200 400 600 800 1000 1200
sf := undetected Cell 1 to 1220 of the 90 nm library
end if Figure 11: CA coverage of SA pattern – 90 nm lib
else
// The TPG did successfully apply the fault excitation The horizontal axis represents the individual library
// and propagation. We leave the while loop with fault
// status tested. cells (from cell 1 to cell 1220). The vertical axis
sf := tested represents their coverage figures. The cells are sorted
Store generated test cube by their coverage incrementally from left to right. This
end if evaluation has shown that for 42% of the cells (516 of
end while 1220) the layout-aware defect coverage of SA patterns
is lower than 100%. This leads to a tremendous
coverage loss for these cells if only SA patterns are
Figure 10: Cell-Aware ATPG Algorithm applied. However, using CA patterns, the defect
coverage would be 100% for them.

Paper 1.2 INTERNATIONAL TEST CONFERENCE 6

The following table shows the 10 library cells from the 4.2 Results for 65nm library cells
90nm library with the highest loss of defect coverage: The CA defect coverage achieved by traditional SA-
patterns for 451 cells of a 65nm library are shown in the
Defect Coverage Additional diagram below:
Cell
Standart ATPG Cell Aware ATPG Pattern
mx31nx05 70,73% 100,00% 3
100%
mx31nx1 71,05% 100,00% 3
mx31nx2 74,55% 100,00% 3 90%
mx31nx4 74,55% 100,00% 3
mx31nx3 75,00% 100,00% 3 80%
mx31x4 75,00% 100,00% 5
mx31x05 79,25% 100,00% 4 70%
ao51x05 79,63% 100,00% 7
mx31x3 80,33% 100,00% 4 60%
ao31x1 81,40% 100,00% 5
50%
0 100 200 300 400
Figure 12: Worst 10 cells from the 90nm lib. Cell 1 to 451 of the 65 nm library

As can be seen in the table above, low defect coverage
exists mainly for certain types of library cells, for
example multiplexers. The cells mx31* are all
multiplexers with three data inputs and two select
inputs with different drive strengths. The cell ao31x1 is
a Boolean (AND/OR) gate with five data inputs. The
cell ao51x05 is a Boolean AND/OR function with nine
data inputs.
Figure 14: CA coverage of SA patterns – 65nm lib
Here the horizontal axis represents the individual
library cells (from cell 1 to cell 451) and the vertical
axis represents the corresponding coverage figures. The
cells are sorted by their coverage from left to right. This
graph illustrates again the layout-aware defect-coverage
of SA patterns. Even in this library 43% of the cells
(196 out of 451) are below 100%.

Figure 13 shows the number of test patterns generated The following table shows the top 10 cells from the
by SA-ATPG and the CA-ATPG for each of the 1220 65nm library with the highest loss of defect coverage:
cells of the 90nm library.
Defect Coverage Additional
Cell
Standart ATPG Cell Aware ATPG Pattern
25 XNOR2X3 71,43% 100% 1
AO32X4 76,00% 100% 1
AOI32X5 79,31% 100% 1
20
MX41X7 79,66% 100% 8
Num ber of Patterns

MUX31X4 80,00% 100% 2

15 XNOR3X4 80,77% 100% 1
SA MX41X4 81,82% 100% 7
CA AO222X9 82,50% 100% 5
10 AO22X4 82,61% 100% 2
AOI13X15 82,76% 100% 2
5
Figure 15: Worst 10 cells from the 65nm library
0
1 201 401 601 801 1001 1201 Again, it is the same observation as with the 90nm
library and it can be concluded that low defect coverage
is mainly occurring for multiplexers, some AO cells
Figure 13: Number of Patterns – 90nm cells
(Boolean gates) and in this library also for some XOR
gates.
In average over all 1220 cells, the CA-ATPG needs to
generate about 50% more pattern as the SA-ATPG, i.e.
Figure 16 shows the number of test patterns generated
in average 7.3 CA patterns per cell instead of 4.8 SA
by the SA- and CA-ATPG for each cell of the 65nm
patterns.
library.

Paper 1.2 INTERNATIONAL TEST CONFERENCE 7

 16 chains, resulting in 37.2 million Stuck-At faults and
14
48.5 million Cell-Aware faults. The designs I1652k,
I1676k, and I6649k are using on-chip test compression;
12
therefore these designs have a high number of internal
Number of Patterns

10 scan chains.
SA
8
CA
6 Considering the last two columns of the table, it can be
4
seen that the number of CA faults is in all cases
significantly higher than the number of SA faults.
2

0 We performed the test coverage analysis that has been

1 51 101 151 201 251 301 351 401 451
discussed in section 3.4 on all designs. The results are
Figure 16: Number of Patterns – 65nm cells listed in Figure 18. All runs were done with the newly
developed ATPG and fault simulator using the CA
On average over all 451 cells, the CA-ATPG needs to library models. First we performed a fault simulation of
generate about 13% more pattern as the SA-ATPG, i.e. the SA patterns followed by a fault simulation of the
on average 4.9 CA patterns instead of 4.3 SA patterns. EMD patterns. Finally we run the CA-ATPG to reach
the highest achievable defect coverage.
For both cell libraries the extraction, the analog fault
simulation, the generation of the cell-aware models and Test Coverage Coverage Increase
the ATPG runs can be done all within one day. Design Stuck-At EMD Cell Aware EMD Cell Aware
I73k 97,44% 97,98% 99,65% 0,54% 2,21%
I247k 98,46% 98,78% 99,49% 0,32% 1,03%
A simple defect coverage translation of the SA patterns
I449k 98,41% 98,75% 99,65% 0,34% 1,24%
from cell level to chip level can not be made. On chip- I671k 98,84% 99,01% 99,30% 0,17% 0,46%
level some of the missed input combination at cell-level I1652k 98,29% 98,30% 99,58% 0,01% 1,29%
might still be applied to that cell, because they are I1676k 98,80% 98,80% 99,26% 0,00% 0,46%
required to test another part of the chip. To quantify the I2181k 98,56% 99,03% 99,89% 0,47% 1,33%
real impact on chip level we created SA patterns for I2183k 98,32% 98,83% 99,35% 0,51% 1,03%
I2986k 98,02% 98,44% 99,85% 0,42% 1,83%
various industrial designs and evaluated these patterns
I6649k 98,20% 98,24% 99,72% 0,04% 1,52%
based on the CA model. The results of this evaluation Average 98,33% 98,62% 99,57% 0,28% 1,24%
are discussed in section 4.3.
Figure 18: Results achieved on Industrial designs
4.3 Results from Industrial Designs
In this section we provide details of our evaluation It can be concluded that the test coverage of the Stuck-
work, using the 90nm and 65nm CA library models for At patterns is on average about 1.2% lower than the
10 real industrial designs. The corresponding design maximal achievable test coverage, which can be
data is shown in Figure 17 . obtained by the CA-ATPG. The test coverage of the
EMD patterns is on average about 0.3% higher than the
Design Data test coverage of the Stuck-At patterns. The reported
Design #gates #FFs #chains #SA-faults #CA faults results indicate that EMD test patterns show no effect
I73k 73k 6k 29 363k 506k on the defect coverage of some designs. This effect is
I247k 247k 21k 34 1.2M 1.7M currently investigated in detail. As expected the CA-
I449k 449k 32k 35 2.0M 2.7M ATPG could target a large number of cell internal faults
I671k 671k 76k 128 3.4M 4.6M explicitly, moreover, the achieved coverage
I1652k 1,6M 135k 300 8.7M 9.8M improvement of 1.2% in average was outperforming
I1676k 1.7M 131k 381 8.6M 11.5M our expectation. An increase of the coverage of about
I2181k 2.1M 148k 70 12.2M 15.4M 1.2% has a significant positive impact on the quality of
I2183k 2.1M 135k 38 10.2M 12.8M the test pattern.
I2986k 2.9M 173k 114 14.9M 18.4M
I6649k 6.6M 457k 1011 37.2M 48.5M
5 Impact on Production Testing
Figure 17: Design data of 10 Industrial designs Of course, an interesting question to answer at this
point is: what will the impact be on test quality. It is
As an example, the last design named “I6649k” has 6.6 difficult to find a straight-forward answer as it is
million gates, 457k flip flops, and 1011 internal scan influenced by many factors, such as defect Pareto of the

Paper 1.2 INTERNATIONAL TEST CONFERENCE 8

underlying fabrication process, composition of the
entire test suite, circuit topology, DfM measures taken
in the cell library design, etc. Hence, we would like to
answer this question in two approximate ways:
• By a theoretical estimation
• By experimental data
It has to be noted that we explicitly exclude the impact
of fringe coverage through other pattern sets, such as
bridge patterns, delay fault patterns, IddQ test methods,
etc. Although such approaches may arguably reduce the
benefit of cell-aware ATPG, we strongly feel that in a
zero defect environment, such as the most challenging
automotive market segment, it is not good practice to
rely on fringe effects - the only metric that really counts
is a measurable one!
In the following section, we'll scale all results to per
square-millimeter of logic area to allow for easy
comparison between cores and designs.
5.1 Theoretical estimation
Defect levels are often estimated with the formula
postulated by Williams and Brown [15]: DLWB = 1 –
Y^(1-f). However, Agrawal, Seth, de Sousa and others
postulated other formulas as summarized in [16][17].
These formulas take additional aspects into account
such as that defects tend to cluster and that a single
defect can cause multiple faults. However, to take these
aspects into account also additional parameters are
introduced. Whilst none of the various formulas is
proven beyond doubt to be superior compared to all
others, a common denominator is that they all estimate
defect levels significantly lower than Williams and
Brown. Hence, we find it convenient and sufficient for
most practical purposes to approximate defect levels as
DLpragmatic=DLWB/4.
If we plug in the achieved coverage rate of 98.33% for
traditional stuck-at patterns, and assume an arbitrary
defect limited yield of 75% for a 100mm2 design, we
arrive at an escape rate of DLpragmatic = 12.0
ppm/mm2. Likewise, with coverage of 98.62% for
EMD patterns, the escape rate will be estimated at 9.9
ppm/mm2 with the difference of 2.1 ppm/mm2
attributed to the positive effect of EMD patterns. The
CA-ATPG reaches coverage of 99.57% corresponding
to an escape rate of 3.1ppm/mm2. In other words, it is
expected to detect an additional 8.4ppm/mm2 compared
to SA patterns.
5.2 Experimental data
In our previous work [9] we have shown experimental
data based on more than one million tested devices.
This data set contained 24.8 devices/mm2, which were
Paper 1.2 INTERNATIONAL TEST CONFERENCE
only detected by EMD patterns. Of course, we could
not simply imply that all of these devices would be
algorithmically detected with cell-aware ATPG.
Therefore we filtered them similarly as explained in
section 4.4 of [9]. This left us with 4.5 devices/mm2
compatible with cell internal faults. In [9] we have
shown on a larger dataset (namely, all devices surviving
a similar filter, not just EMD-only detects), that ~44%
of these devices can be explained with a cell-aware
approach. This amounts to ~2.0 devices/mm2.
Hence, we did attribute these devices to the incremental
coverage improvement of ~0.28% for EMD patterns.
We can then also estimate that an additional coverage
improvement of 1.2% with explicit CA patterns (as
achieved in average over 10 real industrial designs) will
detect an additional 8 devices/mm2.
6 Future work
The next step will be to prove the coverage gain, and
reduction in DPM levels, on real silicon on a large
number of tested devices in an production environment
at NXP. A second further task will be to provide the
CA-ATPG and the CA-Model generation as a
commercial feature. A third future task will concentrate
on enhancing the whole Cell-Aware flow to also
consider cell internal faults that require sequential test
patterns, e.g. for detecting cell internal opens.
In addition to sequential patterns we also want to
evaluate the effect of large defects, e.g. bridges between
three or more nets. Furthermore we intend to enhance
the CA-ATPG to enable and evaluate an Embedded-
Cell-Aware step. This will improve the defect coverage
without increasing the number of test pattern. In
addition we also intend to enhance the layout extraction
step, to include the layout X,Y coordinates for the
individual defects, such that these X,Y coordinates can
be passed on to the Electrical Failure Diagnosis
function to pin point directly to the location with in a
library cell.
7 Conclusion
We have shown that the quality of test patterns can be
improved significantly by explicitly targeting cell
internal faults, e.g. bridges. We have also proven that
Stuck-At patterns that only target faults at the library
cell ports, are not sufficient to detect all detectable cell
internal faults, e.g. bridges. The experiments performed
showed that only about 50% of all 90nm and 65nm
standard library cells are guaranteed to be tested
sufficiently with SA patterns. We further have proven
that EMD patterns are better than SA pattern, i.e. about
9
 0.3% higher coverage as with SA patterns. However,
Cell-Aware patterns which deterministically target
these defects are significantly better, i.e. about 1.2%
higher coverage than SA patterns. To achieve this, a
CA-ATPG has been developed, and CA library models
have been created by an automated flow. For an
industrial application it is intended, that the needed CA
models are created by library providers, and as such
design teams can generate high quality and layout
aware test pattern without using layout data. As shown
in section 5.1 the impact on production testing is
significant, a reduction of 8.4ppm/mm2, e.g. 420 ppm
for a 50mm2 design is expected.
8 Acknowledgements
The authors would like to thank Erik Jan Marinissen,
Bram Kruseman, Peter Weseloh and Michael Wittke for
their assistance, implementations, insight and valuable
discussion over the course of this project.
Parts of this work have been supported by the BMBF
within the project MAYA (Project ID 01M3172).
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