DCR-IP5/IP5E/IP7BT/IP7E

OPERATION MANUAL
 Contents
1. Format …………………….……………………….. 3 3. Servo Circuit …………………….………………… 30
2. Video/Audio Circuit Description …………………. 5 4. System Control Circuit …………………………… 32
2-1. Camera Record Mode ……………………………………….. 5 4-1. HI/Camera Controller ……………………………………….. 32
2-1-1. Video Signal …………………………………..…………….. 5 4-2. MIC (Cassette Memory) Driver ……………………….….…. 32
2-1-2. Audio Signal ………………………………..………..……… 9 4-3. Digital Still Controller …………………………………….… 33
2-2. LINE IN Record Mode …………….……………………….. 11 4-4. System Control Block Diagram ..……………………………. 34
2-2-1. Video Signal ………………………………………………… 11 4-5. MIC (Cassette Memory) Driver ……..………………………. 35
2-2-2. Audio Signal ………………………………………..………. 14 5. Bluetooth Circuit .………...………………………. 37
2-3. iLINK Input Record Mode ……………………..…..………. 16
2-3-1. Video Signal …………………………………….…….……. 16
2-4. Playback Mode …………….…………………..…..…..…… 17
2-4-1. Video Signal …………………………………..…….....…… 17
2-4-2. Audio Signal ……………………………………..…….…… 23
2-5. Digital Still Circuit ….…………………..…………….……. 25
2-5-1. Block Diagram …………………………………..…………. 25
2-5-2. Camera Movie Record Mode …………..…………..………. 27
2-5-3. Tape Movie Record Mode ………………..………………... 27
2-5-4. Movie Playback Mode …………………...………..……..… 28
2-6. System Clock Block Diagram ….……………………….….. 29

2
1. Format

What is the MICROMV system? MICROMV system DV system

Y signals recording Digital Digital
The "MICROMV" system is developed to realize the video equipment that is system
compact having high picture quality with high connectivity with network. Horizontal resolution About 500 lines About 500 lines
The MPEG2 system is used as the picture compression technology having the Sampling frequency 13.5 MHz 13.5 MHz
transfer rate of 12 Mbps. It realizes the high recording and playback density Quantized bit number 8 bits 8 bits
that is about 3 times higher than that of the conventional DV system with the Chroma signal recording Digital (color difference) Digital (color difference)
development of new technology while maintaining the high picture quality system
that is equivalent to that of DV. Sampling frequency 6.75 MHz 3.375 MHz (NTSC)
6.75 MHz (PAL)
[Recording system on tape] Quantized bit number 8 bits 8 bits
In the "MICROMV" system, picture data and sound data are effectively Transfer rate (video) 12 Mbps 25 Mbps
recorded in a single area. The data such as the error correction data for higher Signal compression system MPEG2 Compression within frame
reliability and the search data for higher operability are recorded at the same Audio recording system MPEG1 Audio Layer2 Non-compression
time with high density. The "MICROMV" system has attained the high Tape width 3.8 mm 6.35 mm
degree of established technology. Cassette size (volume) 46×30.2×8.5 mm 66×48×12.2 mm (mini DV)
3 3
(About 12 cm ) (About 39 cm )
Signal recording and Recording/Playback Recording/Playback
playback system rotation by 2 dedicated rotation by 2 heads that
heads respectively are commonly used
Drum rotation/ 6000 rpm/21.7 mm 9000 rpm/21.7 mm
Drum diameter
Tape speed (mm/second) 5.657 18.812 (NTSC SP)
18.831 (PAL SP)
Track pitch (µm) 5 10 (SP)
Cassette memory Built-in (64 kbits) Option

[Conceptual drawing of tape recording pattern]

3
[High density recording and playback technology that realizes about 3 times higher density than that of
the conventional DV system]

Recording with shorter wavelength

The shortest recording wavelength of 0.29mm is realized in the "MICROMV"
system. By this technology, more data can be recorded in the track of the same
length. Realization of such a short wavelength recording is supported by the
development of the high output MR head (Magneto-Resistive Head) for VTR use.
The MR head that has been used in hard disk of personal computer, can detect
magnetic force of tape since resistance value of the MR element changes in
accordance with the change of magnetic force on tape as the sense current flows
in the MR head. Thus the MR head can pick up the magnetic force that becomes
minute as the recording wavelength becomes shorter.

Narrower track
The track pitch as narrow as 5mm is realized. With the introduction of narrower
track pitch, we have developed a new technology that enables more number of
tracks in the same length of tape. Because the conventional VTR scans the
recorded tracks only once by rotating head and the entire track must be read with
the single scan, the recording track must have track width of sufficient width.
The "MICROMV" system has realized the recording and playback track width of
5mm. Introduction of the narrow track width is supported by the "double-scan
system playback". In the double-scan system, every data that is recorded on track
is played back twice and the optimum playback data is selected.

4
2. Video/Audio Circuit Description
2-1. Camera Record Mode
2-1-1. Video Signal
CCD Imager (LD-105 board, IC701)
The CCD imager is driven by the pulses (V1 to V4, H1, H2 and RG)
that are supplied from the timing generator, and outputs the CCD OUT
signal.
Timing generator, CDS, AGC, A/D Converter
(VC-263 board, IC1901)
Timing Generator
The 48 MHz original oscillator signal is frequency-divided to generate
the timing pulses for the camera system. The 48 MHz original oscillator
signal is also frequency-divided to generate the TGCK signal (Pin-og,
24 MHz) that is the clock signal for the camera/base band signal
processing systems.
CDS
The CCD OUT signal is sampled by the correlated double sampling
with the pulse generated by the timing generator block in order to
remove the CCD noise and separate the video signal only.
AGC
If the shooting object is dark and the sufficient video signal level cannot
be obtained even though the iris is fully opened, gain of the AGC
amplifier is increased.
A/D Converter
The video signal is A/D converted to the 10-bit digital signal by the
clock generated by the timing generator block.
Camera Process, Feature Process and Base Band Process
(VC-263 board, IC401)
Camera Process
The Y-signal and the R, G, B signals are separated from the camera video
signal (10-bit digital signal). These signals receive the camera signal
processing such as white balance adjustment and gamma correction.
The processed signals are sent to the matrix circuit that outputs the Y-
signal and the chroma signal (CR signal (R-Y signal) and CB signal (B-Y
signal)). Sampling frequency of the Y-signal is 13.5 MHz and the
quantization bit number is 8 bits. The chroma signal is the sequential
signal consisting of the CR signal and the CB signal. The sampling
frequency of the chroma signal is 6.75 MHz and the quantization bit
number is 8 bits.
Feature Process
The signal processing such as digital effect and picture effect are
performed. The Y-signal and the chroma signal are sent once to the
picture process IC (IC1801) and then are returned to IC401. (The still
picture process IC performs reading and compression of still picture in
the memory mode.)
Base Band Process
The Y-signal and the chroma signal take the four signal paths. The
recording signals are sent to the MPEG video encoder (IC601) as they
are. Regarding the base band signal for the A/V terminal, theY-signal is
D/A converted after sync signal is added, and the chroma signal is D/A
converted after it is encoded to the NTSC (or PAL) chroma signal. The
D/A converter output is sent to the video I/O IC (IC101). The base band
signals for EVF and for LCD are sent to the matrix circuit where the
signals are converted to the RGB signal, and then D/A converted. The
D/A converted signals are sent to the respective circuits.
5
Video signal block diagram for circuit description -1 (Camera recording mode)

6
MPEG Video Encoder (VC-263 Board, IC601)
The Y-signal and the chroma signal are compressed by the MPEG2 system.
In the conventional DV system, the signal is compressed in units of one
frame. In the MPEG2 system, the signal is compressed in two or more
frames and the correlation between frames is also used. Thus the high
signal compression rate is obtained in the MPEG2 system.
DV system compression rate = About 1/5
MPEG2 system compression rate
(in the case of this machine)= About 1/14
The compressed video signal is output to the Q-process IC (IC801).
Q-Process IC (VC-263 Board, IC801)
The compressed audio signal is added to the MPEG2-compressed video
signal so that the compressed video/audio signal is generated. This signal
takes the two signal paths. The compressed video/audio signal for iLINK
is output to the iLINK terminal via the iLINK interface (IC701). The
compressed video/audio signal for recording is added by the ECC (Error
Correction Code) and is converted to the recording data string (1-bit serial
data). The recording data string is output to the REC/PB amplifier (IC902)
in accordance with the rotating timing of the recording heads.
REC/PB Amplifier (VC-263 Board, IC902)
The recording data string (recording RF signal) is current-amplified and is
supplied to the recording heads.Because the recording heads are installed
in the offset position with respect to the playback heads, and because the
signal is recorded only once per every two rotations of drum due to the use
of the double scan system, the recording current is supplied to the
recording heads only during the period when the recording head is
maintaining contact with tape using the XREC ACT P signal and the
XREC ACT M signal.
Recording Head
Recording heads are the ordinary induction type heads.

7
Video signal block diagram for circuit description -2 (Camera recording mode)

8
2-1-2. Audio Signal

Audio I/O Circuit (VC-263 board, IC201)

The MIC signal is amplified by the AGC amplifier, passes through the
input selector and is output to the A/D converter (IC202).
A/D Converter (VC-263 board, IC202)
The analog audio signal is converted digital audio signal and is output
to the base band process IC (VC-263 board, IC401). (AD IN signal)
(Quantization bit number = 16 bits, sampling frequency = 48kHz)
Base Band Process (VC-263 board, IC401)
The audio signal is sent once to the still picture process IC (IC1801)
(ASI signal) and is returned to IC401 (ASO signal). (The still picture
process IC compressed the audio signal during the memory mode and
during movie recording mode.) The audio signal takes the two signal
paths. The audio signal for recording is sent to the MPEG audio encoder
(IC501) (ARECD signal). The audio signal for the A/V terminal is
output to the D/A converter (IC202) (DA OUT signal).
MPEG Audio Encoder (VC-263 board, IC601)
The audio signal is compressed by the MPEG1 Audio Layer2 system.
(Compression rate = about 1/6. Note that audio signal is not compressed
in the DV system.) The compressed audio signal is output to the Q-
process IC (IC801) (AENCD signal) and is added to the compressed
video signal. The remaining circuits are the same as those of the video
signal system.
D/A Converter (VC-263 board, IC202)
The digital audio signal is converted to the analog audio signal and is
output to the Audio I/O circuit (IC201).
Audio I/O Circuit (VC-263 board, IC201)
The analog audio signal is amplified and is output to the A/V terminal.

9
Audio signal block diagram for circuit description (Camera recording mode)

10
2-2. LINE IN Record Mode
2-2-1. Video Signal
Video I/O (VC-263 board, IC101)
When the input video signal is connected to the S VIDEO connector,
the Y-signal is amplified by the AGC amplifier and is sent to the base
band process IC (IC401). The chroma signal is also amplified by the
AGC amplifier as the ACC and is sent to the base band process IC
(IC401). When the input video signal is connected to the VIDEO
connector, the video signal is amplified by the AGC amplifier and is
sent to the base band process IC. The Y/C separation is performed
inside the base band process IC.
Base Band Process, Feature Process (VC-263 board, IC401)
Base Band Process (1)
The Y-signal and the chroma signal are converted by the A/D
converted. Sampling frequency is 13.5 MHz and the quantization bit
number is 8 bits. The chroma signal is demodulated to the CR signal
and the CB signal that are encoded to the sequential signal. Sampling
frequency of the CR signal and the CB signal is 6.75MHz and the
quantization bit number is 8 bits.
Feature Process
The processing such as digital effect and picture effect are performed.
The Y-signal and the chroma signal are sent once to the still picture
process IC (IC1801) and are returned to IC401 again.
Base Band Process (2)
The Y-signal and the chroma signal take the three signal paths. The Y-
signal and the chroma signal for recording are sent to the MPEG video
encoder (IC601) as they are. The Y-signal and the chroma signal for
EVF and for LCD are sent to the matrix circuit that converts these
signals to the RGB signal. After these signals are converted by the
D/A converter, they are sent to the respective circuits.

11
Video signal block diagram for circuit description (LINE IN recording mode)

12
MPEG video encoder (VC-263 board, IC601)
The Y-signal and the chroma signal are compressed by the MPEG2
system.The compressed video signal is output to the Q-process IC (IC801).
Q-process IC (VC-263 board, IC801)
The compressed audio signal is added to the video signal that is
compressed by MPEG2 to generate the video/audio signal. ECC (Error
Correction Code) is added to the recording signal to convert the recording
signal to the recording data string (1-bit serial data). The recording data
string is output to the REC/PB amplifier (IC902) in accordance with the
rotating timing of the recording heads. The subsequent circuits are exactly
same as those of the camera recording mode. Note that the iLINK signal is
not output during the LINE IN mode.

13
2-2-2. Audio Signal

Audio I/O Circuit (VC-263 board, IC201)

The input audio signal that is connected to the A/V terminal is amplified
by the AGC amplifier, passes through the input selector and is output to
the A/D converter (IC202).
A/D Converter (VC-263 board, IC202)
The analog audio signal is converted to the digital audio signal (AD IN
signal).
Base Band Process (VC-263 board, IC401)
The audio signal is once sent to the still picture process IC (IC1801)
(ASI signal) and then returned to IC401 (ASO signal). The audio signal
takes the two signal paths.The audio signal for recording is sent to the
MPEG audio encoder (IC501) (ARECD signal). The audio signal for
the A/V terminal/speaker is output to the D/A converter (IC202) (DA
OUT signal).
MPEG Audio Encoder (VC-263 board, IC501)
The audio signal is compressed by the MPEG1 Audio Layer2 system
and is output to the Q-process IC (IC801). The audio signal is added to
the compressed video signal at the Q-process IC. The subsequent
circuits are the same as those of the video signal system.
D/A Converter (VC-263 board, IC202)
The digital audio signal is converted to the analog audio signal and is
output to the Audio I/O circuit (IC201).
Audio I/O Circuit (VC-263 board, IC201)
The analog audio signal is amplified and is output to the speaker.

14
Audio signal block diagram for circuit description (LINE IN recording mode)

15
2-3. iLINK Input Record Mode
2-3-1. Video Signal
iLINK Interface (IC701)
The serial data from the iLINK terminal is converted to the 8-bit parallel
data and is output to the Q-process IC.
Q-process IC (VC-263 board, IC801)
The 8-bit parallel data takes the two paths.ECC (Error Correction Code)
is added to 8-bit parallel data for recording. Then the 8-bit parallel data is
converted to the recording data string (1-bit serial data). The recording
data string is output to the REC/PB amplifier (IC902) in accordance with
the rotating timing of the recording heads. The subsequent circuits are
exactly same as those of the camera recording mode. The signal for
monitor is separated to the video signal and the audio signal. The video
signal for monitor is output to the MPEG video decoder (IC601). The
subsequent circuits are exactly same as those of the playback mode. The
audio signal for monitor is output to the MPEG audio decoder (IC501).
The subsequent circuits are exactly same as those of the playback mode.

16
2-4. Playback Mode
2-4-1. Video Signal
Playback Head (MR Head)
Because the track width on tape is narrow (5µm= 1/2 of the DV system)
and the shortest recording wavelength is short (0.28 µm = 1/2 of the DV
system), the sufficient output signal cannot be obtained by the
conventional induction type head. So the MR (Magneto-Resistive Head)
is used.In the MR head, resistance value of the MR element changes in
accordance with the change of magnetic force. Therefore, DC bias is
required to convert the change of resistance value to the change of
voltage. Due to the above described reason, the rotary drum contains the
built-in head amplifier IC (for P-channel and for M-channel) of the MR
head and also contains the power regulator/head selector IC in it.
Power Transmission IC (VC-263 board, IC951)
During playback, the PW (+) signal (130kHz signal) and the PW (-)
signal (130kHz signal, inverted phase of the PW (+) signal) are output.
These signals are sent to the drum and is input to the rotating drum
through rotary transformer. These signals are rectified and stabilized by
the power regulator, and become the power of the MR head amplifier.
REC/PB amplifier (VC-263 board, IC902)
The playback RF signal is phase-compensated by the EQ (equalizer)
circuit, is adjusted of its level by the AGC circuit and is output to the Q-
process IC (IC801). At the same time, the playback RF signal is
envelope-detected and is output to the Q-process IC.

17
Video signal block diagram for circuit description -1 (Playback mode)

18
Q-process IC (VC-263 board, IC801)
Because the double scan system is used in this machine, data of the same
track is played back twice. Then the optimum playback data is selected by
the envelope detection signal (ENV OUT). The playback data string is re-
aligned so that it meets the playback system and data error is corrected by
ECC (Error Correction Code). The playback signal takes the two signal
paths.The playback signal for iLINK is output to the iLINK terminal via
the iLINK Interface (IC701). The playback signal for A/V terminal is
separated into the video signal and the audio signal. The video signal is
output to the MPEG video decoder (IC601). The audio signal is output to
the MPEG audio decoder (IC501).
MPEG Video Decoder (VC-263 board, IC601)
The compressed video signal is decompressed to the Y-signal and the
chroma signal (sequential signal consisting of CR signal and CB signal)
and is output to the base band process IC (IC401).

19
Video signal block diagram for circuit description -2 (Playback mode)

20
Base Band Process , Feature Process (VC-263 board, IC401)
Base Band Process (1/2)
The Y-signal and the chroma signal that are supplied from the MPEG
video decoder are sent to the Feature process circuit.
Feature Process
The Y-signal and the chroma signal are once sent to the still picture
process IC (IC1801) and are then returned back to IC401. (The still picture
process IC reads and compresses the still picture during the memory mode.)
Base Band Process (2/2)
The Y-signal and the chroma signal take the three signal paths. Regarding
the Y-signal and the chroma signal for the A/V terminal output, the Y-
signal is D/A converted and sent to the video I/O IC (IC101) after sync
signal is added. The chroma signal is encoded to the NTSC (or PAL)
chroma signal and then D/A converted and sent to the video I/O IC (IC101)
respectively. The Y-signal and the chroma signal for EVF and for LCD are
sent to the matrix circuit where the signals are converted to the RGB signal,
and then D/A converted. The D/A converted signals are sent to the
respective circuits.

21
Video signal block diagram for circuit description -3 (Playback mode)

22
2-4-2. Audio Signal

MPEG Audio Decoder (VC-263 board, IC501)

The compressed audio signal is decompressed back to the original
signal and is output to the base band process IC (IC401) (APBD signal).
Base Band Process (VC-263 board, IC401)
The audio signal is once sent to the still picture process IC (IC1801)
(ASI signal), and then returned back to IC401 (ASO signal). (The still
picture process IC compresses the audio signal during memory mode
and during the movie recording mode. The compressed audio signal is
decompressed back to the original signal during the movie playback
mode.) The audio output selection is performed so that the selected
audio signal is output to the A/D converter (IC202).
D/A Converter (VC-263 board, IC202)
The digital audio signal is converted to the analog audio signal and is
output to the Audio I/O Circuit (IC201).
Audio I/O Circuit (VC-263 board, IC201)
The analog audio signal is amplified and is output to the A/V terminal
and speaker.

23
Audio signal block diagram for circuit description (Playback mode)

24
2-5. Digital Still Circuit
2-5-1. Block Diagram
Flash memory (VC-263 board, IC1802)
Still Picture Process (VC-263 board, IC1801) The compressed picture data is saved in the flash memory. Also the
During the still picture recording mode, still picture is fetched from the EVR data (B page data) of the Digital Still Controller (IC1606) is also
video signal (motion picture signal) that is supplied from IC401 saved in this flash memory.
(camera/base band process). The fetched picture is compressed by the Digital Still Controller (VC-263 board, IC1606)
JPEG system. During the still picture playback mode, the JPEG- It controls the digital still circuit. It sends and receives the picture and
compressed video signal (still picture signal) is decompressed to the sound data to and from a personal computer via USB port. It writes and
original signal and is output to IC401. During the movie recording into reads the picture and sound data to and from memory stick. In the
memory stick, the audio signal that is supplied from IC401 is network mode, it is connected to Internet through the Bluetooth circuit
compressed by the MPEG1 system. During the movie playback from (BT-003 board).
memory stick, the audio signal that is compressed by MPEG1 system is
decompressed to the original signal. During the above described
operations, SDRAM (IC1803) is used as the work area.
SDARM (VC-263 board, IC1803)
This is the work area for IC401 (camera/base band process) and the
Digital Still Controller (IC1606).

25
Digital still circuit block diagram

26
2-5-2. Camera Movie Record Mode
Video Signal
The CCD output video signal is amplified by AGC amplifier and
receives the CDS processing at IC1901. Output signal of IC1901 is A/D
converted and is input to IC401 where the video signal passes through
the camera process circuit. The video signal is once output to IC1801
(still picture process) and then returned back to IC401. The returned
video signal is output to the A/V terminal, to the EVF circuit and to the
LCD circuit. It is at the same time output to IC601 (MPEG video
encoder). (Up to this circuit, the signal path is same as that of the
camera record mode.) The video signal is compressed by the MPEG1
system in IC601. Digital Still Controller (IC1606) reads the compressed
video signal through the data bus line (D0 to D7). The Digital Still
Controller mixes this video signal with the audio signal that is supplied
from IC1801 (still picture process). The mixed video and audio signal
are written in memory stick.
Audio Signal
The MIC audio signal is amplified by IC201, A/D converted by IC202
and then input to IC401. This signal is output to the A/V terminal and at
the same time is output to IC1801 (still picture process). (Up to this
circuit, the signal path is same as that of the camera record mode.)The
audio signal is compressed by the MPEG1 system in IC1801. The
Digital Still Controller (IC1606) reads the compressed audio signal
through the data bus line (D0 to D15).
2-5-3. Tape Movie Record Mode
Video Signal
The playback signal that is picked up from tape is amplified by the head
amplifier and the REC/PB amplifier (IC902) The amplified signal
receives error correction and the data string conversion at IC801 (Q-
process). The playback signal is sent to the branched to the iLINK
terminal signal and then is separated to the video signal and to the audio
signal. The video signal is output to IC601 (MPEG video decoder) and
the audio signal is output to IC501 (MPEG audio decoder). (Up to this
circuit, the signal path is same as that of the VTR playback mode.)The
compressed video signal is decompressed to the original signal by
MPEG2 system at IC601 and is output to IC401 (base band process).
The video signal is sent from IC401 to IC1801 (still picture process)
once and is then returned back to IC401. The returned signal is output to
the A/V terminal, to the EVF circuit and to the LCD circuit. At the same
time, this signal is output to IC601 (MPEG video encoder) again.The
video signal is compressed by the MPEG1 system at IC601. The Digital
Still Controller (IC1606) reads the compressed video signal through the
data bus line (D0 to D7). The Digital Still Controller mixes the video
signal and the audio signal. The mixed video and audio signals are
written into memory stick.
Audio Signal
The audio signal that is separated from the video signal, is input to
IC501 (MPEG audio decoder).The compressed audio signal is
decompressed back to the original signal by the MPEG1 system at
IC501. The audio signal is sent to IC401 (base band process). The audio
signal is then output from IC401 to the A/V terminal and to speaker. At
the same time, the audio signal is sent to IC1801 (still picture process)
where the audio signal is compressed by the MPEG1 system. (See note.)
The Digital Still Controller (IC1606) reads the compressed audio signal
through the data bus line (D0 to D15).
Note: Bit rate of this signal is different from the signal that is
recorded on tape.
27
2-5-4. Movie Playback Mode

Video Signal
The Digital Still Controller (IC1606) reads the data that is recorded in
memory stick. The video data is output to IC601 (MPEG video decoder)
through the data bus line (D0 to D7) and the audio signal is output to
IC1801 (still picture process) through the data bus line (D0 to D15).
The compressed video signal is decompressed to the original signal by
IC601 and is output to IC401 (base band process) where the video
signal is once sent to IC1801 (still picture process) and is returned back
to IC401 again. The returned signal is output to the A/V terminal, to the
EVF circuit and to the LCD circuit.
Audio Signal
The compressed audio signal is decompressed to the original signal by
IC1801 (still picture process) and is output to IC401 (base band process)
where the audio signal is output to the A/V terminal and to speaker.

28
2-6. System Clock Block Diagram
The system clock block diagram is shown below.
The following clock signals are phase-locked to the input signal (input sync
signal) when external signal is input (LINE IN mode or iLINK input mode).
PLL27MCK
AUCKFS
AUCK64FS
AUCK256FS

29
3. Servo Circuit
Servo circuit is almost same as that of the DV system but the following
points are different.
z Numbers of rotations of drum and capstan are different. (See the table
below.)
z The capstan phase servo (ATF) is not applied during playback.
(ATF is not necessary because the double capstan system is used.)
z The analog voltage of the CAP FG signal is detected in order to control the
tape run precisely.

MICROMV system DV system (J mechanism)

Number of drum rotations (rpm) 6000 9000
Drum FG frequency (Hz) 600 900
Drum PG frequency (Hz) 100 150
Tape speed (mm/sec) 5.657 18.81 (SP)
12.56 (LP)
Capstan FG frequency (Hz) About 360 About 1080 (SP)
About 720 (LP)

30
Servo circuit block diagram for circuit description

31
4. System Control Circuit
The system control circuit of this machine consists of the three controllers.
They are the HI/Camera Controller that is the master controller controlling the
entire system and the two slave controllers that are the Mechanism Controller
and the Digital Still Controller.

4-1. HI/Camera Controller 4-2. Mechanism Controller

Role of HI/Camera Controller Role of Mechanism Controller
HI Control Block Control of mechanism block
Mode control of entire system Control of servo circuit
Communication with Mechanism Controller and the Digital Still Control of video and audio circuit
Controller Control of EVF and LCD circuits
Detection of RESET input and resetting the entire system Control of iLINK I/F
Control of DC-DC converter and charge circuit EVR Data of Mechanism Controller
Detection of key input EVR data (pages 4, 8, 9 and C) of Mechanism Controller are written in
Detection SIRCS (infrared remote control) input the EEPROM (IC1102).
Communication with InfoLITHIUM battery
Control of character generator
Communication with timer IC
Communication with cassette memory
Camera Control Block
Control of camera process circuit
Control of timing generator, CDS, AGC, A/D converter circuit
Control of EVR IC
Control of lens (iris meter and ND filter meter)
EVR Data of HI/Camera Controller
EVR data (pages 7, D, E and F) of HI/Camera Controller are written in
the EEPROM (IC1202).

32
4-3. Digital Still Controller
Role of Digital Still Controller
Control of digital still circuit
USB communication
Communication with memory stick
Communication with Bluetooth circuit
Networking function
EVR Data of Digital Still Controller
EVR data (page B) of Digital Still Controller are written in the flash
memory (IC1802).

33
4-4. System Control Block Diagram

34
4-5. MIC (Cassette Memory) Driver
The MICROMV system is different from the DV system in the point that
writing and reading data to and from cassette memory without using any
contactor points. When communication between the DCR machine and
cassette memory starts, the MIC driver (VC-263 board, IC952) outputs the
13.5 MHz carriers (MIC1 and MIC2) that drive the MIC antenna of
mechanism deck. (The HI/Camera Controller controls it with the SW CTL
signal.) Inside cassette, antenna receives the magnetic flux generated by the
MIC antenna and rectifies it and uses the rectified power as the power source
of the cassette memory (EEPROM). The write data that is going to be written
in the cassette memory, is output from the HI/Camera Controller (VC-263
board, IC1203) in the form of serial data (MIC SO). This serial data (MIC SO)
is converted to the serial data for cassette memory (BSD IN) by the
camera/base band process IC (VC-263 board, IC401). The 13.5 MHz carrier is
amplitude-modulated by the BSK IN signal in the MIC driver. Inside a cassette,
change of magnetic flux is detected and the data is demodulated. The
demodulated data is written in the memory.
To read data from cassette memory, the load impedance of the antenna inside a
cassette is changed by the output data (serial data) of the cassette memory. As
the load impedance changes, amplitude of the 13.5 MHz carrier is changed at
the MIC antenna of the DCR machine. This change of amplitude is detected in
the MIC driver. The data is demodulated and is output to the camera/base band
process IC (BSD OUT). This serial data is converted to the serial data for
HI/Camera Controller (MIC SI) by the camera/base band process IC and is
output. Writing and reading data to and from cassette memory are performed
during cassette loading or cassette ejection only. Therefore, all data of a
cassette memory are read into IC1205 (64-kbit EEPROM) so that
writing/reading of data between IC1205 and the DCR machine are performed
only during recording and playback modes.
35
MIC (Cassette Memory) Driver Block Diagram

36
5. Bluetooth Circuit
Bluetooth is the standard that enables a personal computer to be connected to Base Band Circuit (IC101, 102, 104)
peripheral devices with wireless communication. The DCR machine can be Serial communication is performed with the Digital Still Controller
connected to Internet using the modem adapter (BTA-NW1) and cellular (VC-263 board, IC1606).
phone in which the Bluetooth function is installed. It also controls the Bluetooth communication.
(Networking function) RF Circuit (IC103)
Specifications of the Bluetooth communication of this machine are shown This circuit performs the GPSK modulation/demodulation and
below. frequency hopping control.
Communication system Bluetooth standard specifications Ver.1.1
Maximum communication speed About 723kbps
*1 *2
Frequency band in use 2.4 GHz band
Diffusion modulation system Frequency hopping system spectrum
diffusion *4
Primary modulation system GFSK (Gaussian Frequency Shift Keying)
Maximum distance of About 10 m maximum in visible distance
communication *2 (When "BTA-NW1" is used)
Supported Bluetooth profile *3 Generic Access Profile
Dial-up Networking Profile

*1 : The maximum communication speed of the Bluetooth standard

specifications Ver.1.1
*2 : It changes depending on obstacles between communication equipment
and radio wave conditions.
*3 : This is the specification that suits to the purpose of application of the
equipment in which Bluetooth function is installed. It is determined by
the Bluetooth standard specification.
*4 : In the Bluetooth communication, 79 channels of the communication
channel having 1 MHz bandwidth are used. The channels are switched
1600 times every second.

37
Bluetooth circuit block diagram for circuit description

38
9-929-923-21 2002A1600-1
Sony EMCS Co. ©2002.1
Published by DI Customer Center

DCR-IP5/IP5E/IP7BT/IP7E

39