DAYANANDA SAGAR COLLEGE OF

ENGINEERING
(An Autonomous Institute affiliated to VTU, Approved by AICTE & ISO 9001:2008 Certified)
Accredited by National Assessment & Accreditation Council (NAAC) with ‘A’ grade}
Shavige Malleshwara Hills, Kumaraswamy Layout, Banglore-560078.
(2019-2020)

Department of Electronics and Communication Engineering

AAT 1 Report on
“4 BIT BAUGH WOOLEY MULTIPLIER”
AAT 1 report submitted in partial fulfilment of award of the degree of
Master of Technology
in
VLSI DESIGN AND EMBEDDED SYSTEMS

SUBMITTED BY
RASHMI S
III SEMESTER (1DS18LVS07)

Under the guidance of

Dr. JAMUNA S
Professor
Dept. of Electronics & Communication Engineering
Dayananda Sagar College of Engineering
Bangalore-560078

(2019-2020)
 Department of Electronics and Communication Engineering

CERTIFICATE
This is to certify that the Technical Seminar report entitled “HARDWARE-EFFICIENT LOGIC
CAMOUFLAGING FOR MONOLITHIC 3D IC s”, is carried out by RASHMI S [II SEMESTER
(1DS18LVS07)] in partial fulfilment for the award of Degree of Master of Technology in VLSI DESIGN AND
EMBEDDED SYSTEM prescribed by VISVESVARAYA TECHNOLOGICAL UNIVERSITY, BELGAUM
during the academic year of 2018-2019. The Technical Seminar report prepared from refereed journal and conference
papers has been approved as it satisfies the academic requirements prescribed for the said degree.

Signature of the PG Coordinator

Dr. Kiran Gupta

Signature of the HOD Signature of Director, PG studies

Dr.T.C.Manjunath Dr. A Sreenivasan

Name of the Examiners Signature with Date

1.
2
 ACKNOWLEDGEMENT

I am grateful to Dr.C.P.S Prakash, principal, Dayananda Sagar College of Engineering, Bangalore,

for his continuous support throughout the completion of this report.

I would like to take this opportunity to thank and express my gratitude to Dr. A Sreenivasan, PG
Director, Dayananda Sagar College of Engineering, Bangalore. His incessant encouragement and valuable
technical support have been immense help in realizing this seminar.

I would also express my thanks to Dr.T.C.Manjunath, HOD, Department of Electronics and

communication Engineering, Dayananda Sagar College of Engineering, Bangalore. His incessant
encouragement and valuable technical support have been immense help in realizing this seminar.

I would take this opportunity to express my sincere gratitude to Dr. Kiran Gupta, PG Co-ordinator,
Dept. E&C for her guidance gave us the environment to enhance our knowledge, skills and to reach the
pinnacle with sheer determination, dedicated and hard work

RASHMI S
 ABSTRACT

Circuit camouflaging is a layout-level technique to thwart image analysis based reverse engineering
attacks. An efficient dummy contact based camouflaging method for monolithic three-dimensional (3D)
integrated circuits (ICs) is proposed. 3D ICs achieve ultra-high density device integration enabled by fine-
grained monolithic inter-tier vias (MIVs). Standard cell libraries are developed to evaluate the effects of
circuit camouflaging on large-scale 2D and monolithic 3D ICs. These libraries are used to design a
camouflaged SIMON (lightweight block cipher) and several academic benchmarks. Simulation results
demonstrate that the monolithic 3D technology is highly effective to facilitate the utilization of camouflaging
technique against reverse engineering attacks. At the expense of a slight degradation in timing characteristics,
monolithic 3D technology eliminates not only the area, but also the power overhead related to camouflaging.
 CONTENTS
Page No.
CHAPTER 1 INTRODUCTION 1
1.1 INTRODUCTION TO FINFET TECHNOLOGY 1
CHAPTER 2 LITERATURE SURVEY 3
CHAPTER 3 DOUBLE-GATE CMOS 7
3.1 DOUBLE GATE FET 7
3.1.1 Overcoming obstacles by Doubling up 7

3.2 DOUBLE-GATE TAXONOMY 8

3.2.1 Type I, the Planar DG-FET 8

3.2.2 Type II , the vertical DG-FET 9
3.3.3 Type III , non planar FINFET 9
3.3 THE DOUBLE-GATE CHALLENGE 9
CHAPTER 4 FIN-FIELD EFFECT TRANSISTOR 12
4.1 FinFET 12
4.2 FEATURES OF FINFET 13
4.3 FinFET FABRICATION 14
4.4 CHACTERSTICS OF FinFET 16
4.5 FinFET CHALLENGES 16
4.16 APPLICATIONS OF FinFETs 17
CHAPTER 5 RESULT AND DISCUSSION 17
CHAPTER 6 FUTURE SCOPE AND CONCLUSION 23
6.1 RECENT WORK AND FUTURE SCOPE 23
6.2 CONCLUSION 24
REFERENCES 25
 LIST OF FIGURES
Figure No. Name of figure Page No.
Fig 1.1 (a) Planar Mosfets 2
(b) 3d FinFETs 2
Fig 2.1 Fabrication process for 4T FinFETs 3
Fig 2.2 Schematic of NBE system 4
Fig 2.3 SEM view of silicided gate FinFET 6

Fig 3.1 Schematically illustrates the advantage of DG-FETs. 7

Fig 3.2 IDS –VGS characterstics of DG & SG FETs. 8

Fig 3.3 Type I,The Planar DG-FET. 9

Fig 3.4 Type II, The Vertical DG-FET 9
Fig. 3.5 Type III, Non Planar DG-FET 9
Fig 4.1 3D view of FinFET 12
Fig 4.2 FinFET Structure 13
Fig 4.3 Illustrates both processes. 14
Fig 4.4 I-V characterisrics 16
Fig 5.1 1 SEM plane view of 3T FinFET 18
Fig 5.2 SEM Plane view of 4T FinFET 18
Fig 5.3 Drain current versus gate voltage 19
Fig 5.4 Neutralization efficiency as a function of acceleration potential 19
Fig 5.5 STEM images 20
Fig 5.6 I-V characteristics 20
Fig 5.7 Id – Vd characteristics of NiSi gated Finfets 22
Fig 5.8 Comparison of gate leakage 22