Advanced Verification and Debug

0-In Clock-Domain Crossing

D A T A S H E E T

Major product features:

• Automated solution for complete
clock-domain crossing (CDC)
verification
• Identifies all clock domains,
including derived clocks and
gated clocks
• Identifies all CDC synchronizers,
including structured, ad-hoc, and
user-defined synchronizers
• Highlights missing and incorrect
CDC synchronization

0-In CDC is the industry’s most comprehensive and easy-to-use clock-domain • Detects and reports combination-
crossing verification solution, integrating advanced verification engines with ally and sequentially reconvergent
engineered methodologies. Using 0-In CDC, customers can efficiently and CDC signals
effectively eliminate all clock-domain crossing problems from their designs. • Highlights CDC reconvergence
that matches known bug signa-
tures
The CDC Verification Challenge designed to ensure proper transmission
and reception of data. The third problem • Automatically generates CDC
Modern system-on-chip (SoC) designs
protocol monitors with built-in
typically contain many separate clock is incorrect logic function where CDC
coverage support
domains. In hardware, clock-domain signals reconverge (i.e., CDC combina-
crossing (CDC) signals are often subject tional and sequential reconvergence). To • Verifies CDC protocols in
to the effects of metastability. However, avoid this, designers must perform exten- simulation using 0-In Assertion
the effects of metastability cannot be sive manual analysis wherever CDC Synthesis system
analyzed using conventional RTL simu- signals reconverge. Using 0-In® CDC, • Exhaustively verifies CDC
lation. As a result, many CDC-related designers can verify that their designs are functionality using formal
functional bugs go undetected until free of all three types of CDC problems. verification technology
post-silicon verification. • Fully IEEE 1364 Verilog
Designs with CDC signals encounter Ease of Use
language compliant, including
three fundamental types of problems — 0-In CDC accepts a wide variety of non-synthesizable code
all are caused by metastability. The first Verilog coding styles, including non-
problem is propagation of metastability. synthesizable constructs common in early
To avoid this, designers use synchro- stages of designs. In addition, 0-In CDC
nizers to reduce the probability that can be run early in the design process, in
metastability leaks into general logic a fully static mode, with no testbench.
throughout the design. The second 0-In CDC supports Verilog simulator
problem is corruption of data transferred command line arguments, so integration
across clock domains. To avoid this, into existing design environments is
designers implement CDC protocols simple. 0-In CDC is fast and has large

w w w. m e n t o r. c o m
capacity, so it can be used after every
design change, before code check-in. 0-In
CDC makes an ideal regression tool.
CDC Static Analysis
0-In CDC uses fast static RTL
analysis to automatically identify and
report all clocks (including gated and
derived clocks), all clock domains, all
signals crossing clock domains, and all
synchronizers (including user-defined
synchronizers). 0-In CDC also reports
all missing (i.e., ad-hoc) synchronizers.
CDC Protocols
While proper synchronization ensures
that metastability does not leak into
general logic, it does not by itself ensure
correct CDC functionality. Every signal
that crosses clock domains must adhere
to an appropriate CDC protocol.
Otherwise, transferred data will be
corrupted in the presence of metasta-
bility in the hardware. For example: A
single-bit control signal transmitted out
of a fast clock domain must stay stable
long enough to be sampled by a slower
receiving clock domain (i.e., the control
signal must be stable longer than one
receiving clock period).
0-In CDC automatically generates
protocol monitors for popular CDC design
styles, including: single-bit control signals
crossing domains via 2DFF synchronizers,
multi-bit data signals crossing domains
using 2DFF synchronizers, mux-synchro-
nized data/control signals, handshake
synchronizers, and FIFO synchronizers.
The automatically generated CDC
protocol monitors run in simulation using
the 0-In Assertion Synthesis system.
In simulation, these monitors detect all
violations that might lead to corruption
of transferred data. Additionally, these
monitors gather coverage information
that helps assess how thoroughly the
design has been tested for correct CDC
functionality.
CDC Reconvergence
Metastability causes variable and
unpredictable delays in the transitions
of received CDC signals. These variable
delays might cause the logic that
recombines the CDC signals — either
combinationally or after sequential
delays — to fail. As a result, when the
design is implemented in silicon it
might experience functional problems.
0-In CDC embodies the industry’s
most advanced technology for analysis
of CDC reconvergence. It reports all
CDC reconvergence up to a user-speci-
fied sequential depth and filters out false
reconvergence. Information in the recon-
vergence report is grouped and organ-
ized to help the user easily check suspect
reconvergence logic. 0-In CDC also
highlights CDC reconvergence that
matches known bug signatures.
Formal Verification
Using the formal verification capa-
bility included in 0-In CDC, designers
can exhaustively verify that the function
of the design is tolerant of metastability
effects in CDC signals.
First, assertions are placed in the
design to check for the failures that could
be caused by metastability (for example,
violations of mutual exclusivity, viola-
tions of Gray coding, and data integrity
problems). Then, 0-In CDC exhaustively
analyzes all possible metastability
scenarios on all CDC signals, including
CDC signals without explicit synchro-
nizers. Any metastability scenario that
could cause the design to violate an asser-
tion is reported as a simulation trace.
Advanced Debugging Options
0-In CDC provides several debugging
options, including concise textual reports
and color-coded graphical debug using the
unified 0-In View reporting environment,
with links to popular debugging tools.
0-In CDC provides the industry’s most
comprehensive clock- domain crossing
verification environment.

Visit our web site at www.mentor.com/products/fv/abv/0-in for more information.

Copyright © 2004 Mentor Graphics Corporation.
0-In and Mentor Graphics are registered trademarks of Mentor Graphics Corporation. All other trademarks mentioned in this document are trademarks of their respective owners.

Corporate Headquarters Silicon Valley Europe Pacific Rim Japan

Mentor Graphics Corporation
8005 S.W. Boeckman Road
Wilsonville, Oregon 97070 USA
Phone: 503-685-7000
North American Support Center
Phone: 800-547-4303
Fax: 800-684-1795
Mentor Graphics Corporation
1001 Ridder Park Drive
San Jose, California 95131 USA
Phone: 408-436-1500
Fax: 408-436-1501
Mentor Graphics Mentor Graphics Taiwan Mentor Graphics Japan Co., Ltd.
Deutschland GmbH Room 1603, 16F, Gotenyama Hills
Arnulfstrasse 201 International Trade Building 7-35, Kita-Shinagawa 4-chome
80634 Munich No. 333, Section 1, Keelung Road Shinagawa-Ku, Tokyo 140
Germany Taipei, Taiwan, ROC Japan Printed on Recycled Paper
Phone: +49.89.57096.0 Phone: 886-2-27576020 Phone: 81-3-5488-3030
Fax: +49.89.57096.400 Fax: 886-2-27576027 Fax: 81-3-5488-3031 12-04 C&A 1023300-w