MAX9867

19-4573; Rev 2; 6/10
Ultra-Low Power Stereo Audio Codec

General Description Features
MAX9867
The MAX9867 is an ultra-low power stereo audio codec o 1.8V Single-Supply Operation
designed for portable consumer devices such as o 6.7mW Playback Power Consumption
mobile phones and portable gaming consoles.
o 90dB Stereo DAC, 8kHz ≤ fS ≤ 48kHz
The device features stereo differential microphone inputs
that can be connected to either analog or digital micro- o 85dB Stereo ADC, 8kHz ≤ fS ≤ 48kHz
phones. The single-ended line inputs, with configurable o Battery-Measurement Auxiliary ADC
preamplifier, can be sent to the ADC for record or routed o Support for Any Master Clock Between 10MHz to
directly to the headphone amplifier for playback. An aux- 60MHz
iliary ADC path can be used to track any DC voltage.
o Stereo Digital Microphone Input Support
The stereo headphone amplifiers support differential,
single-ended, and capacitorless output configurations. o Stereo Analog Differential Microphone Inputs
Using the capacitorless output configuration, the o Stereo Headphone Amplifiers: Differential,
device can output 10mW into 32Ω headphones. Single-Ended, or Capacitorless
Comprehensive click-and-pop circuitry suppresses o Stereo Line Inputs
audible clicks and pops during volume changes and
startup or shutdown. o Voiceband Filter with a Stopband Attenuation
Greater than 70dB
Utilizing Maxim’s proprietary digital circuitry, the device
can accept any available 10MHz to 60MHz system o 1.65V to 3.6V Digital Interface Supply Voltage
clock. This architecture eliminates the need for an o I2S/TDM-Compatible Digital Audio Bus
external PLL and multiple crystal oscillators. The stereo o 30-Bump, 2.2mm x 2.7mm 0.4mm-Pitch WLP
ADC and DAC paths provide user-configurable voice-
band or audioband digital filters. Voiceband filters pro- Applications
vide extra attenuation at the GSM packet frequency Cell Phones
and greater than 70dB stopband attenuation at fS/2. Portable Gaming Devices
The MAX9867 operates from a single 1.8V supply, and Portable Navigation Devices
supports a 1.65V to 3.6V logic level. An I2C 2-wire seri- Portable Multimedia Players
al interface provides control for volume levels, signal Wireless Headsets
mixing, and general operating modes.
The MAX9867 is available in a tiny 2.2mm x 2.7mm,
Ordering Information
0.4mm-ball-pitch, WLP package. A 32-pin 5mm x 5mm PART TEMP RANGE PIN-PACKAGE
TQFN package is also available. MAX9867EWV+ -40°C to +85°C 30 WLP
MAX9867ETJ+ -40°C to +85°C 32 TQFN-EP*
+Denotes lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
Simplified Block Diagram
I2S/PCM I2C
LEFT MIC AMP CONTROL

DIGITAL AUDIO INTERFACE
INTERFACE
MAX9867
DIGITAL MICROPHONE
MIX ADC DAC
INTERFACE HEADPHONE
AUDIO DIGITAL
AMP
FILTERS
ADC DAC
RIGHT MIC AMP MIX
LEFT PREAMP
LINEIN 1
RIGHT PREAMP HEADPHONE
LINEIN 2 AMP
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
ABSOLUTE MAXIMUM RATINGS
MAX9867
(Voltages with respect to AGND.) Continuous Power Dissipation (TA = +70°C)

DVDD, AVDD, and PVDD .........................................-0.3V to +2V 30-Bump WLP (derate 12.5mW/°C above +70°C) ....1000mW
DVDDIO.................................................................-0.3V to +3.6V 32-Pin TQFN-EP (derate 34.5mW/°C above +70°C) .2759mW
DGND and PGND..................................................-0.1V to +0.1V Junction-to-Ambient Thermal Resistance (θJA) (Note 1)
PREG, REF, REG, MICBIAS ....................-0.3V to (AVDD + 0.3V) 30-Bump WLP .............................................................80°C/W
MCLK, LRCLK, BCLK 32-Pin TQFN-EP ..........................................................29°C/W
SDOUT, SDIN .................................-0.3V to (DVDDIO + 0.3V) Operating Temp Range .......................................-40°C to +85°C
SDA, SCL, IRQ ......................................................-0.3V to +3.6V Storage Temp Range ........................................-65°C to +150°C
LOUTP, LOUTN, ROUTP, Lead Temperature (TQFN only, 10s) ...............................+300°C
ROUTN .................................(PGND - 0.3V) to (PVDD + 0.3V) Soldering Temperature (reflow) .......................................+260°C
LINL, LINR, JACKSNS/AUX, MICLP/DIGMICDATA,
MICLN/DIGMICCLK, MICRP, MICRN..-0.3V to (AVDD + 0.3V)
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VAVDD = VPVDD = VDVDD = VDVDDIO = +1.8V, RL = ∞, headphone load (RL) connected between _OUTP and _OUTN in differential
mode, CREF = 2.2µF, CMICBIAS = CPREG = CREG = 1µF, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB, AVVOL =
0dB, MCLK = 13MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

PVDD, DVDD, AVDD 1.65 1.8 1.95
Supply Voltage Range V
DVDDIO 1.65 1.8 3.6
Analog (AVDD +
Full-duplex 8kHz 4.65 7
PVDD)
mono (voice mode)
(Note 3) Digital (DVDD +
0.96 1.5
DVDDIO)
Analog (AVDD +
DAC playback 48kHz 3.28 5
PVDD)
stereo (audio mode)
1.40 2
DVDDIO)
Total Supply Current IVDD mA
Analog (AVDD +
Full-duplex 48kHz 8.0 12
PVDD)
stereo (audio mode)
2.0 3
DVDDIO)
Analog (AVDD +
3.8 6
PVDD)
Stereo line-in only
Digital (DVDD +
0.004 0.05
DVDDIO)
Analog (AVDD +
1 5
PVDD)
Shutdown Supply Current TA = +25°C µA
Digital (DVDD +
1 5
DVDDIO)
2 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
MAX9867

Shutdown to Full Operation Excludes PLL lock time 10 ms
Soft-Start/-Stop Time 10 ms
DAC (Note 4)
Master or slave
fS = 48kHz, AVVOL = 90
Dynamic Range (Note 5) DR mode dB
0dB, TA = +25°C
Slave mode 84
Differential mode 1
Full-Scale Output VOLL/VOLR = 0x09 Capacitorless and VRMS
0.56
single-ended modes
DC accuracy, measured with respect to
Gain Error 1 5 %
full-scale output
f = 1kHz, 0dBFS, HP fS = 8kHz 1.2
Voice Path Phase Delay PDLY filter disabled, digital ms
input to analog output fS = 16kHz 0.59
MCLK = 12.288MHz, fS = 48kHz, 0dBFS,

Total Harmonic Distortion THD -80 dB
measured at headphone outputs
DAC Attenuation Range AVDAC DACA = 0xF to 0x0 -15 0 dB
DAC Gain Adjust AVGAIN DACG = 00 to 11 0 +18 dB
VAVDD = VPVDD = 1.65V to 1.95V 60 78
f = 217Hz, VRIPPLE = 100mVP-P,
78
AVVOL = 0dB
Power-Supply Rejection Ratio PSRR f = 1kHz, VRIPPLE = 100mVP-P, dB
75
AVVOL = 0dB
f = 10kHz, VRIPPLE = 100mVP-P,
62
AVVOL = 0dB
DAC VOICE MODE DIGITAL IIR LOWPASS FILTER
With respect to fS within ripple; fS = 8kHz to 0.448 x
48kHz fS
Passband Cutoff fPLP Hz
0.451 x
-3dB cutoff
fS
Passband Ripple f < fPLP ±0.1 dB
0.476 x
Stopband Cutoff fSLP With respect to fS; fS = 8kHz to 48kHz Hz
fS
Stopband Attenuation f > fSLP, f = 20Hz to 20kHz 75 dB
_______________________________________________________________________________________ 3
MAX9867

DAC VOICE MODE DIGITAL 5th ORDER IIR HIGHPASS FILTER
DVFLT = 0x1
0.0161
(elliptical tuned for 16kHz GSM + 217Hz
x fS
notch)
DVFLT = 0x2 0.0312

(500Hz Butterworth tuned for 16kHz) x fS
5th Order Passband Cutoff
(-3dB from Peak, I2C Register DVFLT = 0x3
fDHPPB 0.0321 Hz
Programmable) (elliptical tuned for 8kHz GSM + 217Hz
x fS
notch)
DVFLT = 0x4 0.0625

DVFLT = 0x5 0.0042
(fS/240 Butterworth) x fS
DVFLT = 0x1
0.0139
x fS
notch)
DVFLT = 0x2 0.0156

5th Order Stopband Cutoff
(-30dB from Peak, I2C Register DVFLT = 0x3
fDHPSB 0.0279 Hz
x fS
notch)
DVFLT = 0x4 0.0312

DVFLT = 0x5 0.0021
DC Attenuation DCATTEN DVFLT ≠ 000 90 dB
DAC STEREO AUDIO MODE DIGITAL FIR LOWPASS FILTER
With respect to fS within ripple; 0.43 x
fS = 8kHz to 48kHz fS
0.47 x
Passband Cutoff fPLP -3dB cutoff Hz
fS
0.50 x
-6.02dB cutoff
fS
0.58 x
fS
Stopband Attenuation 60 dB
4 _______________________________________________________________________________________
MAX9867

DAC STEREO AUDIO MODE DIGITAL DC BLOCKING HIGHPASS FILTER
Passband Cutoff 0.000625
fDHPPB DVFLT = 0x1 Hz
(-3dB from Peak) x fS
DC Attenuation DCATTEN DVFLT = 0x1 90 dB
ADC (Note 6)
fS = 8kHz, MODE = 0 (IIR voice) 75 84
Dynamic Range (Note 5) DR dB
fS = 8kHz to 48kHz, MODE = 1 (FIR audio) 85
Differential MIC input or stereo-line inputs,
Full-Scale Input 1 VP-P
AVPRE = 0dB, AVPGAM = 0dB
DC accuracy, measured with respect to
Gain Error (Note 7) 1 5 %
80% of full-scale output
f = 1kHz, 0dBFS, HP fS = 8kHz 1.2

filter disabled,
Voice Path Phase Delay PDLY ms
analog input to
digital output fS = 16kHz 0.61
Total Harmonic Distortion THD f = 1kHz, fS = 8kHz, TA = +25°C, 0dBFS -81 -70 dB
ADC Level Adjust Range AVADC AVL/AVR = 0xF to 0x0 -12 +3 dB
VAVDD = 1.65V to 1.95V, input referred 60 85
f = 217Hz, VRIPPLE = 100mV, AVADC = 0dB,
85
input referred
Power-Supply Rejection Ratio PSRR f = 1kHz, VRIPPLE = 100mV, AVADC = 0dB, dB
80
input referred
f = 10kHz, VRIPPLE = 100mV, AVADC = 0dB,
80
input referred
ADC VOICE MODE DIGITAL IIR LOWPASS FILTER
Passband Cutoff fPLP Hz
0.449 x
-3dB cutoff
fS
0.469 x
fS
_______________________________________________________________________________________ 5
MAX9867

ADC VOICE MODE DIGITAL 5th ORDER IIR HIGHPASS FILTER
AVFLT = 0x1
0.0161
x fS
notch)
AVFLT = 0x2 0.0312

5th Order Passband Cutoff
(-3dB from Peak, I2C Register AVFLT = 0x3
fAHPPB 0.0321 Hz
x fS
notch)
AVFLT = 0x4 0.0625

AVFLT = 0x5 0.0042
AVFLT = 0x1
0.0139
x fS
notch)
AVFLT = 0x2 0.0156

Stopband Cutoff (-30dB from AVFLT = 0x3
fAHPSB 0.0279 Hz
Peak) (elliptical tuned for 8kHz GSM + 217Hz
x fS
notch)
AVFLT = 0x4 0.0312

AVFLT = 0x5 0.0021
DC Attenuation DCATTEN AVFLT ≠ 000 90 dB
ADC STEREO AUDIO MODE DIGITAL FIR LOWPASS FILTER
Passband Cutoff fPLP 0.48 x Hz
-3dB cutoff
fS
-6.02dB cutoff 0.5 x fS
0.58 x
fS
6 _______________________________________________________________________________________
MAX9867

ADC STEREO AUDIO MODE DIGITAL DC BLOCKING HIGHPASS FILTER
Passband Cutoff 0.000625
fAHPPB AVFLT = 0x1 Hz
(-3dB from Peak) x fS
DC Attenuation DCATTEN AVFLT = 0x1 90 dB
OUTPUT VOLUME CONTROL
VOLL/VOLR = 0x00 14.55 14.9 15.15
VOLL/VOLR = 0x01 14.1 14.4 14.6
VOLL/VOLR = 0x02 13.6 13.9 14.1
Line Input to Output Volume
AVVOL VOLL/VOLR = 0x04 12.6 12.9 13.1 dB
Control
VOLL/VOLR = 0x08 9.35 9.9 10.35
VOLL/VOLR = 0x10 0.35 0.9 1.35
VOLL/VOLR = 0x20 -50.15 -49.2 -48.15
VOLL/VOLR = 0x00 to 0x06 (+6dB to +3dB) 0.5
VOLL/VOLR = 0x06 to 0x0F (+3dB to -6dB) 1
Output Volume Control Step Size dB
VOLL/VOLR = 0x0F to 0x17 (-6dB to -22dB) 2
VOLL/VOLR = 0x17 to 0x3F (-22dB to mute) 4
Output Volume Control Mute
f = 1kHz 100 dB
Attenuation
HEADPHONE AMPLIFIER (Note 8)
Output Power per Channel f = 1kHz, THD < RL = 16Ω 30 52
POUT mW
(Differential Mode) 1%, TA = +25°C RL = 32Ω 32
Output Power per Channel f = 1kHz, THD < RL = 16Ω 19
POUT mW
(Capacitorless Mode) 1%, TA = +25°C RL = 32Ω 8 10
RL = 16Ω, POUT = 25mW, f = 1kHz -76
MCLK = 13MHz,
Total Harmonic Distortion + Noise -77 -70
THD+N RL = 32Ω, POUT = fS = 8kHz dB
(Differential Mode)
25mW, f = 1kHz MCLK = 12.288MHz,
-80
fS = 48kHz
RL = 16Ω, POUT = 6.25mW, f = 1kHz -72
MCLK = 13MHz,
(Capacitorless Mode)
6.25mW, f = 1kHz MCLK = 12.288MHz,
-74
fS = 48kHz
RL = 16Ω, POUT = 6.25mW, f = 1kHz -74
MCLK = 13MHz,
(SE Mode)
6.25mW, f = 1kHz MCLK = 12.288MHz,
-76
fS = 48kHz
Dynamic Range DR AVVOL = +6dB (Notes 5, 7) 76 90 dB
_______________________________________________________________________________________ 7
MAX9867

VAVDD = VPVDD = 1.65V to 1.95V 60 78
f = 217Hz, VRIPPLE = 100mVP-P,
78
AVVOL = 0dB
Power-Supply Rejection Ratio
PSRR f = 1kHz, VRIPPLE = 100mVP-P, dB
(Note 7) 75
AVVOL = 0dB
f = 10kHz, VRIPPLE = 100mVP-P,
62
AVVOL = 0dB
(LOUTP–LOUTN,
AVVOL = -84dB
ROUTP–ROUTN), ±0.2
differential mode
TA = +25°C
Output Offset Voltage VOS mV
AVVOL = -84dB (LOUTP–LOUTN,
capacitorless ROUTP–LOUTN), ±0.8
mode TA = +25°C
Differential mode, POUT = 5mW, f = 1kHz 87
Capacitorless TQFN 55
Crosstalk XTALK mode, dB
POUT = 5mW,
WLP 60
f = 1kHz
No sustained RL = 32Ω 500
Capacitive Drive pF
oscillations RL = ∞ 100
Peak voltage, Into shutdown -80
Click-and-Pop Level
A-weighted, 32
(Differential, Capacitorless dBV
samples per
Modes) Out of shutdown -69
second
Peak voltage, Into shutdown -75
Click-and-Pop Level A-weighted, 32
dBV
(SE Mode) samples per
Out of shutdown -75
second
MICROPHONE AMPLIFIER
PALEN/PAREN = 01 -0.5 0 +0.5
Preamplifier Gain AVPRE PALEN/PAREN = 10 19.5 20 20.5 dB
PALEN/PAREN = 11 29.5 30 30.5
PGAML/PGAMR = 0x1F -0.6 -0.1 +0.4
MIC PGA Gain AVPGAM dB
PGAML/PGAMR = 0x00 19.3 19.75 20.3
Common-Mode Rejection Ratio CMRR VIN = 100mVP-P, f = 217Hz 50 dB
MIC Input Resistance RIN_MIC All gain settings 30 50 kΩ
8 _______________________________________________________________________________________
MAX9867

AVPRE = 0dB,
-80
VIN = 1VP-P, f = 1kHz
Total Harmonic Distortion + Noise THD+N AVPRE = +30dB, dB
VIN = 32mVP-P, f = 1kHz, -67
(1VP-P at ADC input)
VAVDD = 1.65V to 1.95V, input referred 60 85
f = 217Hz, VRIPPLE = 100mV,
85
AVADC = 0dB, input referred
Power-Supply Rejection Ratio PSRR f = 1kHz, VRIPPLE = 100mV, dB
80
f = 10kHz, VRIPPLE = 100mV,
80
MICROPHONE BIAS
Output Voltage VMICBIAS VAVDD = 1.8V, ILOAD = 1mA 1.5 1.525 1.55 V
Load Regulation ILOAD = 1mA to 2mA 0.2 10 V/A
Line Regulation VAVDD = 1.65V to 1.95V 10 µV/V
f = 217Hz, VRIPPLE = 100mVP-P 85
Power-Supply Rejection Ratio PSRR dB
f = 10kHz, VRIPPLE = 100mVP-P 81
Noise Voltage A-weighted 9.1 µVRMS
LINE INPUT
Full-Scale Input VIN AVLINE = 0dB 1.0 VP-P
Line Input Level Adjust Range AVLINE LIGL/LIGR = 0xF to 0x0 -6.5 +24.5 dB
Line Input Mute Attenuation f = 1kHz 100 dB
Input Resistance RIN_LINE AVLINE = +24dB 20 kΩ
Total Harmonic Distortion + Noise THD+N VIN = 0.1VP-P, f = 1kHz, differential output -83 dB
AUXIN INPUT
Input DC Voltage Range AUXEN = 1 0 0.738 V
AUXIN Input Resistance RIN AUXEN = 1, 0V ≤ AUXIN ≤ 0.738V 10 40 MΩ
JACK SENSE OPERATION
0.92 x 0.95 x 0.98 x
JDETEN = 1, SHDN = 1, JACKSNS
MICBIAS MICBIAS MICBIAS
Threshold VTH V
JDETEN = 1, SHDN = 0, JACKSNS, AVDD - AVDD - AVDD -
LOUTP 0.8 0.4 0.15
JDETEN = 1, SHDN = 1,
4
JACKSNS = GND
Pullup Current IPU µA
JDETEN = 1, SHDN = 0,
4 20
JACKSNS = LOUTP = GND
Pullup Voltage JDETEN = 1, JACKSNS, LOUTP AVDD V
_______________________________________________________________________________________ 9
MAX9867

DIGITAL SIDETONE
Differential output mode,
Sidetone Gain Adjust Range AVSTGA -60 0 dB
DVST = 0x1F to 0x01
MIC input to headphone output, f = 1kHz,
Voice Path Phase Delay PDLY 2.2 ms
HP filter disabled, fS = 8kHz
INPUT CLOCK CHARACTERISTICS
MCLK Input Frequency fMCLK For any LRCLK sample rate 10 60 MHz
Prescaler = /1 mode 40 60
MCLK Input Duty Cycle %
/2 or /4 modes 30 70
Maximum allowable RMS for performance
Maximum MCLK Input Jitter 100 psRMS
limits
LRCLK Sample Rate Range 8 48 kHz
Any allowable LRCLK Rapid lock mode 2 7
LRCLK PLL Lock Time and PCLK rate, slave Nonrapid lock ms
12 25
mode mode
Allowable LRCLK period change from

LRCLK Acceptable Jitter for
nominal for slave PLL mode at any ±100 ns
Maintaining PLL Lock
allowable LRCLK and PCLK rates
FREQ = 0x8 through 0xF 0 0 %
LRCLK Average Frequency Error
PCLK = 192xfS, 256xfS, 384xfS, 512xfS,
(Master and Slave Modes) 0 0
768xfS, and 1024xfS
(Note 9)
All other modes -0.025 +0.025
DIGITAL INPUT (MCLK)
Input High Voltage VIH 1.2 V
Input Low Voltage VIL 0.6 V
Input Leakage Current IIH, IIL TA = +25°C ±1 µA
Input Capacitance 10 pF
DIGITAL INPUTS (SDIN, BCLK, LRCLK)
0.7 x
Input High Voltage VIH V
DVDDIO
0.3 x
Input Low Voltage VIL V
DVDDIO
Input Hysteresis 200 mV
10 ______________________________________________________________________________________
MAX9867

DIGITAL INPUTS (SDA, SCL)
0.7 x
DVDD
0.3 x
DVDD
DIGITAL INPUT (DIGMICDATA)
0.65 x
DVDD
0.35 x
DVDD
CMOS DIGITAL OUTPUTS (BCLK, LRCLK, SDOUT)
Output Low Voltage VOL IOL = 3mA 0.4 V
DVDDIO
Output High Voltage VOH IOH = 3mA V
- 0.4
CMOS DIGITAL OUTPUT (DIGMICCLK)
Output Low Voltage VOL IOL = 1mA 0.4 V
DVDD -
Output High Voltage VOH IOH = 1mA V
0.4
OPEN-DRAIN DIGITAL OUTPUTS (SDA, IRQ)
Output High Current IOH VOUT = VDVDD, TA = +25°C 1 µA
0.2 x
Output Low Voltage VOL IOL = 3mA V
DVDD
DIGITAL MICROPHONE TIMING CHARACTERISTICS (VDVDD = 1.65V)
MICCLK = 00 PCLK/8
DIGMICCLK Divide Ratio fMICCLK MHz
MICCLK = 01 PCLK/6
DIGMICDATA to DIGMICCLK
tSU, MIC Either clock edge 20 ns
Setup Time
DIGMICDATA to DIGMICCLK
tHD, MIC Either clock edge 0 ns
Hold Time
DIGITAL AUDIO INTERFACE TIMING CHARACTERISTICS (VDVDD = 1.65V)
tBCLKS Slave operation 75 ns
Minimum BCLK Cycle Time
tBCLKM Master operation 325 ns
______________________________________________________________________________________ 11
MAX9867

Minimum BCLK High Time tBCLKH Slave operation 30 ns
Minimum BCLK Low Time tBCLKL Slave operation 30 ns
BCLK or LRCLK Rise and Fall tR, tF Master operation, CL = 15pF 7 ns
SDIN or LRCLK to BCLK Setup
tSU 20 ns
Time
SDIN or LRCLK to BCLK Hold
tHD 0 ns
Time
SDOUT Delay Time from BCLK
tDLY CL = 30pF 0 40 ns
Rising Edge
I2C TIMING CHARACTERISTICS (VDVDD = 1.65V)
Serial-Clock Frequency fSCL 0 400 kHz
Bus Free Time Between STOP
tBUF 1.3 µs
and START Conditions
Hold Time (REPEATED) START
tHD, STA 0.6 µs
Condition
SCL Pulse-Width Low tLOW 1.3 µs
SCL Pulse-Width High tHIGH 0.6 µs
Setup Time for a REPEATED
tSU, STA 0.6 µs
START Condition
Data Hold Time tHD, DAT RPU, SDA = 475Ω 0 900 ns
Data Setup Time tSU, DAT 100 ns
SDA and SCL Receiving Rise 20 +
tR (Note 10) 300 ns
Time 0.1CB
SDA and SCL Receiving Fall 20 +
tF (Note 10) 300 ns
Time 0.1CB
RPU, SDA = 475Ω 20 +
SDA Transmitting Fall Time tF 250 ns
(Note 10) 0.1CB
Setup Time for STOP Condition tSU, STO 0.6 µs
Bus Capacitance CB 400 pF
Pulse Width of Suppressed Spike tSP 0 50 ns
Note 2: The MAX9867 is 100% production tested at TA = +25°C. Specifications over temperature limits are guaranteed by design.
Note 3: Clocking all zeros into the DAC, master mode, and differential headphone mode.
Note 4: DAC performance measured at the headphone outputs.
Note 5: Dynamic range measured using the EIAJ method. -60dBFS 1kHz output signal, A-weighted, and normalized to 0dBFS.
f = 20Hz to 20kHz.
Note 6: Performance measured using microphone inputs, unless otherwise stated.
Note 7: Performance measured using line inputs.
Note 8: Performance measured using DAC, unless otherwise stated. LRCLK = 8kHz, unless otherwise stated.
Note 9: In master-mode operation, the accuracy of the MCLK input proportionally determines the accuracy of the sample clock rate.
Note 10: CB is in pF.
12 ______________________________________________________________________________________
Typical Operating Characteristics
MAX9867
(VAVDD = VDVDD = VPVDD = +1.8V, CREF = 2.2µF, CMICBIAS = CPREG = CREG = 1µF, AVMICPGA = 0dB, MCLK = 13MHz, LRCLK =
8kHz, BW = 20Hz to fS/2, TA = +25°C, unless otherwise noted.)
TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE
vs. POWER OUT (DAC TO HEADPHONE) vs. POWER OUT (DAC TO HEADPHONE) vs. POWER OUT (DAC TO HEADPHONE)
0 0 0
MAX9867 toc01
MAX9867 toc02
MAX9867 toc03
MCLK = 13MHz MCLK = 13MHz MCLK = 12.288MHz
-10 LRCLK = 8kHz -10 LRCLK = 8kHz -10 LRCLK = 48kHz
RLOAD = 32Ω RLOAD = 16Ω RLOAD = 32Ω
-20 DIFFERENTIAL MODE -20 DIFFERENTIAL MODE -20 DIFFERENTIAL MODE
-30 -30 -30
THD+N (dB)
THD+N (dB)
THD+N (dB)
-40 -40 -40
-50 -50 -50
3kHz 3kHz
-60 1kHz -60 1kHz -60 6kHz 1kHz
-70 -70 -70

-80 -80 -80
20Hz 20Hz 20Hz
-90 -90 -90
0 5 10 15 20 25 30 35 0 10 20 30 40 50 60 0 5 10 15 20 25 30 35
POWER OUT (mW) POWER OUT (mW) POWER OUT (mW)
vs. POWER OUT (DAC TO HEADPHONE) vs. FREQUENCY (DAC TO HEADPHONE) vs. FREQUENCY (DAC TO HEADPHONE)
0 0 0
MAX9867 toc04
MAX9867 toc05
MAX9867 toc06
MCLK = 12.288MHz MCLK = 13MHz MCLK = 13MHz
-20 DIFFERENTIAL MODE -20 DIFFERENTIAL MODE -20 DIFFERENTIAL MODE
-30 -30 -30
THD+N (dB)
THD+N (%)
THD+N (%)
-40 -40 -40

-50 -50 -50
-60 6kHz -60 -60 5mW
1kHz 5mW
-70 -70 -70
-80 -80 -80
20mW 20mW
20Hz
-90 -90 -90
0 10 20 30 40 50 60 10 100 1000 10,000 10 100 1000 10,000
POWER OUT (mW) FREQUENCY (Hz) FREQUENCY (Hz)
vs. FREQUENCY (DAC TO HEADPHONE) vs. FREQUENCY (DAC TO HEADPHONE) vs. POWER OUT (DAC TO HEADPHONE)
0 0 0
MAX9867 toc07
MAX9867 toc08
MAX9867 toc09
MCLK = 12.288MHz MCLK = 12.288MHz MCLK = 13MHz

-20 DIFFERENTIAL MODE -20 DIFFERENTIAL MODE -20 CAPACITORLESS MODE
-30 -30 -30
THD+N (dB)
THD+N (%)
THD+N (%)
-40 -40 -40

-50 -50 -50 3kHz
1kHz
-60 -60 5mW -60
5mW
-70 -70 -70
-80 -80 -80 20Hz
20mW 20mW
-90 -90 -90
10 100 1000 10,000 100,000 10 100 1000 10,000 100,000 0 2 4 6 8 10
FREQUENCY (Hz) FREQUENCY (Hz) POWER OUT (mW)
______________________________________________________________________________________ 13
Typical Operating Characteristics (continued)
MAX9867
vs. POWER OUT (DAC TO HEADPHONE) vs. FREQUENCY (DAC TO HEADPHONE) vs. FREQUENCY (DAC TO HEADPHONE)
0 0 0
MAX9867 toc10
MAX9867 toc11
MAX9867 toc12
MCLK = 12.288MHz MCLK = 13MHz MCLK = 12.288MHz
-20 CAPACITORLESS MODE -20 CAPACITORLESS MODE -20 CAPACITORLESS MODE
-30 -30 -30
THD+N (dB)
THD+N (%)
THD+N (%)
-40 -40 -40
-50 6kHz -50 -50
1mW
-60 1kHz -60 1mW -60
-70 -70 -70

-80 20Hz -80 5mW -80
5mW
-90 -90 -90
0 2 4 6 8 10 12 10 100 1000 10,000 10 100 1000 10,000 100,000
POWER OUT (mW) FREQUENCY (Hz) FREQUENCY (Hz)
vs. POWER OUT (DAC TO HEADPHONE) vs. POWER OUT (DAC TO HEADPHONE) vs. FREQUENCY (DAC TO HEADPHONE)
0 0 0
MAX9867 toc13
MAX9867 toc14
MAX9867 toc15
MCLK = 13MHz MCLK = 12.288MHz MCLK = 13MHz
RLOAD = 32Ω, COUT = 220µF RLOAD = 32Ω, COUT = 220µF RLOAD = 32Ω, COUT = 220µF
-20 SINGLE-ENDED MODE -20 SINGLE-ENDED MODE -20 SINGLE-ENDED MODE
-30 -30 -30 POUT SPECIFIED AT 1kHz
THD+N (dB)
THD+N (dB)
THD+N (%)
-40 -40 -40

-50 20Hz -50 20Hz -50
3kHz
6kHz
-60 -60 -60 1mW
-70 -70 -70

-80 1kHz -80 1kHz -80 5mW
-90 -90 -90
0 2 4 6 8 10 0 2 4 6 8 10 12 10 100 1000 10,000
POWER OUT (mW) POWER OUT (mW) FREQUENCY (Hz)
vs. FREQUENCY (DAC TO HEADPHONE) vs. POWER OUT (LINE IN TO HEADPHONE) vs. POWER OUT (LINE IN TO HEADPHONE)
0 0 0
MAX9867 toc16
MAX9867 toc17
MAX9867 toc18
MCLK = 13MHz LINE IN PREAMP = +18dB LINE IN PREAMP = 0dB

-10 LRCLK = 8kHz -10 RLOAD = 32Ω -10 RLOAD = 32Ω
RLOAD = 32Ω, COUT = 220µF DIFFERENTIAL MODE DIFFERENTIAL MODE
-20 -20
SINGLE-ENDED MODE -20
-30 POUT SPECIFIED AT 1kHz -30
-30
THD+N (dB)
THD+N (dB)
THD+N (%)
-40 -40
-40
-50 -50
1mW -50
-60 -60
20Hz 6kHz
-60
-70 1kHz -70 20Hz
-80 -70 -80
5mW 6kHz 1kHz
-90 -80 -90
10 100 1000 10,000 100,000 0 5 10 15 20 25 30 35 40 45 50 0 5 10 15 20 25 30 35 40
FREQUENCY (Hz) POWER OUT (mW) POWER OUT (mW)
14 ______________________________________________________________________________________
MAX9867
TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE

vs. FREQUENCY (LINE IN TO HEADPHONE) vs. FREQUENCY (LINE IN TO HEADPHONE) POWER OUT vs. HEADPHONE LOAD
0 0 60
MAX9867 toc21
MAX9867 toc19
MAX9867 toc20
LINE IN PREAMP = +18dB LINE IN PREAMP = 0dB MCLK = 12.288MHz
-10 RLOAD = 32Ω -10 RLOAD = 32Ω LRCLK = 48kHz
DIFFERENTIAL MODE DIFFERENTIAL MODE 50 THD+N = < 0.1%
-20 -20 DIFFERENTIAL MODE
POWER OUT (mW)

-30 -30 40
THD+N (dB)
THD+N (dB)
-40 -40
30
-50 5mW -50
-60 -60 20
5mW
-70 -70
10
-80 -80
20mW
20mW
-90 -90 0
10 100 1000 10,000 100,000 10 100 1000 10,000 100,000 1 10 100 1000
FREQUENCY (Hz) FREQUENCY (Hz) HEADPHONE LOAD (Ω)
TOTAL HARMONIC DISTORTION + NOISE

POWER OUT vs. HEADPHONE LOAD POWER OUT vs. HEADPHONE LOAD vs. FREQUENCY (MICROPHONE TO ADC)
30 25 0
MAX9867 toc24
MAX9867 toc22
MAX9867 toc23
MCLK = 12.288MHz MCLK = 12.288MHz MCLK = 13MHz

LRCLK = 48kHz LRCLK = 48kHz -10 LRCLK = 8kHz
25 THD+N = < 0.1% THD+N = < 0.1% MICPRE = 0dB
20 -20
CAPACITORLESS MODE SINGLE-ENDED MODE VIN = 1VP-P
POWER OUT (mW)
POWER OUT (mW)
20 -30
THD+N (%)
15
-40
15
-50
10
10 -60
-70
5
5
-80
0 0 -90
1 10 100 1000 1 10 100 1000 10 100 1000 10,000
HEADPHONE LOAD (Ω) HEADPHONE LOAD (Ω) FREQUENCY (Hz)
TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY (MICROPHONE TO ADC) vs. FREQUENCY (MICROPHONE TO ADC) vs. FREQUENCY (DAC TO HEADPHONE)
0 0 0
MAX9867 toc25
MAX9867 toc26
MAX9867 toc27
MCLK = 13MHz MCLK = 13MHz VRIPPLE = 100mVP-P

-10 LRCLK = 8kHz -10 LRCLK = 8kHz -10 MCLK = 13MHz
MICPRE = 20dB MICPRE = 30dB LRCLK = 8kHz
-20 VIN = 0.11VP-P -20 VIN = 0.032VP-P -20
-30 -30 -30
THD+N (%)
THD+N (%)
PSRR (dB)
-40 -40 -40

-50 -50 -50
-60 -60 -60
-70 -70 -70

-80 -80 -80
-90 -90 -90

10 100 1000 10,000 10 100 1000 10,000 10 100 1000 10,000 100,000
FREQUENCY (Hz) FREQUENCY (Hz) FREQUENCY (Hz)
______________________________________________________________________________________ 15
MAX9867

POWER-SUPPLY REJECTION RATIO POWER-SUPPLY REJECTION RATIO FFT, DAC TO HEADPHONE,

vs. FREQUENCY (MIC TO ADC) vs. FREQUENCY (MICBIAS) 0dBFS, MCLK = 13MHz, LRCLK = 8kHz
0 0 20
MAX9867 toc28
MAX9867 toc29
MAX9867 toc30
VRIPPLE = 100mVP-P VRIPPLE = 100mVP-P FREQ = 0xA
-10 MCLK = 13MHz -10 0
LRCLK = 8kHz
-20 -20
-20
-30 -30
AMPLITUDE (dB)
-40
PSRR (dB)
PSRR (dB)
-40 -40
-60
-50 -50
-80
-60 -60
-100
-70 -70
-80 -80 -120
-90 -90 -140

10 100 1000 10 100 1000 0 2 4 6 8 10 12 14 16 18 20
FREQUENCY (Hz) FREQUENCY (Hz) FREQUENCY (kHz)
FFT, DAC TO HEADPHONE, FFT, DAC TO HEADPHONE, FFT, DAC TO HEADPHONE,

-60dBFS, MCLK = 13MHz, LRCLK = 8kHz 0dBFS, MCLK = 12.288MHz, LRCLK = 48kHz -60dBFS, MCLK = 12.288MHz, LRCLK = 48kHz
20 20 20
MAX9867 toc31
MAX9867 toc32
MAX9867 toc33
FREQ = 0xA NI = 6000 NI = 6000
0 0 0
-20 -20 -20

AMPLITUDE (dB)
AMPLITUDE (dB)
AMPLITUDE (dB)
-40 -40 -40
-60 -60 -60
-80 -80 -80
-100 -100 -100
-120 -120 -120
-140 -140 -140

0 2 4 6 8 10 12 14 16 18 20 0 2 4 6 8 10 12 14 16 18 20 0 2 4 6 8 10 12 14 16 18 20
FREQUENCY (kHz) FREQUENCY (kHz) FREQUENCY (kHz)
FFT, DAC TO HEADPHONE, FFT, DAC TO HEADPHONE, FFT, DAC TO HEADPHONE,

0dBFS, MCLK = 13MHz, LRCLK = 48kHz -60dBFS, MCLK = 13MHz, LRCLK = 48kHz 0dBFS, MCLK = 13MHz, LRCLK = 44.1kHz
20 20 20
MAX9867 toc34
MAX9867 toc35
MAX9867 toc36
PLL MODE PLL MODE PLL MODE

0 0 0
-20 -20 -20

AMPLITUDE (dB)
AMPLITUDE (dB)
AMPLITUDE (dB)
-40 -40 -40
-60 -60 -60
-80 -80 -80
-100 -100 -100
-120 -120 -120
-140 -140 -140

0 2 4 6 8 10 12 14 16 18 20 0 2 4 6 8 10 12 14 16 18 20 0 2 4 6 8 10 12 14 16 18 20
16 ______________________________________________________________________________________
MAX9867
FFT, DAC TO HEADPHONE, -60dBFS, FFT, MICROPHONE TO ADC, FFT, MICROPHONE TO ADC,
MCLK = 13MHz, LRCLK = 44.1kHz 0dBFS, MCLK = 13MHz, LRCLK = 8kHz -60dBFS, MCLK = 13MHz, LRCLK = 8kHz
20 20 20
MAX9867 toc37
MAX9867 toc38
MAX9867 toc39
PLL MODE FREQ = 0xA FREQ = 0xA
0 0 0
-20 -20 -20

AMPLITUDE (dB)
AMPLITUDE (dB)
AMPLITUDE (dB)
-40 -40 -40
-60 -60 -60
-80 -80 -80
-100 -100 -100
-120 -120 -120
-140 -140 -140

0 2 4 6 8 10 12 14 16 18 20 0 500 1000 1500 2000 2500 3000 3500 4000 0 500 1000 1500 2000 2500 3000 3500 4000
FREQUENCY (kHz) FREQUENCY (Hz) FREQUENCY (Hz)
FFT, MICROPHONE TO ADC, FFT, MICROPHONE TO ADC, FFT, MICROPHONE TO ADC,

0dBFS, MCLK = 12.288MHz, LRCLK = 48kHz -60dBFS, MCLK = 12.288MHz, LRCLK = 48kHz 0dBFS, MCLK = 13MHz, LRCLK = 48kHz
20 20 20
MAX9867 toc40
MAX9867 toc41
MAX9867 toc42
NI = 6000 NI = 6000 PLL MODE
0 0 0
-20 -20 -20

AMPLITUDE (dB)
AMPLITUDE (dB)
AMPLITUDE (dB)
-40 -40 -40
-60 -60 -60
-80 -80 -80
-100 -100 -100
-120 -120 -120
-140 -140 -140

0 2 4 6 8 10 12 14 16 18 20 0 2 4 6 8 10 12 14 16 18 20 0 2 4 6 8 10 12 14 16 18 20
FFT, MICROPHONE TO ADC, WIDEBAND FFT, DAC TO HEADPHONE, WIDEBAND FFT, DAC TO HEADPHONE,
-60dBFS, MCLK = 13MHz, LRCLK = 48kHz 0dBFS, MCLK = 13MHz, LRCLK = 8kHz -60dBFS, MCLK = 13MHz, LRCLK = 8kHz
20 0 20
MAX9867 toc43
MAX9867 toc44
MAX9867 toc45
PLL MODE FREQ = 0xA FREQ = 0xA

0 -20 0
-20 -20
-40
AMPLITUDE (dB)
AMPLITUDE (dB)
AMPLITUDE (dB)
-40 -40
-60
-60 -60
-80
-80 -80
-100
-100 -100
-120 -120 -120
-140 -140 -140

0 2 4 6 8 10 12 14 16 18 20 0 20 40 60 80 100 120 0 20 40 60 80 100 120
______________________________________________________________________________________ 17
MAX9867
DAC IIR HIGHPASS FILTER DAC IIR HIGHPASS FILTER DAC IIR/FIR LOWPASS FILTER
FREQUENCY RESPONSE, MODE = 0 FREQUENCY RESPONSE, MODE = 0 FREQUENCY RESPONSE (8kHz)
20 20 20
MAX9867 toc46
MAX9867 toc47
MAX9867 toc48
DVFLT = 0 LRCLK = 8kHz AVFLT = 0 LRCLK = 8kHz
MODE = 0 10 MODE = 1
0 0
0
DVFLT = 3 AVFLT = 3
-10
-20 -20
AMPLITUDE (dB)
AMPLITUDE (dB)
AMPLITUDE (dB)
-20 MODE = 0
-40 -40 -30
-40
-60 -60
-50
DVFLT = 4 AVFLT = 4
-60
-80 -80
-70
-100 -100 -80
20 120 220 320 420 520 20 120 220 320 420 520 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4.0
FREQUENCY (Hz) FREQUENCY (Hz) FREQUENCY (kHz)
ADC IIR/FIR LOWPASS FILTER SHUTDOWN TO DAC FULL OPERATION

FREQUENCY RESPONSE (8kHz) (CAPACITORLESS OR DIFFERENTIAL MODE)
20
MAX9867 toc49
MAX9867 toc50
MODE = 1
SCL (2V/div)
10
-20
AMPLITUDE (dB)
MODE = 0
-40
LOUTP (500mV/div)
-60
-80
-100
3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4.0 TIME (4ms/div)
FREQUENCY (kHz)
SHUTDOWN TO DAC FULL OPERATION SHUTDOWN TO DAC FULL OPERATION

(CLICKLESS SINGLE-ENDED MODE) (FAST TURN-ON SINGLE-ENDED MODE)
MAX9867 toc51
MAX9867 toc52
SCL (2V/div)
SCL (2V/div)
LOUTP (500mV/div)
LOUTP (500mV/div)
TIME (40ms/div) TIME (4ms/div)
18 ______________________________________________________________________________________
MAX9867
FULL OPERATION TO SHUTDOWN (DAC) ADC SOFT-START
MAX9867 toc53
MAX9867 toc54
SCL (2V/div)
SCL (2V/div)
ADC OUT (500mV/div)
LOUTP (500mV/div)
TIME (1ms/div) TIME (4ms/div)
TOTAL HARMONIC DISTORTION + NOISE

vs. MCLK FREQUENCY, 0dBFS DYNAMIC RANGE vs. MCLK FREQUENCY
0 120
MAX9867 toc55
MAX9867 toc56
LRCLK = 48kHz VIN = -60dBFS
-10 PLL MODE LRCLK = 48kHz
-20 110 PLL MODE
A-WEIGHTED
DYNAMIC RANGE (dB)
-30
100
THD+N (dB)
-40
-50 90
-60
-70 80
-80
70
-90
-100 60
10 15 20 25 30 35 40 45 50 55 60 10 100
MCLK FREQUENCY (MHz) MCLK FREQUENCY (MHz)
LINE INPUT RESISTANCE vs. GAIN SETTING AUX CODE vs. INPUT VOLTAGE
270 30,000
MAX9867 toc57
MAX9867 toc58
25,000
220
AUX CODE (SIGNED DECIMAL)
INPUT RESISTANCE (kΩ)
20,000
170
15,000
120 10,000
5000
70
0
20 -5000
-6 -1 4 9 14 19 24 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 1.2
GAIN SETTING (dB) INPUT VOLTAGE (V)
______________________________________________________________________________________ 19
Pin Description
MAX9867
PIN/BUMP
NAME FUNCTION
TQFN-EP WLP
1 A2 DGND Digital Ground
2 B3 SCL I2C Serial-Clock Input. Connect a pullup resistor to a 1.7V to 3.3V supply.
3 A3 SDA I2C Serial-Data Input/Output. Connect a pullup resistor to a 1.7V to 3.3V supply.
Hardware Interrupt Output. IRQ can be programmed to pull low when bits in
status register 0x00 are set. Read status register 0x00 to clear IRQ once set.
4 C3 IRQ
Repeat faults have no effect on IRQ until it is cleared by reading register 0x00.
Connect a 10kΩ pullup resistor to a 1.7V to 3.3V supply.
5 A4 AVDD Analog Power Supply. Bypass to AGND with a 1µF capacitor.
6 B4 REF Converter Reference. Bypass to AGND with a 2.2µF capacitor (1.23V nominal).
Positive Internal Regulated Supply. Bypass to AGND with a 1µF capacitor (1.6V
7 A5 PREG
nominal).
8 B5 REG PREG/2 Voltage Reference. Bypass to AGND with a 1µF capacitor (0.8V nominal).
9 A6 AGND Analog Ground
Low-Noise Microphone Bias. Connect a 2.2kΩ to 470Ω resistor to the positive
10 B6 MICBIAS
output of a microphone (1.525V nominal). Bypass to AGND with a 1µF capacitor.
Left Negative Differential Microphone Input or Digital Microphone Clock Output.
MICLN/ For analog microphones, AC-couple to the negative output of a microphone with a
11 C5
DIGMICCLK 1µF capacitor. For digital microphones, connect to the clock input of the
microphone.
Left Positive Differential Microphone Input or Digital Microphone Data Input. For
MICLP/ analog microphones, AC-couple to the positive output of a microphone with a 1µF
12 C6
DIGMICDATA capacitor. For digital microphones, connect to the data output of the
microphone(s). Up to two digital microphones can be connected.
Right Positive Differential Microphone Input. AC-couple to the positive output of a
13 C4 MICRP
microphone with a 1µF capacitor.
Right Negative Differential Microphone Input. AC-couple to the negative output of
14 D6 MICRN
a microphone with a 1µF capacitor.
15 D5 LINL Left-Line Input. AC-couple analog audio signal to LINL with a 1µF capacitor.
16 E6 LINR Right-Line Input. AC-couple analog audio signal to LINR with a 1µF capacitor.
Jack Sense or Auxiliary ADC Input. When configured for jack detection, JACKSNS
detects the presence or absence of a jack. See the Mode Configuration section
17 D4 JACKSNS/AUX
for details. When configured as an auxiliary ADC input, AUX is used to measure
DC voltages.
18 E5 PGND Headphone Power Ground
Positive Right-Channel Headphone Output. Connect directly to the load in
19 D3 ROUTP
differential and capacitorless mode. AC-couple to the load in single-ended mode.
Negative Right-Channel Headphone Output. Inverting output in differential mode.

20 E4 ROUTN Leave unconnected in capacitorless and fast turn-on single-ended mode. Bypass
with a 1µF capacitor to AGND in clickless, single-ended mode.
Negative Left-Channel Headphone Output. Noninverting output in differential
mode. Common headphone return in capacitorless mode. Leave unconnected in
21 D2 LOUTN
fast turn-on single-ended mode. Bypass with a 1µF capacitor to AGND in clickless
single-ended mode.
20 ______________________________________________________________________________________
Pin Description (continued)
MAX9867
PIN/BUMP
NAME FUNCTION
TQFN-EP WLP
Positive Left-Channel Headphone Output. Connect directly to the load in
22 E3 LOUTP
differential and capacitorless mode. AC-couple to the load in single-ended mode.
23 E2 PVDD Headphone Power Supply. Bypass to PGND with a 1µF capacitor.
24, 25 — N.C. No Connection
26 E1 DVDDIO Digital Audio Interface Power Supply. Bypass to DGND with a 1µF capacitor.
27 D1 SDOUT Digital Audio Serial-Data ADC Output
28 C2 SDIN Digital Audio Serial-Data DAC Input
Digital Audio Left-Right Clock Input/Output. LRCLK is the audio sample rate clock
and determines whether the audio data on SDIN is routed to the left or right
29 C1 LRCLK
channel. In TDM mode, LRCLK is a frame synchronization pulse. LRCLK is an
input when the MAX9867 is in slave mode and an output when in master mode.
Digital Audio Bit Clock Input/Output. BCLK is an input when the MAX9867 is in
30 B1 BCLK
slave mode and an output when in master mode.
31 B2 MCLK Master Clock Input. Acceptable input frequency range: 10MHz to 60MHz.
Digital Power Supply. Supply for the digital circuitry and I2C interface. Bypass to
32 A1 DVDD
DGND with a 1µF capacitor.
— — EP Exposed Pad. Connect the exposed thermal pad to AGND.
Detailed Description transmission noise. The digital filtering provides attenuation

of out-of-band energy by over 70dB, eliminating audi-
The MAX9867 is a low-power stereo audio codec
ble aliasing. A digital sidetone function allows audio
designed for portable applications requiring minimum
from the record path to be summed into the playback
power consumption.
path after digital filtering.
The stereo playback path accepts digital audio through
The MAX9867 also includes two stereo, single-ended
a flexible interface compatible with I2S, TDM, and left-
line inputs with gain adjustment, which can be record-
justified signals. An oversampling sigma-delta DAC
ed by the ADCs and/or output by the headphone ampli-
converts the incoming digital data stream to analog
fiers. An auxiliary ADC accurately measures a DC
audio and outputs the audio through the stereo head-
voltage by utilizing the right audio ADC and reporting
phone amplifier. The headphone amplifier can be con-
the DC voltage through the I2C interface. A jack detec-
figured in differential, single-ended, and capacitorless
tion function allows the detection of headphone, micro-
output modes.
phone, and headset jacks. Insertion and removal
The stereo record path has two analog microphone events can be programmed to trigger a hardware inter-
inputs with selectable gain. An integrated microphone rupt and flag an I2C register bit.
bias can be used to power the microphones. The left
The MAX9867’s flexible clock circuitry utilizes a program-
analog microphone inputs can also accept data from
mable clock divider and a digital PLL, allowing the DAC
up to two digital microphones. An oversampling sigma-
and ADC to operate at maximum dynamic range for all
delta ADC converts the microphone signals and out-
combinations of master clock (MCLK) and sample rate
puts the digital bit stream over the digital audio
(LRCLK) without consuming extra supply current. Any
interface.
master clock between 10MHz and 60MHz is supported
Integrated digital filtering provides a range of notch and as are all sample rates from 8kHz to 48kHz. Master and
highpass filters for both the playback and record paths slave modes are supported for maximum flexibility.
to limit undesirable low-frequency signals and GSM
______________________________________________________________________________________ 21
MAX9867
I2C Registers I2C Slave Address

The MAX9867 responds to the slave address 0x30 for
The MAX9867 audio codec is completely controlled
all write commands and 0x31 for all read operations.
through software using an I2C interface. The power-on
default setting is complete shutdown, requiring that the
internal registers be programmed to activate the device.
See Table 1 for the device’s complete register map.
Table 1. I2C Register Map

POWER-
REGISTER
REGISTER B7 B6 B5 B4 B3 B2 B1 B0 ON RESET
ADDRESS
STATE
STATUS
Status (Read Only) CLD SLD ULK 0 0 0 JDET 0 0x00 —
Jack Sense (Read Only) LSNS JKSNS JKMIC 0 0 0 0 0 0x01 —
AUX High (Read Only) AUX[15:8] 0x02 —
AUX Low (Read Only) AUX[7:0] 0x03 —
Interrupt Enable ICLD ISLD IULK 0 0 SDODLY IJDET 0 0x04 0x00
CLOCK CONTROL
System Clock 0 0 PSCLK FREQ 0x05 0x00
Stereo Audio Clock
PLL NI[14:8] 0x06 0x00
Control High
Stereo Audio Clock RLK/
NI[7:1] 0x07 0x00
Control Low NI[0]
DIGITAL AUDIO INTERFACE
Interface Mode MAS WCI BCI DLY HIZOFF TDM 0 0 0x08 0x00
Interface Mode 0 0 0 LVOLFIX DMONO BSEL 0x09 0x00
DIGITAL FILTERING
Codec Filters MODE AVFLT 0 DVFLT 0x0A 0x00
LEVEL CONTROL
Sidetone DSTS 0 DVST 0x0B 0x00
DAC Level 0 DACM DACG DACA 0x0C 0x00
ADC Level AVL AVR 0x0D 0x00
Left-Line Input Level 0 LILM 0 0 LIGL 0x0E 0x00
Right-Line Input Level 0 LIRM 0 0 LIGR 0x0F 0x00
Left Volume Control 0 VOLLM VOLL 0x10 0x00
Right Volume Control 0 VOLRM VOLR 0x11 0x00
Left Microphone Gain 0 PALEN PGAML 0x12 0x00
Right Microphone Gain 0 PAREN PGAMR 0x13 0x00
CONFIGURATION
ADC Input MXINL MXINR AUXCAP AUXGAIN AUXCAL AUXEN 0x14 0x00
Microphone MICCLK DIGMICL DIGMICR 0 0 0 0 0x15 0x00
Mode DSLEW VSEN ZDEN 0 JDETEN HPMODE 0x16 0x00
POWER MANAGEMENT
System Shutdown SHDN LNLEN LNREN 0 DALEN DAREN ADLEN ADREN 0x17 0x00
Revision REV 0xFF 0x42
22 ______________________________________________________________________________________
Device Status register and are set the next time the event occurs.
MAX9867
Status registers 0x00 and 0x01 are read-only registers Registers 0x02 and 0x03 report the DC level applied to
that report the status of various device functions. The AUX. See the ADC section for more details and Table 2.
status register bits are cleared upon reading the status
Table 2. Status Registers

REGISTER
REGISTER B7 B6 B5 B4 B3 B2 B1 B0
ADDRESS
Status (Read Only) CLD SLD ULK 0 0 0 JDET 0 0x00
Jack Sense (Read Only) LSNS JKSNS JKMIC 0 0 0 0 0 0x01
AUX High (Read Only) AUX[15:8] 0x02
AUX Low (Read Only) AUX[7:0] 0x03
BITS FUNCTION
Clip Detect Flag
CLD
Indicates that a signal has reached or exceeded full scale in the ADC or DAC.
Slew Level Detect Flag
When volume or gain changes are made, the slewing circuitry smoothly steps through all intermediate
SLD
settings. When SLD is set high, all slewing has completed and the volume or gain is at its final value. SLD
is also set when soft-start or stop is complete.
Digital PLL Unlock Flag
ULK
Indicates that the digital audio PLL has become unlocked and digital signal data is not reliable.
Headset Configuration Change Flag
JDET JDET is set whenever there is a change in register 0x01, indicating that the headset configuration has
changed.
LOUTP State (Valid if SHDN = 0, JDETEN = 1)
LSNS is set when the voltage at LOUTP exceeds AVDD - 0.4V. An internal pullup from AVDD to LOUTP
LSNS
causes this condition whenever there is no load on LOUTP. LSNS is only valid in differential and
capacitorless output modes.
JACKSNS State (Valid if JDETEN = 1)
JKSNS JKSNS is set when the voltage at JACKSNS exceeds AVDD - 0.4V. An internal pullup from AVDD to
JACKSNS causes this condition whenever there is no load on JACKSNS.
Microphone Detection (Valid if PALEN or PAREN ≠ 00 and JDETEN = 1)
JKMIC
JKMIC is set when JACKSNS exceeds 0.95 x VMICBIAS.
Auxiliary Input Measurement
AUX is a 16-bit signed two’s complement number representing the voltage measured at JACKSNS/AUX.
Before reading a value from AUX, set AUXCAP to 1 to ensure a stable reading. After reading the value,
set AUXCAP to 0.
AUX Use the following formula to convert the AUX value into an equivalent JACKSNS/AUX voltage:
⎛ AUX ⎞
Voltage = 0.738V × ⎜
⎝ k ⎟⎠
k = AUX value when AUXGAIN = 1. See the ADC section for complete details.
______________________________________________________________________________________ 23
Hardware Interrupts accommodate a wide range of system architectures,
MAX9867
Hardware interrupts are reported on the open-drain IRQ the MAX9867 supports three main clocking modes:
pin. When an interrupt occurs, IRQ remains low until the • Normal: This mode uses a 15-bit clock divider coeffi-
interrupt is serviced by reading the status register 0x00. cient to set the sample rate relative to the prescaled
If a flag is set, it is reported as a hardware interrupt only MCLK input (PCLK). This allows high flexibility in both
if the corresponding interrupt enable is set. Each bit the MCLK and LRCLK frequencies and can be used
enables interrupts for the status flag in the respective in either master or slave mode.
bit location in register 0x00. See Table 3.
• Exact Integer: In both master and slave mode, com-
SDODLY is used to control the SDOUT timing. See the mon MCLK frequencies (12MHz, 13MHz, 16MHz,
Digital Audio Interface section for a detailed description. and 19.2MHz) can be programmed to operate in
Clock Control exact integer mode for both 8kHz and 16kHz sample
The MAX9867 can work with a master clock (MCLK) rates. In these modes, the MCLK and LRCLK rates
supplied from any system clock within the 10MHz-to- are selected by using the FREQ bits instead of the NI
60MHz range. Internally, the MAX9867 requires a and PLL control bits.
10MHz-to-20MHz clock. A prescaler divides MCLK by • PLL: When operating in slave mode, a PLL can be
1, 2, or 4 to create the internal clock (PCLK). PCLK is enabled to lock onto externally generated LRCLK
used to clock all portions of the MAX9867. See Table 4. signals that are not integer related to PCLK. Prior to
The MAX9867 is capable of supporting any sample rate enabling the interface, program NI to the nearest
from 8kHz to 48kHz, including all common sample rates desired ratio and set the NI[0] = 1 to enable the
(8kHz, 16kHz, 24kHz, 32kHz, 44.1kHz, and 48kHz). To PLL’s rapid lock mode. If NI[0] = 0, then NI is ignored
and PLL lock time is slower.
Table 3. Interrupt Register
REGISTER
ADDRESS
Interrupt Enable ICLD ISLD IULK 0 0 SDODLY IJDET 0 0x04
Table 4. Clock Control Registers

REGISTER B7 B6 B5 B4 B3 B2 B1 B0 REGISTER
System Clock 0 0 PSCLK FREQ 0x05
Stereo Audio Clock
PLL NI[14:8] 0x06
Control High
Stereo Audio Clock
NI[7:1] NI[0] 0x07
Control Low
BITS FUNCTION
MCLK Prescaler
Divides MCLK to generate a PCLK between 10MHz and 20MHz.
00 = Disable clock for low-power shutdown.
PSCLK
01 = Select if MCLK is between 10MHz and 20MHz.
24 ______________________________________________________________________________________
MAX9867
Table 4. Clock Control Registers (continued)
BITS FUNCTION
Exact Integer Modes
Allows integer sampling for specific PCLK (prescaled MCLK) frequencies and 8kHz or 16kHz sample rates.
FREQ[3:0] PCLK (MHz) LRCLK (kHz) PCLK/LRCLK
0x00 Normal or PLL mode
0x1–0x7 Reserved Reserved Reserved
0x8 12 8 1500
0x9 12 16 750
FREQ 0xA 13 8 1625
0xB 13 16 812.5
0xC 16 8 2000
0xD 16 16 1000
0xE 19.2 8 2400
0xF 19.2 16 1200
Modes 0x8–0xF are available in either master or slave mode. In slave mode, if the indicated PCLK/LRCLK ratio
cannot be guaranteed, use PLL mode instead.
PLL Mode Enable
0 = Valid for slave and master mode. The frequency of LRCLK is set by the NI divider bits. In master mode, the
MAX9867 generates LRCLK using the specified divide ratio. In slave mode, the MAX9867 expects an
LRCLK as specified by the divide ratio.
PLL
1 = Valid for slave mode only. A digital PLL locks on to any externally supplied LRCLK signal.
Rapid Lock Mode

To enable rapid lock mode, set NI to the nearest desired ratio and set NI[0] = 1 before enabling the interface.
Normal Mode LRCLK Divider
When PLL = 0, the frequency of LRCLK is determined by NI. See Table 5 for common NI values.
NI = (65536 x 96 x fLRCLK)/fPCLK
NI
fLRCLK = LRCLK frequency
fPCLK = Prescaled MCLK internal clock frequency (PCLK)
LRCLK > 24kHz is only valid for MODE = 0 (stereo audio mode). MODE = 1 (voice mode) requires LRCLK ≤
24kHz.
Table 5. Common NI Values

LRCLK (kHz)
MCLK (MHz)
PSCLK 8 16 24 32 44.1 48
11.2896 01 0x116A 0x22D4 0x343F 0x45A9 0x6000 0x687D
12 01 0x1062 0x20C5 0x3127 0x4189 0x5A51 0x624E
12.288 01 0x1000 0x2000 0x3000 0x4000 0x5833 0x6000
13 01 0x0F20 0x1E3F 0x2D5F 0x3C7F 0x535F 0x5ABE
19.2 01 0x0A3D 0x147B 0x1EB8 0x28F6 0x3873 0x3D71
24 10 0x1062 0x20C5 0x1893 0x4189 0x5A51 0x624E
26 10 0x0F20 0x1E3F 0x16AF 0x3C7F 0x535F 0x5ABE
27 10 0x0E90 0x1D21 0x15D8 0x3A41 0x5048 0x5762
Note: Bolded values are exact integers that provide maximum full-scale performance.
______________________________________________________________________________________ 25
Digital Audio Interface mode, BCLK can be configured in a number of ways to
MAX9867
The MAX9867’s digital audio interface supports a wide ensure compatiblity with other audio devices.
range of operating modes to ensure maximum compati- LVOLFIX is used to fix the line input playback volume to
bility. See Figures 1–4 for timing diagrams. In master 0dB regardless of VOLL and VOLR. See the Line Inputs
mode, the MAX9867 outputs LRCLK and BCLK, while in section for complete details and Table 6.
slave mode they are inputs. When operating in master
Table 6. Digital Audio Interface Registers

REGISTER
ADDRESS
Interface Mode MAS WCI BCI DLY HIZOFF TDM 0 0 0x08
Interface Mode 0 0 0 LVOLFIX DMONO BSEL 0x09
BITS FUNCTION
Master Mode
MAS 0 = The MAX9867 operates in slave mode with LRCLK and BCLK configured as inputs.
1 = The MAX9867 operates in master mode with LRCLK and BCLK configured as outputs.
LRCLK Invert
0 = Left-channel data is input and output while LRCLK is low.
WCI
1 = Right-channel data is input and output while LRCLK is low.
Note: WCI is ignored when TDM = 1.
BCLK Invert
In master and slave modes:
0 = SDIN is latched into the part on the rising edge of BCLK.
SDOUT transitions after the rising edge of BCLK as determined by SDODLY.
BCI 1 = SDIN is latched into the part on the falling edge of BCLK.
SDOUT transitions after the falling edge of BCLK as determined by SDODLY.
In master mode:
0 = LRCLK changes state immediately after the rising edge of BCLK.
1 = LRCLK changes state immediately after the falling edge of BCLK.
SDOUT Delay
0 = SDOUT transitions one half BCLK cycle after SDIN is latched into the part.
SDODLY
1 = SDOUT transitions on the same BCLK edge as SDIN is latched into the part.
See Figures 1–4 for complete details. See Register 0x04 (interrupt registers).
Delay Mode
0 = SDIN/SDOUT data is latched on the first BCLK edge following an LRCLK edge.
DLY 1 = SDIN/SDOUT data is assumed to be delayed one BCLK cycle so that it is latched on the 2nd BCLK edge
following an LRCLK edge (I2S-compatible mode).
Note: DLY is ignored when TDM = 1.
SDOUT High-Impedance Mode
0 = SDOUT goes to a high-impedance state after all data bits have been transferred out of the MAX9867,
HIZOFF allowing SDOUT to be shared by other devices.
1 = SDOUT is set either high or low after all data bits have been transferred out of the MAX9867.
Note: High-impedance mode is intended for use when TDM = 1.
LVOLFIX See the Line Inputs section.
26 ______________________________________________________________________________________
MAX9867
Table 6. Digital Audio Interface Registers (continued)
BITS FUNCTION
TDM Mode Select
0 = LRCLK signal polarity indicates left and right audio.
1 = LRCLK is a framing pulse that transitions polarity to indicate the start of a frame of audio data consisting
TDM
of multiple channels.
When operating in TDM mode, the left channel is output immediately following the frame sync pulse. If right-
channel data is being transmitted, the 2nd channel of data immediately follows the 1st channel data.
Mono Playback Mode
DMONO 0 = Stereo data input on SDIN is processed separately.
1 = Stereo data input on SDIN is mixed to a single channel and routed to both the left and right DAC.
BCLK Select
Configures BCLK when operating in master mode. BSEL has no effect in slave mode. Set BSEL = 010, unless
sharing the bus with multiple devices:
000 = Off
001 = 64x LRCLK (192x internal clock divided by 3)
BSEL 010 = 48x LRCLK (192x internal clock divided by 4)
011 = Reserved for future use.
100 = PCLK/2
101 = PCLK/4
110 = PCLK/8
111 = PCLK/16
______________________________________________________________________________________ 27
MAX9867
AUDIO MASTER MODES:

LEFT JUSTIFIED: WCI = 0, BCI = 0, DLY = 0, SDODLY = 0
7ns (typ) 7ns (typ)

LRCLK LEFT RIGHT
1/fS
RELATIVE TO PCLK (SEE NOTE)
SDOUT D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
40ns (max)
0ns (min)
7ns (typ) 7ns (typ)
BCLK
CONFIGURED BY BSEL
25ns (min) 0ns (min)
SDIN D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LEFT JUSTIFIED + LRCLK INVERT: WCI = 1, BCI = 0, DLY = 0, SDODLY = 0
7ns (typ) 7ns (typ)

LRCLK LEFT RIGHT
1/fS
40ns (max)
0ns (min)
7ns (typ) 7ns (typ)
BCLK
CONFIGURED BY BSEL
LEFT JUSTIFIED + BCLK INVERT: WCI = 0, BCI = 1, DLY = 0, SDODLY = 0
7ns (typ) 7ns (typ)

LRCLK LEFT RIGHT
1/fS
40ns (max)
0ns (min)
7ns (typ) 7ns (typ)
BCLK
CONFIGURED BY BSEL
NOTE: THE DELAY FROM A BCLK EDGE AND AN LRCLK EDGE IS DETERMINED BY LENGTH OF TIME THAT PCLK (THE INTERNALLY DIVIDED DOWN VERSION OF MCLK AS DEFINED BY THE PSCLK BITS) IS HIGH DURING ONE PERIOD OF
MCLK PLUS THE INTERNAL DELAY. FOR EXAMPLE: IF PCLK = 12.288MHZ, THEN THE DELAY BETWEEN BCLK AND LRCLK IS TYPICALLY 45ns.
Figure 1. Digital Audio Interface Audio Master Mode Example (Sheet 1 of 2)
28 ______________________________________________________________________________________
MAX9867
I2S: WCI = 0, BCI = 0, DLY = 1, SDODLY = 0
7ns (typ) 7ns (typ)

LRCLK LEFT RIGHT
1/fS
40ns (max)
0ns (min)
7ns (typ) 7ns (typ)
BCLK
CONFIGURED BY BSEL
7ns (typ) 7ns (typ)

LRCLK LEFT RIGHT
1/fS
40ns (max)
0ns (min)
7ns (typ) 7ns (typ)
BCLK
CONFIGURED BY BSEL
NOTE: THE DELAY FROM A BCLK EDGE AND AN LRCLK EDGE IS DETERMINED BY LENGTH OF TIME THAT PCLK (THE INTERNALLY DIVIDED DOWN VERSION OF MCLK AS DEFINED BY THE PSCLK BITS) IS HIGH DURING ONE PERIOD OF
MCLK PLUS THE INTERNAL DELAY. FOR EXAMPLE: IF PCLK = 12.288MHZ, THEN THE DELAY BETWEEN BCLK AND LRCLK IS TYPICALLY 45ns.
Figure 1. Digital Audio Interface Audio Master Mode Example (Sheet 2 of 2)
______________________________________________________________________________________ 29
MAX9867
VOICE (TDM, PCM) MASTER MODES:

BCI = 0, HIZOFF = 0, SDODLY = 0
7ns (typ) 7ns (typ)
LRCLK
1/fS
SDOUT L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
40ns (max)
0ns (min) 7ns (typ) 7ns (typ)
BCLK
CONFIGURED BY BSEL
SDIN L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
7ns (typ) 7ns (typ)

LRCLK
1/fS
40ns (max)
BCLK
CONFIGURED BY BSEL
7ns (typ) 7ns (typ)

LRCLK
1/fS
40ns (max)
BCLK
CONFIGURED BY BSEL
7ns (typ) 7ns (typ)

LRCLK
1/fS
40ns (max)
BCLK
CONFIGURED BY BSEL
Figure 2. Digital Audio Interface Voice Master Mode Examples
30 ______________________________________________________________________________________
MAX9867
AUDIO SLAVE MODES:
LRCLK LEFT RIGHT

1/fS
40ns (max)
0ns (min)
30ns (min)
BCLK
LEFT JUSTIFIED + LRCLK INVERT: WCI = 1, BCI = 0, DLY = 0, SDODLY = 0
LRCLK LEFT RIGHT

1/fS
40ns (max)
0ns (min)
30ns (min)
BCLK
LEFT JUSTIFIED + BCLK INVERT: WCI = 0, BCI = 1, DLY = 0, SDODLY = 0
LRCLK LEFT RIGHT

1/fS
40ns (max)
BCLK
Figure 3. Digital Audio Interface Audio Slave Mode Examples (Sheet 1 of 2)
______________________________________________________________________________________ 31
MAX9867
I2S: WCI = 0, BCI = 0, DLY = 1, SDODLY = 0
LRCLK LEFT RIGHT

1/fS
40ns (max)
0ns (min)
30ns (min)
BCLK
LRCLK LEFT RIGHT

1/fS
40ns (max)
0ns (min)
30ns (min)
BCLK
Figure 3. Digital Audio Interface Audio Slave Mode Examples (Sheet 2 of 2)
32 ______________________________________________________________________________________
MAX9867
VOICE (TDM, PCM) SLAVE MODES:
LRCLK
1/fS
0ns (min)
40ns (max)
BCLK
LRCLK
1/fS
0ns (min)
40ns (max)
0ns (min)
30ns (min)
BCLK
LRCLK
1/fS
0ns (min)
40ns (max)
BCLK
LRCLK
1/fS
0ns (min)
40ns (max)
BCLK
Figure 4. Digital Audio Interface Voice Slave Mode Examples
______________________________________________________________________________________ 33
Digital Filtering stopband attenuation as well as selectable highpass fil-
MAX9867
The MAX9867 incorporates both IIR (voice) and FIR ters. The FIR filters provide low-power consumption and
(audio) digital filters to accomodate a wide range of are linear phase to maintain stereo imaging. Table 7 is
audio sources. The IIR fiilters provide over 70dB of the digital filtering register.
Table 7. Digital Filtering Register

REGISTER
ADDRESS
Codec Filters MODE AVFLT 0 DVFLT 0x0A
BITS FUNCTION
Digital Audio Filter Mode
MODE 0 = IIR Voice Filters
1 = FIR Audio Filters
ADC Digital Audio Filter
MODE = 0
Select the desired digital filter response from Table 8. See the Frequency Response graph in the Typical
AVFLT
Operating Characteristics section for details on each filter.
MODE = 1
0x0 = DC-blocking filter is disabled. Any other setting = DC-blocking filter is enabled.
DAC Digital Audio Filter

MODE = 0
Select the desired digital filter response from Table 8. See the Frequency Response graph in the Typical
DVFLT
Operating Characteristics section for details on each filter.
MODE = 1
0x0 = DC-blocking filter is disabled. Any other setting = DC-blocking filter is enabled.
Table 8. IIR Highpass Digital Filters

INTENDED SAMPLE HIGHPASS CORNER
CODE FILTER TYPE 217Hz NOTCH
RATE (kHz) FREQUENCY (Hz)
0x0 Disabled
0x1 Elliptical 16 256 Yes
0x2 Butterworth 16 500 No
0x3 Elliptical 8 256 Yes
0x4 Butterworth 8 500 No
0x5 Butterworth 8 to 24 fS/240 No
0x6 to 0x7 Reserved
34 ______________________________________________________________________________________
Digital Gain Control gain adjustment is also provided to set the sidetone
MAX9867
The MAX9867 includes digital gain adjustment for the level relative to the playback level. Table 9 is the digital
playback and record paths. Independent gain adjust- gain registers.
ment is provided for the two record channels. Sidetone
Table 9. Digital Gain Registers
REGISTER
ADDRESS
Sidetone DSTS 0 DVST 0x0B
DAC Level 0 DACM DACG DACA 0x0C
ADC Level AVL AVR 0x0D
BITS FUNCTION
Digital Sidetone Source Mixer
00 = No sidetone is selected.
DSTS 01 = Left ADC
10 = Right ADC
11 = Left + right ADC
Digital Sidetone Level Control
All gain settings are relative to the ADC input voltage.
Differential Headphone Output Mode

SETTING GAIN (dB) SETTING GAIN (dB) SETTING GAIN (dB)
0x00 Off 0x0B -20 0x16 -42
0x01 0 0x0C -22 0x17 -44
0x02 -2 0x0D -24 0x18 -46
0x03 -4 0x0E -26 0x19 -48
0x04 -6 0x0F -28 0x1A -50
0x05 -8 0x10 -30 0x1B -52
0x06 -10 0x11 -32 0x1C -54
0x07 -12 0x12 -34 0x1D -56
0x08 -14 0x13 -36 0x1E -58
0x09 -16 0x14 -38 0x1F -60
DVST
0x0A -18 0x15 -40 — —
Capacitorless and Single-Ended Headphone Output Mode
0x00 Off 0x0B -25 0x16 -47
0x01 -5 0x0C -27 0x17 -49
0x02 -7 0x0D -29 0x18 -51
0x03 -9 0x0E -31 0x19 -53
0x04 -11 0x0F -33 0x1A -55
0x05 -13 0x10 -35 0x1B -57
0x06 -15 0x11 -37 0x1C -59
0x07 -17 0x12 -39 0x1D -61
0x08 -19 0x13 -41 0x1E -63
0x09 -21 0x14 -43 0x1F -65
0x0A -23 0x15 -45 — —
DAC Mute Enable
DACM 0 = No mute
1 = Mute
______________________________________________________________________________________ 35
MAX9867
Table 9. Digital Gain Registers (continued)

BITS FUNCTION
DAC Gain
00 = 0dB
01 = +6dB
DACG
10 = +12dB
11 = +18dB
Note: DACG is only used when MODE = 0. If MODE = 1, the DAC level is only set by DACA.
DAC Level Control
DACA works in all modes.

SETTING GAIN (dB) SETTING GAIN (dB)
0x0 0 0x8 -8
0x1 -1 0x9 -9
DACA 0x2 -2 0xA -10
0x3 -3 0xB -11
0x4 -4 0xC -12
0x5 -5 0xD -13
0x6 -6 0xE -14
0x7 -7 0xF -15
ADC Left/Right Level Control
0x0 +3 0x8 -5
0x1 +2 0x9 -6
0x2 +1 0xA -7
AVL/AVR
0x3 0 0xB -8
0x4 -1 0xC -9
0x5 -2 0xD -10
0x6 -3 0xE -11
0x7 -4 0xF -12
Line Inputs to the headphone amplifier and can be optionally con-

The MAX9867 includes one pair of single-ended line nected to the ADC for recording. Table 10 lists the line
inputs. When enabled, the line inputs connect directly input registers.
Table 10. Line Input Registers

REGISTER
ADDRESS
Left-Line Input Level 0 LILM 0 0 LIGL 0x0E
Right-Line Input Level 0 LIRM 0 0 LIGR 0x0F
36 ______________________________________________________________________________________
MAX9867
Table 10. Line Input Registers (continued)
BITS FUNCTION
Line-Input Left/Right Playback Mute
LILM/LIRM 0 = Line input is connected to the headphone amplifiers.
1 = Line input is disconnected from the headphone amplifiers.
Line-Input Left/Right Gain
0x0 +24 0x8 +8
0x1 +22 0x9 +6
0x2 +20 0xA +4
LIGL/LIGR
0x3 +18 0xB +2
0x4 +16 0xC 0
0x5 +14 0xD -2
0x6 +12 0xE -4
0x7 +10 0xF -6
Fix Line Input Volume
0 = Line input to headphone output volume tracks VOLL and VOLR bits.
LVOLFIX
1 = Line input to headphone output volume fixed at VOLL and VOLR bits.
See the Digital Audio Interface section.
Playback Volume registers 0x10 and 0x11 to set the desired volume. See
The MAX9867 incorporates volume and mute control to Table 11.
allow level control for the playback audio path. Program
Table 11. Playback Volume Registers

REGISTER
ADDRESS
Left Volume Control 0 VOLLM VOLL 0x10
Right Volume Control 0 VOLRM VOLR 0x11
______________________________________________________________________________________ 37
MAX9867
Table 11. Playback Volume Registers (continued)

BITS FUNCTION
Left/Right Playback Mute
VOLLM and VOLRM mute both the DAC and line input audio signals.
0 = Audio playback is unmuted.
VOLLM/VOLRM
1 = Audio playback is muted
Note: VSEN has no effect on the mute function. When VOLLM or VOLRM is set, the output is muted
immediately (ZDEN = 1) or at the next zero-crossing (ZDEN = 0).
Left/Right Playback Volume
VOLL and VOLR control the playback volume for both the DAC and line input audio signals.
0x00 +6 0x0E -5 0x1C -42
0x01 +5.5 0x0F -6 0x1D -46
0x02 +5 0x10 -8 0x1E -50
0x03 +4.5 0x11 -10 0x1F -54
0x04 +4 0x12 -12 0x20 -58
0x05 +3.5 0x13 -14 0x21 -62
VOLL/VOLR 0x06 +3 0x14 -16 0x22 -66
0x07 +2 0x15 -18 0x23 -70
0x08 +1 0x16 -20 0x24 -74
0x09 0 0x17 -22 0x25 -78
0x0A -1 0x18 -26 0x26 -82
0x0B -2 0x19 -30 0x27 -84
0x0C -3 0x1A -34
0x28 to 0x3F MUTE
0x0D -4 0x1B -38
Note: Gain settings apply when the headphone amplifier is configured in differential mode. In the single-
ended and capacitorless modes, the actual gain is 5dB lower for each setting.
Microphone Inputs the ADCs. The first stage offers selectable 0dB, 20dB,
Two differential microphone inputs and a low-noise micro- or 30dB settings. The second stage is a programmable
phone bias for powering the microphones are provided gain amplifier (PGA) adjustable from 0dB to 20dB in
by the MAX9867. In typical applications, the left micro- 1dB steps. Zero-crossing detection is included on the
phone records a voice signal and the right microphone PGA to minimize zipper noise while making gain
records a background noise signal. In applications that changes. See Figure 5 for a detailed diagram of the
require only one microphone, use the left microphone microphone input structure. Table 12 is the microphone
input and disable the right ADC. The microphone signals input register.
are amplified by two stages of gain and then routed to
Table 12. Microphone Input Registers

REGISTER
ADDRESS
Left Microphone Gain 0 PALEN PGAML 0x12
Right Microphone Gain 0 PAREN PGAMR 0x13
38 ______________________________________________________________________________________
MAX9867
Table 12. Microphone Input Registers (continued)
BITS FUNCTION
Left/Right Microphone Preamplifier Gain
Enables the microphone circuitry and sets the preamplifier gain.
00 = Disabled
PALEN/PAREN
01 = 0dB
10 = +20dB
11 = +30dB
Left/Right Microphone Programmable Gain Amplifier
0x00 +20 0x0B +9
0x01 +19 0x0C +8
0x02 +18 0x0D +7
0x03 +17 0x0E +6
PGAML/PGAMR 0x04 +16 0x0F +5
0x05 +15 0x10 +4
0x06 +14 0x11 +3
0x07 +13 0x12 +2
0x08 +12 0x13 +1
0x09 +10 0x14
0
0x0A +11 to 0x1F
MAX9867
MICBIAS 1.5V
0/20/30dB
VREG
0dB TO +20dB
MICLP
PREAMP PGA ADC
MICLN L
0/20/30dB
VREG 0dB TO +20dB
MICRP
PREAMP PGA ADC
MICRN R
Figure 5. Microphone Input Signal Path
______________________________________________________________________________________ 39
ADC
MAX9867
Table 13. AUX ADC Wait Times

The MAX9867 includes two 16-bit ADCs. The first ADC
is used to record left-channel microphone and line-input WAIT TIMES
audio signals. The second ADC can be used to record LRCLK (kHz) WAIT TIME (ms)
right-channel microphone and line-input signals, or it
48 40
can be configured to accurately measure DC voltages.
44.1 44
When measuring DC voltages, both the left and right
ADCs must be enabled by setting ADLEN and ADREN 32 60
in register 0x17. The input to the second ADC is JACK- 24 80
SNS/AUX and the output is reported in AUX (registers 22.05 90
0x02 and 0x03). Since the audio ADC is used to per-
16 120
form the measurement, the digital audio interface must
be properly configured. If the left ADC is being used to 12 160
convert audio, the DC measurement is performed at the 11.025 175
same sample rate. When not using the left ADC, config- 8 240
ure the digital interface for a 48kHz sample rate to
ensure the fastest possible settling time. 1) Enable the AUX input (AUXEN = 1).
To ensure accurate results, the MAX9867 includes two 2) Enable the offset calibration (AUXCAL = 1).
calibration routines. Calibrate the ADC each time the
MAX9867 is powered on. Calibration settings are not 3) Wait the appropriate time (see Table 13).
lost if the MAX9867 is placed in shutdown. When mak- 4) Complete calibration (AUXCAL = 0).
ing a measurement, set AUXCAP to 1 to prevent AUX
from changing while reading the registers. Gain Calibration Procedure
Perform the following steps the first time a DC measure-
Setup Procedure ment is taken after applying power to the MAX9867 or if
1) Ensure a valid MCLK signal is provided and config- the temperature changes significantly:
ure PSCLK appropriately. 1) Enable the AUX input (AUXEN = 1).
2) Choose a clocking mode. The following options are 2) Start gain calibration (AUXGAIN = 1).
possible:
3) Wait the appropriate time (see Table 13).
• Slave mode with LRCLK and BCLK signals pro-
vided. The measurement sample rate is deter- 4) Freeze the measurement results (AUXCAP = 1).
mined by the external clocks. 5) Read AUX and store the value in memory to correct
• Slave mode with no LRCLK and BCLK signals all future measurements (k = AUX[15:0], k is typical-
provided. Configure the device for normal clock ly 19500).
mode using the NI ratio. Select fS = 48kHz to allow 6) Complete calibration (AUXGAIN = AUXCAP = 0).
for the fastest settling times.
DC Measurement Procedure
• Master mode with audio. Configure the device in
Perform the following steps after offset and gain cali-
normal mode using the NI ratio or exact integer
bration are complete:
mode using FREQ as required by the audio signal.
1) Enable the AUX input (AUXEN = 1).
• Master mode without audio. Configure the
device in normal mode using the NI ratio. Select fS 2) Wait the appropriate time (see Table 13).
= 48kHz to allow for the fastest settling times. 3) Freeze the measurement results (AUXCAP = 1).
3) Ensure JACKSNS is disabled. 4) Read AUX and correct with the gain calibration
4) Enable the left and right ADC; take the MAX9867 out value:
of shutdown.
⎛ AUX[15 : 0] ⎞
Offset Calibration Procedure VAUX = 0.738⎜ ⎟
⎝ k ⎠
Perform the following steps before the first DC mea-
surement is taken after applying power to the 5) Complete measurement (AUXCAP = 0).
MAX9867:
40 ______________________________________________________________________________________
Complete DC Measurement Example b. Wait 40ms.
MAX9867
MCLK = 13MHz, slave mode, BCLK and LRCLK not c. Freeze the measurement results (AUXCAP = 1).
externally supplied:
d. Read AUX and store the value in memory to cor-
1) Configure the digital audio interface for fS = 48kHz rect all future measurements (k = AUX[15:0]).
(PSCLK = 01, FREQ = 0x0, PLL = 0, NI = 0x5ABE,
MAS = 0). e. Complete calibration (AUXGAIN = AUXCAP =
AUXEN = 0).
2) Disable JACKSNS (JDETEN = 0).
6) Measure the voltage on JACKSNS/AUX:
3) Enable the left and right ADC; take the MAX9867 out
of shutdown (ADLEN = ADREN = SHDN = 1). a. Enable the AUX input (AUXEN = 1).
4) Calibrate the offset: b. Wait 40ms.
a. Enable the AUX input (AUXEN = 1). c. Freeze the measurement results (AUXCAP = 1).
b. Enable the offset calibration (AUXCAL = 1). d. Read AUX and correct with the gain calibration
value.
c. Wait 40ms.
e. Complete measurement (AUXCAP = 0).
d. Complete calibration (AUXCAL = 0).
7) DC measurement complete.
5) Calibrate the gain:
a. Start gain calibration (AUXGAIN = 1).
Table 14. ADC Input Register

REGISTER
ADDRESS
ADC Input MXINL MXINR AUXCAP AUXGAIN AUXCAL AUXEN 0x14
BITS FUNCTION
Left/Right ADC Audio Input Mixer
00 = No input is selected.
01 = Left/right analog microphone
10 = Left/right line input
MXINL/MXINR
11 = Left/right analog microphone + line input
Note: If the right-line input is disabled, then the left-line input is connected to both mixers. Enabling the
left and right digital microphones disables the left and right audio mixers, respectively. See DIGMICL/
DIGMICR in Table 15 for more details.
Auxiliary Input Capture
AUXCAP 0 = Update AUX with the voltage at JACKSNS/AUX.
1 = Hold AUX for reading.
Auxiliary Input Gain Calibration
0 = Normal operation
AUXGAIN 1 = The input buffer is disconnected from JACKSNS/AUX and connected to an internal voltage reference.
While in this mode, read the AUX register and store the value. Use the stored value as a gain
calibration factor, K, on subsequent readings.
Auxiliary Input Offset Calibration
0 = Normal operation
AUXCAL
1 = JACKSNS/AUX is disconnected from the input and the ADC automatically calibrates out any internal
offsets.
Auxiliary Input Enable
0 = Use JACKSNS/AUX for jack detection.
AUXEN
1 = Use JACKSNS/AUX for DC measurements.
Note: For AUXEN = 1, set MXINR = 00, ADLEN = 1, and ADREN = 1.
______________________________________________________________________________________ 41
Digital Microphone Input phone input. The right analog microphone input is still
MAX9867
The MAX9867 can accept audio from up to two digital available to allow a combination of analog and digital
microphones. When using digital microphones, the left microphones to be used. Figure 6 shows the digital
analog microphone input is retasked as a digital micro- microphone interface timing diagram. See Table 15.
Table 15. Digital Microphone Input Register

REGISTER
ADDRESS
Microphone MICCLK DIGMICL DIGMICR 0 0 0 0 0x15
BITS FUNCTION
Digital Microphone Clock
00 = PCLK/8
MICCLK 01 = PCLK/6
10 = Reserved
11 = Reserved
Digital Left/Right Microphone Enable
DIGMICL DIGMICR Left ADC Input Right ADC Input
0 0 ADC input mixer ADC input mixer
Line input (left analog
DIGMICL/DIGMICR 0 1 Right digital microphone
microphone unavailable)
1 0 Left digital microphone ADC input mixer
1 1 Left digital microphone Right digital microphone
Note: The left analog microphone input is never available when DIGMICL or DIGMICR = 1.
1/fMICCLK
DIGMICCLK
tHD, MIC tSU, MIC tHD, MIC tSU, MIC
DIGMICDATA LEFT RIGHT LEFT RIGHT
Figure 6. Digital Microphone Timing Diagram
42 ______________________________________________________________________________________
Mode Configuration Powered-On Headset Detection
MAX9867
The MAX9867 includes circuitry to minimize click-and- When the MAX9867 is in normal operation and the micro-
pop during volume changes, detect headsets, and con- phone interface is enabled, jack insertion and removal can
figure the headphone amplifier mode. Both volume be detected through the JACKSNS/AUX pin. As shown in
slewing and zero-crossing detection are included to Figure 7, VMIC is pulled up by MICBIAS. When a micro-
ensure click-and-pop free volume transitions. Table 16 phone is connected, VMIC is assumed to be between 0V
is the mode configuration register. and 95% of VMICBIAS. If the jack is removed, VMIC increas-
es to VMICBIAS. This event causes JKMIC to be set, alert-
Headset Detection Overview ing the system that the headset has been removed.
The MAX9867 features headset detection that can detect Alternatively, if the jack is inserted, VMIC decreases to
the insertion and removal of a jack as well as the load below 95% of VMICBIAS and JKMIC is cleared, alerting the
type. When a jack is detected, an interrupt on IRQ can be system that a jack has been inserted. The JKMIC bit can
triggered to alert the microcontroller of the event. Figure 7 be configured to create a hardware interrupt that alerts the
shows the typical configuration for jack detection. microcontroller of jack removal and insertion events.
Sleep-Mode Headset Detection Headphone Modes
When the MAX9867 is in shutdown and the power supply The headphone amplifier supports differential, single-
is available, sleep-mode headset detection can be ended, and capacitorless output modes, as shown in
enabled to detect jack insertion. Sleep mode applies a Figure 8. In each mode, the amplifier can be configured
4µA pullup current to JACKSNS/AUX and LOUTP that for stereo or mono operation. The differential and
forces the voltage on JACKSNS/AUX and LOUTP to capacitorless modes are inherently click and pop free.
AVDD when no load is applied. When a jack is inserted, The single-ended mode optionally includes click-and-
either JACKSNS, LOUTP (assuming the headphone pop reduction to eliminate the click and pop that would
amplifier is not configured in single-ended mode), or both normally be caused by the output coupling capacitor.
are loaded sufficiently to reduce the output voltage to When click-and-pop reduction is not required in the sin-
nearly 0V and clear the JKSNS or LSNS bits, respectively. gle-ended configuration, leave LOUTN and ROUTN
The change in the LSNS and JKSNS bits sets JDET and unconnected.
triggers an interrupt on IRQ if IJDET is set. The interrupt
signals the microcontroller that a jack has been inserted,
allowing the microcontroller to respond as desired.
LOUTP
MICBIAS
GND MIC HPR HPL
JACKSNS/AUX
ROUTP
MICLP
LOUTN
Figure 7. Typical Configuration for Headset Detection
DIFFERENTIAL CAPACITORLESS SINGLE ENDED

220µF
LOUTP LOUTP LOUTP
LOUTN LOUTN LOUTN
1µF
220µF
ROUTP ROUTP ROUTP
ROUTN ROUTN ROUTN
1µF
OPTIONAL COMPONENTS REQUIRED FOR CLICK AND POP SUPPRESSION ONLY
Figure 8. Headphone Amplifier Modes
______________________________________________________________________________________ 43
MAX9867
Table 16. Mode Configuration Register

REGISTER
ADDRESS
Mode DSLEW VSEN ZDEN 0 JDETEN HPMODE 0x16
BITS FUNCTION
Digital Volume Slew Speed
DSLEW 0 = Digital volume changes are slewed over 10ms.
1 = Digital volume changes are slewed over 80ms.
Volume Change Smoothing
VSEN 0 = Volume changes slew through all intermediate values.
1 = Volume changes occur in one step.
Line Input Zero-Crossing Detection
0 = Line input volume changes occur at zero crossings in the audio waveform or after 62ms if no zero
ZDEN
crossing occurs.
1 = Line-input volume changes occur immediately.
Jack Detection Enable
SHDN = 0: Sleep Mode
Enables pullups on LOUTP and JACKSNS/AUX to detect jack insertion. LSNS and JKSNS are valid.
LOUTP detection is only valid in differential and capacitorless output modes.
JDETEN
SHDN = 1: Normal Mode
Enables the comparator circuitry on JACKSNS/AUX to detect voltage changes. JKMIC is valid if the
microphone circuitry is enabled.
Note: AUXEN must be set to 0 for jack detection to function.
Headphone Amplifier Mode
HPMODE Mode
000 Stereo differential (clickless)
001 Mono (left) differential (clickless)
010 Stereo capacitorless (clickless)
HPMODE 011 Mono (left) capacitorless (clickless)
100 Stereo single-ended (clickless)
101 Mono (left) single-ended (clickless)
110 Stereo single-ended (fast turn-on)
111 Mono (left) single-ended (fast turn-on)
Note: In mono operation, the right amplifier is disabled.
44 ______________________________________________________________________________________
Power Management required circuitry is active. Toggle the SHDN bit when-
MAX9867
The MAX9867 includes complete power management ever a configuration change is made. Table 17 is the
control to minimize power usage. The DAC and both power-management register.
ADC can be independently enabled so that only the
Table 17. Power-Management Register

REGISTER
ADDRESS
System Shutdown SHDN LNLEN LNREN 0 DALEN DAREN ADLEN ADREN 0x17
BITS FUNCTION
Shutdown
SHDN
Places the device in low-power shutdown mode.
Left-Line Input Enable
Enables the left-line input preamp and automatically enables the left and right headphone amplifiers.
LNLEN If LNREN = 0, the left-line input signal is also routed to the right ADC input mixer and right headphone
amplifier.
Note: Control of the right headphone amplifier can be overridden by HPMODE.
Right-Line Input Enable
LNREN Enables the right-line input preamp and automatically enables the right headphone amplifier.
Left DAC Enable
Enables the left DAC and automatically enables the left and right headphone amplifiers. If DAREN = 0, the
DALEN
left DAC signal is also routed to the right headphone amplifier.
Right DAC Enable
DAREN Enabling the right DAC must be done in the same I2C write operation that enables the left DAC. Right
DAC operation requires DALEN = 1.
ADLEN Left ADC Enable
Right ADC Enable
Enabling the right ADC must be done in the same I2C write operation that enables the left ADC. The right
ADREN
ADC can be enabled while the left ADC is running if used for DC measurements. SHDN must be toggled
to disable the right ADC in this case. Right ADC operation requires ADLEN = 1.
Revision Code
The MAX9867 includes a revision code to allow easy
identification of the device revision. The revision code is
0x42. See Table 18 for the revision code register.
Table 18. Revision Code Register
REGISTER
ADDRESS
Revision REV 0xFF
______________________________________________________________________________________ 45
I2C Serial Interface required on SCL if there are multiple masters on the bus,
MAX9867
The MAX9867 features an I 2 C/SMBus-compatible, or if the single master has an open-drain SCL output.
2-wire serial interface consisting of a serial-data line Series resistors in line with SDA and SCL are optional.
(SDA) and a serial-clock line (SCL). SDA and SCL facili- Series resistors protect the digital inputs of the
tate communication between the MAX9867 and the mas- MAX9867 from high-voltage spikes on the bus lines, and
ter at clock rates up to 400kHz. Figure 9 shows the minimize crosstalk, and undershoot of the bus signals.
2-wire interface timing diagram. The master generates
SCL and initiates data transfer on the bus. The master Bit Transfer
device writes data to the MAX9867 by transmitting the One data bit is transferred during each SCL cycle. The
proper slave address followed by the register address data on SDA must remain stable during the high period
and then the data word. Each transmit sequence is of the SCL pulse. Changes in SDA while SCL is high
framed by a START (S) or REPEATED START (Sr) condi- are control signals. See the START and STOP
tion and a STOP (P) condition. Each word transmitted to Conditions section.
the MAX9867 is 8 bits long and is followed by an START and STOP Conditions
acknowledge clock pulse. A master reading data from SDA and SCL idle high when the bus is not in use. A
the MAX9867 transmits the proper slave address master initiates communication by issuing a START con-
followed by a series of nine SCL pulses. The MAX9867 dition. A START condition is a high-to-low transition on
transmits data on SDA in sync with the master-generated SDA with SCL high. A STOP condition is a low-to-high
SCL pulses. The master acknowledges receipt of each transition on SDA while SCL is high (Figure 10). A START
byte of data. Each read sequence is framed by a START condition from the master signals the beginning of a
or REPEATED START condition, a not acknowledge, and transmission to the MAX9867. The master terminates
a STOP condition. SDA operates as both an input and an transmission, and frees the bus, by issuing a STOP con-
open-drain output. A pullup resistor, typically greater dition. The bus remains active if a REPEATED START
than 500Ω is required on SDA. SCL operates only as an condition is generated instead of a STOP condition.
input. A pullup resistor, typically greater than 500Ω, is
SDA
tSU, STA tBUF

tSU, DAT tHD, STA
tLOW tSP
tHD, DAT tSU, STO
SCL tHIGH
tHD, STA
tR tF
START CONDITION REPEATED START CONDITION STOP START

CONDITION CONDITION
Figure 9. 2-Wire Interface Timing Diagram
S Sr P
SCL
SDA
Figure 10. START, STOP, and REPEATED START Conditions
46 ______________________________________________________________________________________
Early STOP Conditions down SDA during the entire master-generated 9th clock
MAX9867
The MAX9867 recognizes a STOP condition at any pulse if the previous byte is successfully received.
point during data transmission except if the STOP con- Monitoring ACK allows for detection of unsuccessful
dition occurs in the same high pulse as a START condi- data transfers. An unsuccessful data transfer occurs if
tion. For proper operation, do not send a STOP a receiving device is busy or if a system fault has
condition during the same SCL high pulse as the occurred. In the event of an unsuccessful data transfer,
START condition. the bus master retries communication. The master pulls
down SDA during the 9th clock cycle to acknowledge
Slave Address receipt of data when the MAX9867 is in read mode. An
The slave address is defined as the 7 most significant acknowledge is sent by the master after each read byte
bits (MSBs) followed by the read/write bit. For the to allow data transfer to continue. A not acknowledge is
MAX9867, the 7 most significant bits are 0011000. sent when the master reads the final byte of data from
Setting the read/write bit to 1 (slave address = 0x31) the MAX9867, followed by a STOP condition.
configures the MAX9867 for read mode. Setting the
read/write bit to 0 (slave address = 0x30) configures Write Data Format
the MAX9867 for write mode. The address is the first A write to the MAX9867 includes transmission of a
byte of information sent to the MAX9867 after the START condition, the slave address with the R/W bit set
START condition. to 0, 1 byte of data to configure the internal register
address pointer, 1 or more bytes of data, and a STOP
Acknowledge condition. Figure 12 illustrates the proper frame format
The acknowledge bit (ACK) is a clocked 9th bit that the for writing 1 byte of data to the MAX9867. Figure 13
MAX9867 uses to handshake receipt each byte of data illustrates the frame format for writing n bytes of data to
when in write mode (see Figure 11). The MAX9867 pulls the MAX9867.
CLOCK PULSE FOR

ACKNOWLEDGMENT
START
CONDITION
SCL 1 2 9
NOT ACKNOWLEDGE
SDA
ACKNOWLEDGE
Figure 11. Acknowledge
ACKNOWLEDGE FROM MAX9867
B7 B6 B5 B4 B3 B2 B1 B0
ACKNOWLEDGE FROM MAX9867 ACKNOWLEDGE FROM MAX9867
S SLAVE ADDRESS 0 A REGISTER ADDRESS A DATA BYTE A P
R/W 1 BYTE
AUTOINCREMENT INTERNAL
REGISTER ADDRESS POINTER
Figure 12. Writing 1 Byte of Data to the MAX9867
______________________________________________________________________________________ 47
The slave address with the R/W bit set to 0 indicates The first byte transmitted from the MAX9867 is the con-
MAX9867
that the master intends to write data to the MAX9867. tent of register 0x00. Transmitted data is valid on the
The MAX9867 acknowledges receipt of the address rising edge of SCL. The address pointer autoincre-
byte during the master-generated 9th SCL pulse. ments after each read data byte. This autoincrement
The second byte transmitted from the master config- feature allows all registers to be read sequentially within
ures the MAX9867’s internal register address pointer. one continuous frame. A STOP condition can be issued
The pointer tells the MAX9867 where to write the next after any number of read data bytes. If a STOP condi-
byte of data. An acknowledge pulse is sent by the tion is issued followed by another read operation, the
MAX9867 upon receipt of the address pointer data. first data byte to be read is from register 0x00.
The third byte sent to the MAX9867 contains the data The address pointer can be preset to a specific register
that is written to the chosen register. An acknowledge before a read command is issued. The master presets
pulse from the MAX9867 signals receipt of the data byte. the address pointer by first sending the MAX9867’s
The address pointer autoincrements to the next register slave address with the R/W bit set to 0 followed by the
address after each received data byte. This autoincre- register address. A REPEATED START condition is then
ment feature allows a master to write to sequential regis- sent followed by the slave address with the R/W bit set
ters within one continuous frame. Figure 13 illustrates to 1. The MAX9867 then transmits the contents of the
how to write to multiple registers with one frame. The specified register. The address pointer autoincrements
master signals the end of transmission by issuing a after transmitting the first byte.
STOP condition. Register addresses greater than 0x17 The master acknowledges receipt of each read byte
are reserved. Do not write to these addresses. during the acknowledge clock pulse. The master must
acknowledge all correctly received bytes except the
Read Data Format last byte. The final byte must be followed by a not
Send the slave address with the R/W bit set to 1 to initi- acknowledge from the master and then a STOP condi-
ate a read operation. The MAX9867 acknowledges tion. Figure 14 illustrates the frame format for reading 1
receipt of its slave address by pulling SDA low during byte from the MAX9867. Figure 15 illustrates the frame
the 9th SCL clock pulse. A START command followed format for reading multiple bytes from the MAX9867.
by a read command resets the address pointer to reg-
ister 0x00.
B7 B6 B5 B4 B3 B2 B1 B0 B7 B6 B5 B4 B3 B2 B1 B0
S SLAVE ADDRESS 0 A REGISTER ADDRESS A DATA BYTE 1 A DATA BYTE n A P
R/W 1 BYTE 1 BYTE
Figure 13. Writing n Bytes of Data to the MAX9867
NOT ACKNOWLEDGE FROM MASTER

ACKNOWLEDGE FROM MAX9867 ACKNOWLEDGE FROM MAX9867 ACKNOWLEDGE FROM MAX9867
S SLAVE ADDRESS 0 A REGISTER ADDRESS A Sr SLAVE ADDRESS 1 A DATA BYTE A P
R/W REPEATED START R/W 1 BYTE
Figure 14. Reading 1 Byte of Data from the MAX9867
48 ______________________________________________________________________________________
MAX9867
ACKNOWLEDGE FROM MAX9867 ACKNOWLEDGE FROM MAX9867 ACKNOWLEDGE FROM MAX9867
S SLAVE ADDRESS 0 A REGISTER ADDRESS A Sr SLAVE ADDRESS 1 A DATA BYTE A P
R/W REPEATED START R/W 1 BYTE
Figure 15. Reading n Bytes of Data from the MAX9867
Applications Information Connect all digital I/O termination to the ground plane
with minimum path length to DGND. Bypass DVDD and
Proper layout and grounding are essential for optimum
DVDDIO directly to DGND.
performance. When designing a PCB for the MAX9867,
partition the circuitry so that the analog sections of the Route microphone signals from the microphone to the
MAX9867 are separated from the digital sections. This MAX9867 as a differential pair, ensuring that the posi-
ensures that the analog audio traces are not routed tive and negative signals follow the same path as close-
near digital traces. ly as possible with equal trace length. When using
single-ended microphones or other single-ended audio
Use a large continuous ground plane on a dedicated
sources, ground the negative microphone input as near
layer of the PCB to minimize loop areas. Connect
as possible to the audio source and then treat the posi-
AGND and DGND directly to the ground plane using
tive and negative traces as differential pairs.
the shortest trace length possible. Proper grounding
improves audio performance, minimizes crosstalk The MAX9867 TQFN package features an exposed
between channels, and prevents any digital noise from thermal pad on its underside. Connect the exposed
coupling into the analog audio signals. thermal pad to AGND.
Ground the bypass capacitors on MICBIAS, REG, An evaluation kit (EV Kit) is available to provide an
PREG, and REF directly to the ground plane with mini- example layout for the MAX9867. The EV kit allows
mum trace length. Also be sure to minimize the path quick setup of the MAX9867 and includes easy-to-use
length to AGND. Bypass AVDD directly to AGND. software, allowing all internal registers to be controlled.
______________________________________________________________________________________ 49
Functional Diagram/Typical Operating Circuit
MAX9867
1.7V–3.6V 1.8V 1.8V 1.8V

SYSTEM
TO PROCESSOR CLOCK TO PROCESSOR 1µF
1µF 1µF 1µF 1µF
26 4 3 2 31 30 29 28 27 32 5 7 23
(E1) (C3) (A3) (B3) (B2) (B1) (C1) (C2) (D1) (A1) (A4) (A5) (E2)
2.2µF 6 DVDDIO IRQ SDA SCL MCLK BCLK LRCLK SDIN SDOUT DVDD AVDD PREG PVDD
(B4) REF
REF
1µF 8 CLOCK DIGITAL AUDIO LINEAR
(B5) REG I2C
GEN INTERFACE REG
VCM PREG
1µF 10 DVST:
(B6) MICBIAS DSTS 0dB TO -60dB
MIX
MAX9867
2.2kΩ PALEN: PGAML:

0.22µF 12 MICLP/
0/20/30dB +20dB TO 0dB AVL: DACG: DACA: VOLL:
(C6) DIGMICDATA MXINL +3dB TO -12dB 0/6/12/18dB 0dB TO -15dB +6dB TO -84dB 22
DIGITAL LOUTP (E3)
DIGITAL
MIX
MIX
ADCL DACL
FILTERING FILTERING
MIX
11 MICLN/
0.22µF (C5) DIGMICCLK
2.2kΩ DMONO LOUTN 21
(D2)
DACG: DACA: VOLR:
0/6/12/18dB 0dB TO -15dB +6dB TO -84dB 19
ROUTP (D3)
DIGITAL
DACR
MIX
FILTERING
2.2kΩ PAREN: PGAMR:
0.22µF 13
0/20/30dB +20dB TO 0dB AVR: ROUTN 20
(C4) MICRP
MXINR +3dB TO -12dB (E4)
DIGITAL
MIX
ADCR
14 MICRN FILTERING
0.22µF (D6)
2.2kΩ
LIGL: VOLL, LVOLFIX:

15 +24dB TO -6dB +6dB TO -84dB
0.47µF JACKSNS/ 17
(D5) LINL JACK AUX (D4)
DETECT
LIGR: VOLR, LVOLFIX:

16 +24dB TO -6dB +6dB TO -84dB
0.47µF
(E6) LINR
DGND AGND PGND

1 9 18
(A2) (A6) (E5)
() WLP PACKAGE
50 ______________________________________________________________________________________
Pin Configurations
MAX9867
TOP VIEW
JACKSNS/AUX
(BUMP SIDE DOWN)
MAX9867
ROUTN
LOUTN
ROUTP
LOUTP
TOP VIEW
PGND
PVDD
N.C.
1 2 3 4 5 6
24 23 22 21 20 19 18 17
DVDD DGND SDA AVDD PREG AGND
N.C. 25 16 LINR
A
DVDDIO 26 15 LINL
SDOUT 27 14 MICRN BCLK MCLK SCL REF REG MICBIAS

B
SDIN 28 13 MICRP
MAX9867
LRCLK 29 12 MICLP/DIGMICDATA LRCLK SDIN IRQ MICRP MICLN MICLP
BCLK 30 11 MICLN/DIGMICCLK C
MCLK 31 + *EP 10 MICBIAS SDOUT LOUTN ROUTP JACKSNS LINL MICRN

DVDD 32 9 AGND D
1 2 3 4 5 6 7 8
DVDDIO PVDD LOUTP ROUTN PGND LINR
DGND
SCL
SDA
IRQ
AVDD
REF
PREG
REG
THIN QFN
(5mm × 5mm)
*EP = EXPOSED PAD WLP
(2.2mm x 2.7mm)
______________________________________________________________________________________ 51
Package Information
MAX9867
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the
package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the
package regardless of RoHS status.
PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO.

30 WLP W302A2+3 21-0211 —
32 TQFN-EP T3255+4 21-0140 90-0121
52 ______________________________________________________________________________________
Package Information (continued)
MAX9867
QFN THIN.EPS
______________________________________________________________________________________ 53
Package Information (continued)
MAX9867
54 ______________________________________________________________________________________
Revision History
MAX9867
REVISION REVISION PAGES
DESCRIPTION
NUMBER DATE CHANGED
0 4/09 Initial release —
Added lead temperature and soldering temperatures, updated VOS
1 5/10 2, 8
specification
2 6/10 Corrected error in TOC20 15
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 55
© 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

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19-4573; Rev 2; 6/10

Ultra-Low Power Stereo Audio Codec

LEFT MIC AMP CONTROL

________________________________________________________________ Maxim Integrated Products 1

(Voltages with respect to AGND.) Continuous Power Dissipation (TA = +70°C)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

MCLK = 12.288MHz, fS = 48kHz, 0dBFS,

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

DVFLT = 0x2 0.0312

DVFLT = 0x4 0.0625

DVFLT = 0x2 0.0156

DVFLT = 0x4 0.0312

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

f = 1kHz, 0dBFS, HP fS = 8kHz 1.2

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

AVFLT = 0x2 0.0312

AVFLT = 0x4 0.0625

AVFLT = 0x2 0.0156

AVFLT = 0x4 0.0312

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Allowable LRCLK period change from

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

-70 -70 -70

-40 -40 -40

MCLK = 12.288MHz MCLK = 12.288MHz MCLK = 13MHz

-40 -40 -40

-70 -70 -70

-40 -40 -40

-70 -70 -70

MCLK = 13MHz LINE IN PREAMP = +18dB LINE IN PREAMP = 0dB

TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE

POWER OUT (mW)

TOTAL HARMONIC DISTORTION + NOISE

MCLK = 12.288MHz MCLK = 12.288MHz MCLK = 13MHz

POWER OUT (mW)

MCLK = 13MHz MCLK = 13MHz VRIPPLE = 100mVP-P

-40 -40 -40

-70 -70 -70

-90 -90 -90

Typical Operating Characteristics (continued)

POWER-SUPPLY REJECTION RATIO POWER-SUPPLY REJECTION RATIO FFT, DAC TO HEADPHONE,

-90 -90 -140

FFT, DAC TO HEADPHONE, FFT, DAC TO HEADPHONE, FFT, DAC TO HEADPHONE,

-20 -20 -20

-40 -40 -40

-60 -60 -60

-80 -80 -80

-100 -100 -100

-120 -120 -120

-140 -140 -140

FFT, DAC TO HEADPHONE, FFT, DAC TO HEADPHONE, FFT, DAC TO HEADPHONE,

PLL MODE PLL MODE PLL MODE

-20 -20 -20

-40 -40 -40

-60 -60 -60

-80 -80 -80

-100 -100 -100

-120 -120 -120

-140 -140 -140