Solid-State Electronics 52 (2008) 1291–1296

Contents lists available at ScienceDirect

Solid-State Electronics
journal homepage: www.elsevier.com/locate/sse

Multi-gate devices for the 32 nm technology node and beyond

N. Collaert a,*, A. De Keersgieter a, A. Dixit b, I. Ferain b, L.-S. Lai c, D. Lenoble d, A. Mercha a, A. Nackaerts a,
B.J. Pawlak e, R. Rooyackers a, T. Schulz f, K.T. San g, N.J. Son h, M.J.H. Van Dal e, P. Verheyen a, K. von Arnim f,
L. Witters a, K. De Meyer b, S. Biesemans a, M. Jurczak a
a
IMEC, Kapeldreef 75, Heverlee, Belgium
b
K.U.Leuven, ESAT-INSYS, Kasteelpark Arenberg 10, B-3001 Heverlee, Belgium
c
TSMC, Assignee to IMEC, Belgium
d
STMicroelectronics, Assignee to IMEC, Belgium
e
NXP Semiconductors, Kapeldreef 75, B-3001 Leuven, Belgium
f
Infineon Technologies Leuven, Kapeldreef 75, 3001 Leuven, Belgium
g
Texas Instruments Inc., 13560 N. Central Expressway, Dallas, TX 75243, USA
h
Samsung Electronics, Assignee to IMEC, Belgium

a r t i c l e i n f o a b s t r a c t

Article history: Due to the limited control of the short channel effects, the high junction leakage caused by band-to-band
Available online 12 May 2008 tunneling and the dramatically increased VT statistical fluctuations, the scaling of planar bulk MOSFETs
becomes more and more problematic with every technology node. The ITRS roadmap predicts that from
The review of this paper was arranged by
the 32 nm technology node on, planar bulk devices will not be able to meet the stringent leakage require-
Jurriaan Schmitz
ments anymore and that multi-gate devices will be required. In this paper, the suitability of FinFET-based
multi-gate devices for the 32 nm technology and beyond will be discussed. Apart from the benefits, some
technological challenges will be addressed.
Ó 2008 Elsevier Ltd. All rights reserved.

1. Introduction
FinFET-based multi-gate (MuGFET) devices have been the topic
of many publications over the last decade [1–3]. The benefits of
these devices are very clear: reduced short channel effects, leakage
currents, VT dopant fluctuations and possible higher mobility due
to the undoped channels. Recently [4] it has also been demon-
strated that these devices can be used for large-scale integration
and that digital MuGFET circuits can show superior performance
over planar bulk devices. In the first section of this paper, we will
briefly discuss the benefits of using MuGFET from the intrinsic
transistor performance point of view. The main part of the paper
will describe the technological challenges. The last part will briefly
give an overview of the performance of circuits fabricated in MuG-
FET technology.
as conducting channels. Due to the fact that the gate is wrapped
around a tiny fin, the electrostatic control of the gate on the chan-
nel is enhanced leading to better immunity against short channel
effects (SCE).
The fin width is therefore a crucial parameter in the design of
MuGFET devices. Fig. 2 shows that scaling the fin width decreases
the drain induced barrier lowering (DIBL) for the short channel de-
vices. The width of the fin is determined by the required controllabil-
ity of the SCE and hence by the target gate length (LGATE). Depending
on the kind of MuGFET structure under investigation (Omega-gate,
Pi-gate, Tri-gate. . .) the gate length LGATE to fin width WFIN ratio
can vary from 1.5 to 2 [5]. As shown in [6] and in Fig. 3, good scala-
bility down to 25–30 nm LGATE can be achieved. The results clearly
show that the fin width needs to be scaled down below 10 nm,
which is a challenge as will be discussed in the next paragraph.

2. Benefits of MuGFET devices 3. Technological challenges

Fig. 1 shows a SEM view of a typical MuGFET transistor. The de-
vice consists of a channel formed in a Si fin and a self-aligned gate
wrapped around the thin Si fin. In this device, the current flow is
still horizontal while the sidewalls of the dry-etched Si fin are used
* Corresponding author. Tel.: +32 16 28 16 41; fax: +32 16 28 18 44.
E-mail address: collaert@imec.be (N. Collaert).
MuGFET fabrication follows a quite conventional Si processing.
However, specific process steps will require additional restrictions,
e.g. fin critical dimension (CD) control. Next to that, new process
modules such as selective epitaxial growth of Si (SEG) will be
needed.
In the next part of this section we will present the technological
challenges related to the processing of MuGFET devices. Topics like

0038-1101/$ - see front matter Ó 2008 Elsevier Ltd. All rights reserved.
doi:10.1016/j.sse.2008.04.018
1292 N. Collaert et al. / Solid-State Electronics 52 (2008) 1291–1296

0.5
nMOS
0.4
0.3

0.2
Wfin = 17 nm
0.1

VT_sat (V)
Wfin = 12 nm
0 Wfin = 8 nm
Wfin = 6 nm
-0.1

-0.2
-0.3

-0.4 pMOS
-0.5
20 40 60 80 100
Lg (nm)

Fig. 3. Saturated threshold voltage (jVDSj = 1 V) as function of gate length for devices
with different fin widths demonstrating the excellent scalability of these devices
down to LG = 25–30 nm.

Fig. 1. SEM view of a typical MuGFET device, showing several fins in parallel and
the gate running over the fins. ever, this assumes that WFIN variation is the main cause of VT var-
iability. In [6] it is shown that for short gates, VT variability is
mainly dominated by LGATE variation. This is again shown in
0.4 Fig. 4 where the VT_lin dependency upon fin width and LGATE is
Wfin = 20nm shown. For short (<70 nm) gates, the WFIN dependency upon VT_lin
0.35 is found to be surprisingly weak. For longer gates, a strong VT_lin in-
Wfin = 12nm crease is observed, especially for narrow fins. This increase can be
0.3
Wfin = 30nm attributed to fin width fluctuations, as is confirmed by Monte Carlo
DIBL [V/V]

0.25 simulations accounting for quantum confinement. Only for long

gates and narrow fins VT is greatly affected by the within-die fin
0.2
width variability.
0.15 Another fin fabrication technique is the spacer defined pattern-
ing technique that can provide double and even quadruple fin den-
0.1 sity with less stringent lithography requirements [8]. In this case, a
0.05 dummy pattern is defined. Then spacers are formed next to
the dummy pattern, which will eventually define the fin spacing.
0 The dummy areas are removed selectively towards the spacers
0.01 0.1 1
Lgate [um]
0
Fig. 2. DIBL as function of the gate length for different fin widths; nMOS devices are
shown. Lg

-0.1
device scaling, work function tuning, access resistance and strain
30 nm
engineering will be discussed.
-0.2
35 nm
3.1. Fin width and density scaling
VT_lin (V)

40 nm
One of the challenges in MuGFET integration is the formation of -0.3
50 nm
5–10 nm wide fins, required to fully benefit from the short channel
70 nm
control of multi-gate devices. The fins are typically defined by opti-
cal lithography and dry etch. Depending on the device layout -0.4
110 nm
(standalone fins, single fins, fins with large source and drain pads)
optimization of the lithography settings is needed in order to con- Monte-Carlo
-0.5 simulation for
trol the fin width [7]. This requires the development of model- 160 nm
based optical proximity correction (OPC) which is very specific 10 µm Lg = 110 nm
for MuGFET. Assuming a target fin width of 10 nm and allowing 410 nm
-0.6
a maximum variation in fin width of 10% in order to keep the max- 0 5 10 15 20
imum VT shift at LG = 20 nm smaller than 70 mV, this would mean Wfin (nm)
that at litho level only a litho CD variation of 1.5% can be allowed
taking into account a specific and constant etch bias (in this case of Fig. 4. VT_lin vs. WFIN for various LGATE; only pMOS is shown. Dashed line: simulation
60 nm). This is a very stringent requirement at litho level. How- (LGATE = 110 nm) including WFIN fluctuations.
 N. Collaert et al. / Solid-State Electronics 52 (2008) 1291–1296
and the spacers are used as a hardmask during the formation of the
fins.
Fig. 5a and b show that the spacer technology provides a more
uniform pattern size and much higher device density than the cur-
rent optical lithography. Devices and circuits with a fin pitch as
small as 50 nm have been demonstrated.
Apart from the ability to fabricate these narrow fins, metrology
tools have to guarantee a high enough accuracy to measure those
features. For example, a 5 nm accuracy error would correspond
to a 30% change in CD when dealing with a 15 nm feature, which
is unacceptable.
Next to that, line width roughness (LWR) and sidewall rough-
ness have a direct impact on device performance. A robust metrol-
ogy to characterize these elements in both development and
production is required [9].
3.2. Workfunction engineering
Threshold voltage tuning in planar devices is achieved by
increasing or decreasing the channel implant, using halo implanta-
tions for the short gate lengths, scaling the gate dielectric or using a
metal gate to tune the work function. In the case of MuGFET de-
vices, the full depletion of the fin makes threshold voltage setting
and tuning with implantation very difficult [10]. Whereas the fin
doping can easily tune the VT for wide fin devices, the impact of
the implantation is dramatically reduced for narrow fin devices
(Fig. 6). The threshold voltage for devices with WFIN = 35 nm lies
around zero and seems to become insensitive to fin doping. Next
to that, introducing a large amount of fin doping makes the device
vulnerable to variations in fin width. Therefore work function tun-
ing with metal gate is needed for setting the VT in MuGFET devices.
Integration of a single metal gate is the preferred solution when
considering process complexity. However, a single mid-gap metal
like TiN or TaN on planar bulk devices results in either high thresh-
old voltages or poor short channel control. In MuGFET the mid-gap
work function of TiN leads to symmetric threshold voltages for
nMOS and pMOS [10]. However, setting the VT is not enough. Cir-
cuit operation needs different flavors of VT: low, medium, high
VT. Different from planar bulk devices, MuGFETs need less shifting
from mid-gap work functions to reach low VT targets. Different
techniques are under investigation for VT tuning: implantation into
the metal gate, TiN thickness variation [11] and recently also the
use of dielectric capping layers. The boundary condition is that
these techniques, typically also used in planar bulk, need to be
compatible with the high topography in MuGFETs. In [12] NMOS
Fig. 5. Tilted SEM view of MuGFET devices where the fins have been defined by spacer defined patterning; a fin pitch of 50 nm has been demonstrated; in (a) devices with
standalone fins are shown and in (b) devices with large source and drain pads.
1293
0.6
0.5
0.4
0.3
VTlin [V]
0.2
increased fin doping
0.1
0
no fin doping
-0.1
-0.2
0.01 0.1 1 10
Wfin [um]
Fig. 6. Linear threshold voltage as function of fin width; nMOS device with poly/
SiON gate stack and LGATE = 10 lm is shown.
MuGFET devices with a VT of 0.33 V through As implantation into
TiN were demonstrated. This method allows for devices with mul-
tiple VT’s through just one As implantation step into 10 nm TiN. For
pMOS, Al implantation can be considered. It is an integration-
friendly method but it is not without issues: the most critical steps
are the fine-tuning of the implantation and annealing conditions in
order to keep the implantation damage away from the gate dielec-
tric. In the case of MuGFET, this also means that conformal doping
is needed to implant both top and sidewalls adequately, similar to
the extension doping that will be discussed in the next section.
Recently the use of dielectric capping layers became very pop-
ular. Typically Dy- and La-based capping layers are used for nMOS
and Al-based layers for pMOS. The first nMOS MuGFET devices
with TiN/Dy2O3/SiO2 were demonstrated in [13]. The obtained VT
shift for nMOS of 120 mV to lower values (Fig. 5) is very promising.
The work demonstrated that bi-directional mixing occurs between
the Dy-capping and the host dielectric leading to the formation of
Dy-silicates. It was found that the optimum Dy2O3:SiO2 ratio is 1:2.
A thicker Dy2O3 layer will degrade the inversion Tox. Next to that, it
was found that thicker Dy-layers have some issues related to the
gate stack etch: a larger gate undercut was found for thicker layers
thereby degrading the short channel characteristics as can be seen
in Fig. 7a for the 1.5 nm Dy2O3 layer.
1294 N. Collaert et al. / Solid-State Electronics 52 (2008) 1291–1296

a 0.5 b 1.E+09
nFET Poly/TiN 10 years
Weff=25nm
T=125°C
Vds=50mV 1.E+08
0.4
PBTI

120mV 1.E+07
VT,Lin (V)

Lifetime (s)
0.3
1.E+06
2.0nm SiO2

0.2 w/o Dy2O3 1.E+05

NBTI
1.0nm Dy2O3
1.5nm Dy2O3 Poly/TiN
1.E+04
0.1 w/o Dy2O3
0.01 0.1 1 10 1nm Dy2O3/2nm SiO2
Lg (um) 1.E+03
1 10
Eox (MV/cm)

Fig. 7. (a) Linear threshold voltage VT lin as function of gate length LGATE for nMOS MuGFET devices with WFIN = 25 nm; the devices with Dy2O3 capping (1.5 nm and 1 nm) are
compared to the reference devices; (b) BTI analysis comparing devices without Dy2O3 capping and with a 1 nm Dy2O3 capping (on a 2 nm SiO2 host dielectric).

A thinner SiO2 host dielectric degrades the interface quality 70

(mobility and sub-threshold slope) significantly. A thinner Dy2O3
n-type
Estimated NiSi thickness [nm]

layer will lead to a reduction in VFB shift. As reliability is one of 60

the major concerns, bias temperature instability (BTI) measure- p-type
ments were done and the results are shown in Fig. 7b. For both 50
nMOS (PBTI) and pMOS (NBTI), no degradation is seen when the
optimal Dy2O3:SiO2 ratio (1:2) is used. 40
Although the method is more complicated from an integration
point of view since different capping layers are needed on nMOS 30
and pMOS, the use of capping layers is a viable option for setting
and tuning the VT in both MuGFET and bulk devices. 20

3.3. Access resistance 10

For the 32 nm technology node, fin widths smaller than 10 nm 0

will be needed to maintain good short channel behavior as was dis- 0 20 40 60 80
cussed in Section 2. Just like in fully depleted SOI (FD SOI) where
Wfin [nm]
ultra-thin Si films are needed to obtain good electrostatic control,
the access resistance is very high in narrow fin devices [14]. The Fig. 8. Estimated NiSi thickness as function of WFIN for n-type and p-type doped
contact resistance is typically reduced by the implementation of source/drain areas; HFIN = 65 nm and the thickness has been estimated from resis-
selective epitaxial growth of Si (SEG) on the source and drain areas. tance measurements.

Providing more Si area increases the contact area and at the same
time reduces the over-silicidation that occurs in aggressively
scaled fins. The latter problem is more severe for nMOS than for
pMOS since p-type dopants like B typically retard the Ni-silicida-
tion. This is also shown in Fig. 8 where the estimated NiSi thickness
is shown as function of WFIN. The NiSi thickness on n-type areas is
overall much thicker than on p-type areas. Next to that, a dramatic
increase in thickness occurs when scaling the WFIN below 35 nm,
leading to a full silicidation of the fin. The multi-directional con-
sumption of Si during the silicidation and the limited amount of
available Si are the main causes for this problem. As the Ni is the
diffusing species, it will look for available Si to form NiSi. Next to
that, defects remaining from the extension and highly doped
source/drain implants and recrystallization can lead to local NiSi-
piping towards the channel.
The issue of over-silicidation is again shown in Fig. 9a and b
where the cross-sections of a wide and narrow fin device are com-
pared after Ni-silicidation. Fig. 9b clearly shows the increase in NiSi
on the source and drain areas and the encroachment of the silicide
under the spacers, towards the channel.
Over-silicidation of the narrows fins also leads to excessive gate
induced drain leakage (GIDL) [15]. When silicide encroachment to-
wards the channel occurs, the Ni-silicide can overrun the lowly
doped extensions. In that case, a typical Schottky barrier FET
behavior is seen and this leads to an increased off-state leakage.
Again the use of SEG can reduce the GIDL significantly.
Although the use of SEG can clearly decrease the RSD in thin
body devices, it is not enough to meet the ITRS requirements for
the 32 nm technology node [16]. Other contributors like the
spreading and sheet resistance will need to be addressed in order
to meet the ITRS specifications. In [17] it was shown that the root
cause for the high access resistance in aggressively scaled fins is re-
lated to the full amorphization of the fins during source/drain im-
plant and its problematic recrystallization during the high
 N. Collaert et al. / Solid-State Electronics 52 (2008) 1291–1296 1295

Fig. 9. Cross-section SEM of (a) a wide fin device (W = 1 lm) showing the NiSi on source and drain and (b) a narrow fin device (WFIN = 50 nm); in the latter case the source/
drain NiSi is much thicker, almost reaching the interface between Si film and buried oxide, and moreover there is NiSi encroachment towards the channel.

Fig. 11. Tilted SEM view of a 0.274 lm2 6T SRAM cell after fin patterning, gate etch
and spacer formation.
Fig. 10. X-TEM of a wide and narrow fin after implantation and rapid thermal
annealing (RTA) at 1050 °C showing the poor fin crystallinity for the narrow fin.

mobility. Moreover, the fin patterning by reactive ion etch (RIE)

temperature anneal. In sub-20 nm wide fins, surface proximity
suppresses crystal regrowth, and promotes the formation of twin
boundary defects in the implanted region (Fig. 10, left). If solid
phase epitaxy (SPE) is significantly retarded, random nucleation
and growth (RNG) may take place and part of the fin transforms
into polysilicon (Fig. 10, right). Therefore, alternative implantation
techniques like plasma doping and vapor phase doping can bring
some extra benefits in forming conformal junctions with limited
amorphization of the fins [18], but so far these techniques are
not mature enough.
3.4. Strain engineering
In order to achieve the stringent requirements for the drive cur-
rent for the 32 nm technology node and beyond, strain engineering
techniques will be needed. Especially the weaker nMOS device de-
mands some amount of strain engineering for higher channel
leads to increased sidewall roughness thereby reducing the chan-
nel mobility.
Surface smoothening by H2 anneal [19] has been demonstrated
to increase the mobility. However, the impact of the H2 anneal is
layout dependent and careful optimization of the process condi-
tions is needed.
One of the most straightforward and efficient ways of introduc-
ing strain into both planar and multi-gate devices is the use of
intrinsically strained SiN layers. In [20] and [21] it has been dem-
onstrated that the nMOS performance can be largely improved by
the use of tensile strained contact etch stop layers (CESL). Simula-
tions also show that scaling the fin width and increasing the fin
height will lead to higher top-down and longitudinal stress compo-
nents which are beneficial for nMOS mobility. For pMOS, only a
moderate improvement is seen with compressively strained CESL
(cCESL). It has been demonstrated that tensile CESL can also be
used on pMOS without degradation of the current. The latter gives
1296 N. Collaert et al. / Solid-State Electronics 52 (2008) 1291–1296
the opportunity to go for a more simple process scheme where a
single tensile CESL can be used to improve nMOS and which has
no negative impact on pMOS.
Similar to bulk strain engineering techniques, the impact of
CESL might be strongly reduced if the fin and poly pitch are scaled
down.
4. Circuit performance
The Shallow Trench Isolation (STI) free isolation process for
MuGFET devices on SOI allows fabricating high density SRAMs
(Fig. 11). SRAM cells with dimensions down to 0.314 lm2 [22]
and even 0.274 lm2 [23] have been demonstrated. The latter cell,
having a TaN based gate stack, showed a high static noise margin
of 216 mV at 1 V with devices having a LGATE = 37 nm. At the same
time, improved OPC for CD control and integration of SRAM and lo-
gic circuits was studied.
In [4] a MuGFET inverter delay of 13.9 ps at VDD = 1.0 V and
Ioff = 1.9 nA/stage has been demonstrated. Furthermore, the excel-
lent stack performance of MuGFET circuits results in both better
circuit performance and smaller area when using logic gates with
higher fan-in. A low-power product-typical pipelined critical path
with low standby current and good low-operating power perfor-
mance demonstrates the potential of MuGFETs for large-scale
integration.
Due to their good short channel control, MuGFET devices are
also beneficial for RF/analog circuits [24]. The undoped channel
and the absence of poly depletion (due to the metal gate) lead to
better matching properties [25]. However, the low sidewall mobil-
ity and the high level of parasitics (high RSD,. . .) associated to the
3D nature of the MuGFETs affect their speed considerably and opti-
mization is needed.
5. Conclusions
The MuGFET transistor is the most widely studied and known
multi-gate architecture that has the potential to be scaled beyond
the 32 nm technology node. In this paper we have addressed the
benefits of these devices and a number of integration challenges.
Next to that, we have briefly discussed the potential of these de-
vices for large-scale integration.
Acknowledgements
The authors would like to thank the people working in the litho,
etch and SEG development groups, the material characterization
group, the IMEC pilot line and measurements labs.
This research is supported by the IMEC EMERALD IIAP program
and the European Commission’s Information Society Technologies
Program under PULLNANO project Contract No. IST-026828.
References
[1] Hisamoto D et al. FinFet – a self-aligned double-gate MOSFET scalable to
20 nm. IEEE Trans Electron Dev 2000;47(12):2320–5.
[2] Kavalieros J, Doyle B, Datta S, Dewey G, Doczy M, Jin B, et al. Tri-gate transistor
architecture with high-k gate dielectrics, metal gates and strain engineering.
VLSI Technol Symp 2006:50–1.
[3] Park J-T, Colinge J-P, Diaz CH. Pi-gate SOI MOSFET. IEEE Electron Dev Lett
2001;22(8):405.
[4] von Arnim K et al. A low-power multi-gate FET CMOS technology with 13.9 ps
inverter delay large-scale integrated high performance digital circuits and
SRAM. VLSI Technol Symp 2007:106–7.
[5] Pei G et al. FinFET design considerations based on 3-D simulation and
analytical modeling. IEEE Trans Electron Dev 2002;49(8):1411–9.
[6] Van Dal MJH et al. Highly manufacturable FinFETs with sub-10 nm fin width
and high aspect ratio fabricated with immersion lithography. VLSI Technol
Symp 2007:110–1.
[7] Ercken M, Delvaux C, Baerts C, Locorotondo S, Degroote B, Wiaux V, et al.
Challenges in patterning 45 nm node multiple-gate devices and SRAM cells. In:
Proceedings 41st interface symposium.
[8] Rooyackers R et al. Doubling or quadrupling MuGFET fin integration scheme
with higher pattern fidelity, lower CD variation and higher layout efficienty.
IEDM Tech Digest 2006:993–6.
[9] Lorusso GF et al. Comprehensive approach to MuGFET metrology. In:
Metrology, inspection, and process control for microlithography XX, Proc
SPIE 6152, 615219, 2006.
[10] Collaert N, Demand M, Ferain I, Lisoni J, Singanamalla R, Zimmerman P, et al.
Tall triple-gate devices with TiN/HfO2 gate stack. VLSI Technol Symp 2005:
108–9.
[11] Singanamalla R et al. Jpn J Appl Phys 2007;46(14):L320–2.
[12] Witters L, Son NJ, Ferain I, San T, Singanamalla R, Kerner C, et al. Threshold
voltage modulation in FinFET devices through arsenic ion implantation into
TiN/HfSiON gate stack. SOI Conference 2007:31–2.
[13] Ferain I, Son NJ, Witters L, Collaert N, Onsia B, Kaczer B, et al. Metal gate
technology using a 3 dielectric cap approach for multiple-VT in NMOS FinFETs.
SOI Conference 2007:141–2.
[14] Dixit A, Kottantharayil A, Collaert N, Goodwin M, Jurczak M, De Meyer K.
Analysis of the parasitic source/drain resistance in multiple gate field effect
transistors. IEEE Trans Electron Dev 2005;52(6):1132–40.
[15] Hoffmann T et al. S/D engineering in advanced HfO2/TiN FinFET devices: a view
on GIDL (gate-induced drain leakage) and Schottky barriers S/D leakages.
IEDM Tech Digest 2005:743–6.
[16] ITRS Roadmap, Semiconductor Industry Association. CA: San Jose; 2006.
[17] Duffy R, van Dal MJH, Pawlak BJ, Kaiser M, Weemaes RG, Degroote B, et al.
Solid phase epitaxy versus random nucleation and growth in sub-20 nm wide
fin field-effect transistors. Appl Phys Lett 2007;90:241912.
[18] Lenoble D et al. Enhanced performance of PMOS MUGFET via integration of
conformal plasma-doped source/drain extensions. VLSI Technol Symp 2006:
168–9.
[19] Weize Xiong, Gabriel Gebara, Joyti Zaman, Michael Gostkowski, Billy Nguyen,
Greg Smith, et al. Improvement of FinFET electrical characteristics by
hydrogen annealing. IEEE Electron Dev Lett 2004;25(8):541–3.
[20] Shin K, Chui CO, King T-J. Dual stress capping layer enhancement study for
hybrid orientation FinFET CMOS technology. IEDM Tech Digest 2005:1009–12.
[21] Collaert N, De Keersgieter A, Anil KG, Rooyackers R, Eneman G, Goodwin M,
et al. Performance improvement of tall triple gate devices with strained SiN
layers. IEEE Electron Dev Lett 2005;26(11):820–2.
[22] Nackaerts A et al. A 0.314 lm2 6T-SRAM cell build with tall triple-gate devices
for 45 nm node applications using 0.75NA 193 nm lithography. IEDM Tech
Digest 2004:269–72.
[23] Witters L et al. Integration of tall triple-gate devices with inserted-TaxNy gate
in a 0.274 lm2 6T-SRAM Cell and advanced CMOS logic circuits. VLSI Technol
Symp 2005:106–7.
[24] Subramanian V et al. Device and circuit-level analog performance trade-offs: a
comparative study of planar bulk FETs versus FinFETs. IEDM Tech Digest
2005:898–901.
[25] Gustin C et al. Stochastic matching properties of FinFETs. IEEE Electron Dev
Lett 2006;27(10):846–8.