Bài 1:

1. Cổng logic
-------------------------------------main circuit------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity bai11 is
Port ( InA : in STD_LOGIC;
InB : in STD_LOGIC;
InC : in STD_LOGIC;
InD : in STD_LOGIC;
OutF : out STD_LOGIC);
end bai11;

architecture Behavioral of bai11 is

signal X,Y: std_logic;
begin
X <= InA and InB;
Y <= InC xor InD;
OutF <= X or Y;

end Behavioral;
----------------------------------------------------------------------------------------
--------------------------------------Testbench-----------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb IS
END tb;

ARCHITECTURE behavior OF tb IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT bai11
PORT(
InA : IN std_logic;
InB : IN std_logic;
InC : IN std_logic;
InD : IN std_logic;
OutF : OUT std_logic
);
END COMPONENT;

--Inputs
signal InA : std_logic := '0';
signal InB : std_logic := '0';
signal InC : std_logic := '0';
signal InD : std_logic := '0';

--Outputs
 signal OutF : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: bai11 PORT MAP (
InA => InA,
InB => InB,
InC => InC,
InD => InD,
OutF => OutF
);

-- Clock process definitions

process

begin
InA <= '0';
InB <= '0';
InC <= '0';
InD <= '0';
wait for 20 ns;
InA<= '0';
InB <= '1';
InC <= '1';
InD <= '0';
wait for 20 ns;
InA <= '1';
InB <= '0';
InC <= '1';
InD <= '1';
wait for 10 ns;
InA <= '1';
InB <= '1';
InC <= '0';
InD <= '1';
wait for 20 ns;
InA <= '1';
InB <= '1';
InC <= '1';
InD <= '1';
wait for 20 ns;

end process;
END;

2.Mạch cộng
 a. Mạch bán tổng
-----------------------------main circuit--------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity H_Adder is
Port(
a,b: in std_logic;
sum, carry: out std_logic
);
end H_Adder;

architecture Behavioral of H_Adder is

begin
sum <= a xor b;
carry <= a and b;
end Behavioral;
----------------------------------------------------------------------------------------

-----------------------------TestBench-------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity tb is
-- Port ( );
end tb;
architecture Behavioral_tb of tb is
component H_Adder port(
a,b: in std_logic;
sum, carry: out std_logic
);
end component;
signal a, b, sum, carry: std_logic;
begin
uut: H_Adder
port map( a => a, b => b, sum => sum, carry => carry );
process
begin
a <= '0';
b <= '0';
wait for 20 ns;
a <= '0';
b <= '1';
wait for 30 ns;
a <= '1';
b <= '0';
wait for 10 ns;
a <= '1';
b <= '1';
wait for 15 ns;
end process;
end Behavioral_tb;
  Mạch toàn tổng
 Xây dựng trực tiếp

-----------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity F_Adder is
Port(
a,b,cin: in std_logic;
sum, cout: out std_logic
);
end F_Adder;

architecture Behavioral of F_Adder is

begin
sum <= a xor b xor cin;
cout <= (cin and (a xor b)) or (a and b);
end Behavioral;
----------------------------------------------------------------------------------------

-----------------------------TestBench-------------------------

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY tb IS
END tb;

ARCHITECTURE Behavioral_tb OF tb IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT F_Adder
PORT(
a : IN std_logic;
b : IN std_logic;
cin : IN std_logic;
sum : OUT std_logic;
cout : OUT std_logic
);
END COMPONENT;

signal a, b, sum, cin, cout: std_logic;

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: F_Adder PORT MAP (
a => a, b => b, cin => cin,sum => sum, cout => cout
);

process
begin
a <= '0';
b <= '0';
cin <= '0';
wait for 20 ns;
a <= '0';
b <= '1';
cin<= '1';
wait for 30 ns;
a <= '1';
b <= '0';
cin <= '0';
wait for 10 ns;
a <= '1';
b <= '1';
cin <= '1';
wait for 15 ns;
end process;
end Behavioral_tb;
 Xây dựng dựa trên các bộ bán tổng sử dụng 2 Process
------------------------------2 process----------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity F_Adder is
port (
A, B, Cin : in std_logic;
Sum, Cout : out std_logic
);
end F_Adder;

architecture Behavioral of F_Adder is

signal int1, int2, int3: std_logic;
begin
P1: process (A, B)
begin
int1<= A xor B;
int2<= A and B;
end process;
P2: process (int1, int2, Cin)
begin
Sum <= int1 xor Cin;
int3 <= int1 and Cin;
Cout <= int2 or int3;
end process;
end Behavioral;

---------------------------------------------TestBench---------------------------------

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY tb IS
END tb;

ARCHITECTURE Behavioral_tb OF tb IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT F_Adder
PORT(
A : IN std_logic;
B : IN std_logic;
Cin : IN std_logic;
Sum : OUT std_logic;
Cout : OUT std_logic
);
END COMPONENT;

signal a, b, sum, cin, cout: std_logic;

BEGIN
uut: F_Adder PORT MAP (
A => A,
B => B,
Cin => Cin,
Sum => Sum,
Cout => Cout
);

process
begin
a <= '0';
b <= '0';
cin <= '0';
wait for 20 ns;
a <= '0';
b <= '1';
cin <= '1';
wait for 30 ns;
a <= '1';
b <= '0';
cin <= '0';
wait for 10 ns;
a <= '1';
b<= '1';
cin <= '1';
wait for 15 ns;
end process;
end Behavioral_tb;
---------------------------------------------------------------------------------------
 Xây dựng sử dụng Component
---------------------------Component----------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity half_adder is
port(x,y: in std_logic;
sum, carry: out std_logic
);
end half_adder;

architecture Behavioral_h of half_adder is

begin
sum <= x xor y;
carry <= x and y;
end Behavioral_h;

-----------------------------------main circuit----------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity full_adder is
Port (a,b,cin: in std_logic;
sum, cout: out std_logic
);
end full_adder;

architecture Behavioral of full_adder is

component half_adder port(
x,y: in std_logic;
sum, carry: out std_logic
);
end component;
signal e0, e1, e2, e3: std_logic;
begin
half1: half_adder
port map( x => a, y => b, sum => e0, carry => e1);
half2: half_adder
port map( x => e0, y => cin, sum => e2, carry => e3);
sum <= e2;
cout <= e1 or e3;
end Behavioral;
---------------------------------------------testbench----------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb IS
END tb;

ARCHITECTURE Behavioral_tb OF tb IS
COMPONENT full_adder
PORT(
a : IN std_logic;
b : IN std_logic;
cin : IN std_logic;
sum : OUT std_logic;
cout : OUT std_logic
);
END COMPONENT;
signal a, b, cin, sum, cout: std_logic;

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: full_adder PORT MAP (
a => a,
b => b,
cin => cin,
sum => sum,
cout => cout
);

process
begin
a <= '0';
b <= '0';
cin <= '0';
wait for 20 ns;
a <= '0';
b <= '1';
cin <= '1';
wait for 20 ns;
a <= '1';
b <= '0';
cin <= '1';
wait for 10 ns;
a <= '1';
b <= '1';
cin <= '0';
wait for 20 ns;
a <= '1';
b <= '1';
cin <= '1';
wait for 20 ns;
end process;
end Behavioral_tb;
3. Mạch giải mã địa chỉ, phân kênh, ghép kênh.
c.Mạch giải mã địa chỉ
 Cấu trúc when/else
--------------------------------------------when/else----------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity giaima3to8 is
Port(
input: in std_logic_vector(2 downto 0);
output: out std_logic_vector(7 downto 0)
);
end giaima3to8;

architecture Behavioral of giaima3to8 is

begin
output <= "00000001" when input = "000" else
"00000010" when input = "001" else
"00000100" when input = "010" else
"00001000" when input = "011" else
"00010000" when input = "100" else
"00100000" when input = "101" else
"01000000" when input = "110" else
"10000000";
end Behavioral;

-------------------------------------------testbench cho cả 3 phần----------------------------------------------

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb IS
END tb;

ARCHITECTURE Behavioral_tb OF tb IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT giaima3to8
PORT(
input : IN std_logic_vector(2 downto 0);
output : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
signal input : std_logic_vector (2 downto 0);
 signal output : std_logic_vector(7 downto 0) ;

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: giaima3to8 PORT MAP (
input => input,
output => output
);

process
begin
input <= "000";
wait for 5 ns;
input<= "001";
wait for 20 ns;
input <= "010";
wait for 10 ns;
input <= "011";
wait for 15 ns;
input <= "100";
wait for 20 ns;
input <= "101";
wait for 20 ns;
input <= "110";
wait for 20 ns;
input <= "111";
wait for 20 ns;
end process;
end Behavioral_tb;
-----------------------------------------------------------------------------------------
 Cấu trúc with/select/when
--------------------------------------with/select/when-----------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity giaima3to8 is
Port(
input: in std_logic_vector(2 downto 0);
output: out std_logic_vector(7 downto 0)
);
end giaima3to8;

architecture Behavioral of giaima3to8 is

begin
with input select
output <= "00000001" when "000",
"00000010" when "001",
"00000100" when "010",
"00001000" when "011",
 "00010000" when "100",
"00100000" when "101",
"01000000" when "110",
"10000000" when others;
end Behavioral;

-----------------------------------------------------------------------------------------
 Sử dụng Process
----------------------------------------Process--------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity giaima3to8 is
Port(
input: in std_logic_vector(2 downto 0);
output: out std_logic_vector(7 downto 0)
);
end giaima3to8;

architecture Behavioral of giaima3to8 is

begin
process(input)
begin
if(input = "000") then output <= "00000001";
elsif(input = "001") then output <= "00000010";
elsif(input = "010") then output <= "00000100";
elsif(input = "011") then output <= "00001000";
elsif(input = "100") then output <= "00010000";
elsif(input = "101") then output <= "00100000";
elsif(input = "110") then output <= "01000000";
else output <= "10000000";
end if;
end process;
end Behavioral;
----------------------------------------------------------------------------------------
d.Mạch phân kênh 1 đầu vào 8 đầu ra
 Dựa trên mạch giải mã 3:8
------------------------------------------------------------------------------------( SAI code)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity bai3x4 is
Port(
input: in std_logic;
sel: in std_logic_vector(2 downto 0);
output: out std_logic_vector(7 downto 0)
);
end bai3x4;

architecture Behavioral of bai3x4 is

begin
process(sel)
begin
if(sel = "000") then output(0) <= input;
elsif(sel = "001") then output(1) <= input;
elsif(sel = "010") then output(2) <= input;
elsif(sel = "011") then output(3) <= input;
elsif(sel = "100") then output(4) <= input;
elsif(sel = "101") then output(5) <= input;
elsif(sel = "110") then output(6) <= input;
else output(7) <= input;
end if;
end process;
end Behavioral;
---------------------------------------------testbench------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY tb IS
END tb;

ARCHITECTURE Behavioral_tb OF tb IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT bai3x4
PORT(
input : IN std_logic;
sel : IN std_logic_vector(2 downto 0);
output : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;

signal input : std_logic;

signal sel : std_logic_vector(2 downto 0);
signal output : std_logic_vector(7 downto 0) ;

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: bai3x4 PORT MAP (
input => input,
sel => sel,
output => output
);
 process
begin
input <= '1';
sel <= "000";
wait for 5 ns;
input <= '1';
sel <= "001";
wait for 20 ns;
input <= '1';
sel <= "010";
wait for 10 ns;
input <= '1';
sel <= "011";
wait for 15 ns;
input <= '1';
sel <= "100";
wait for 20 ns;
input <= '1';
sel <= "101";
wait for 20 ns;
input <= '1';
sel <= "110";
wait for 20 ns;
input <= '1';
sel <= "111";
wait for 20 ns;
end process;
end Behavioral_tb;
-------------------------Mạch phân kênh xây dựng trực tiếp------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity bai3x5 is
Port(
output: out std_logic_vector(7 downto 0);
a,b,c: in std_logic;
input: in std_logic
);
end bai3x5;

architecture Behavioral of bai3x5 is

begin
output(0) <= (not a) and (not b) and (not c) and input;
output(1) <= (not a) and (not b) and c and input;
output(2) <= (not a) and b and (not c) and input;
output(3) <= (not a) and (b) and (c) and input;
output(4) <= (a) and (not b) and (not c) and input;
output(5) <= (a) and (not b) and (c) and input;
output(6) <= (a) and (b) and (not c) and input;
output(7) <= (a) and (b) and (c) and input;
end Behavioral;
---------------------------------------------testbench------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY tb IS
END tb;

ARCHITECTURE Behavioral_tb OF tb IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT bai3x5
PORT(
output : OUT std_logic_vector(7 downto 0);
a : IN std_logic;
b : IN std_logic;
c : IN std_logic;
input : IN std_logic
);
END COMPONENT;

signal input, a, b, c: std_logic;

signal output : std_logic_vector(7 downto 0);
BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: bai3x5 PORT MAP (
output => output,
a => a,
b => b,
c => c,
input => input
);

process
begin
input <= '1';
a <= '0';
b <= '0';
c <= '0';
wait for 5 ns;
input <= '1';
a <= '1';
b <= '0';
c <= '0';
wait for 20 ns;
input<= '1';
a <= '1';
b <= '1';
c <= '0';
wait for 10 ns;
input <= '1';
a <= '1';
b <= '1';
c <= '1';
wait for 15 ns;
end process;
end Behavioral_tb;
Ghép kênh 8 đầu vào 1 đầu ra
 Dựa trên mạch giải mã 8:3
-------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity 8to1 is
Port(
output: out std_logic;
sel: in std_logic_vector(2 downto 0);
input: in std_logic_vector(7 downto 0)
);
end 8to1;

architecture Behavioral of 8to1 is

begin
process(sel)
begin
case sel is
when "000" => output <= input(0);
when "001" => output <= input(1);
when "010" => output <= input(2);
when "011" => output <= input(3);
when "100" => output <= input(4);
when "101" => output <= input(5);
when "110" => output <= input(6);
when others => output <= input(7);
end case;
end process;
end Behavioral;
---------------------------------------------testbench------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb IS
END tb;

ARCHITECTURE Behavioral_tb OF tb IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT bai3x6
PORT(
output : OUT std_logic;
sel : IN std_logic_vector(2 downto 0);
input : IN std_logic_vector(7 downto 0)
);
END COMPONENT;

signal output: std_logic;

signal sel : std_logic_vector(2 downto 0);
signal input : std_logic_vector(7 downto 0);
BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: bai3x6 PORT MAP (
output => output,
sel => sel,
input => input
);

process
begin
input <= "11111111";
sel <= "000";
wait for 5 ns;
input <= "11111111";
sel <= "001";
wait for 20 ns;
input <= "11111111";
sel <= "010";
wait for 10 ns;
input <= "11111111";
sel <= "011";
wait for 15 ns;
input <= "11111111";
sel <= "100";
wait for 15 ns;
input <= "11111111";
sel <= "101";
wait for 15 ns;
input <= "11111111";
sel <= "110";
wait for 15 ns;
input <= "11111111";
sel <= "111";
wait for 15 ns;
end process;
end Behavioral_tb;

---------------------Mạch hợp kênh xây dựng trực tiếp-----------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity 8to1 is
Port(
output: out std_logic;
a,b,c: in std_logic;
input: in std_logic_vector(7 downto 0)
);
end 8to1;

architecture Behavioral of 8to1 is

signal d1,d2,d3,d4,d5,d6,d7,d0: std_logic;
begin
d0 <= (not a) and (not b) and (not c) and input(0);
d1 <= (not a) and (not b) and c and input(1);
d2 <= (not a) and b and (not c) and input(2);
d3 <= (not a) and (b) and (c) and input(3);
d4 <= (a) and (not b) and (not c) and input(4);
d5 <= (a) and (not b) and (c) and input(5);
d6 <= (a) and (b) and (not c) and input(6);
d7 <= (a) and (b) and (c) and input(7);
output <= d0 or d1 or d2 or d3 or d4 or d5 or d6 or d7;
end Behavioral;
---------------------------------------------testbench------------------------------------------------

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY tb IS
END tb;

ARCHITECTURE Behavioral_tb OF tb IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT bai3x7
 PORT(
output : OUT std_logic;
a : IN std_logic;
b : IN std_logic;
c : IN std_logic;
input : IN std_logic_vector(7 downto 0)
);
END COMPONENT;

--Inputs
signal a : std_logic ;
signal b : std_logic ;
signal c : std_logic ;
signal input : std_logic_vector(7 downto 0) ;

--Outputs
signal output : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: bai3x7 PORT MAP (
output => output,
a => a,
b => b,
c => c,
input => input
);

process

begin
a <= '0';
b <= '0';
c <= '0';
input <= "11111111";
wait for 20 ns;
a <= '0';
b <= '0';
c <= '1';
input <= "11111111";
wait for 20 ns;
a <= '0';
b <= '1';
c <= '0';
input <= "11111111";
wait for 20 ns;
a <= '0';
b <= '1';
c <= '1';
input <= "11111111";
wait for 20 ns;
a <= '1';
b <= '0';
c <= '0';
input <= "11111111";
wait for 20 ns;
a <= '1';
b <= '0';
c <= '1';
input <= "11111111";
wait for 20 ns;
a <= '1';
b <= '1';
c <= '0';
input <= "11111111";
wait for 20 ns;
a <= '1';
b <= '1';
c <= '1';
input <= "11111111";
wait for 20 ns;

end process;

END;

4. Xây dựng mạch giải mã BCD sang LED 7 đoạn

-----------------------BCD sang LED 7 đoạn---------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity btoled is
Port(
output: out std_logic_vector(7 downto 0);
input: in std_logic_vector(3 downto 0)
);
end btoled;

architecture Behavioral of btoled is

begin
output <= "00000011" when input = "0000" else
 "10011111" when input = "0001" else
"00100101" when input = "0010" else
"00001101" when input = "0011" else
"10011001" when input = "0100" else
"01001001" when input = "0101" else
"01000001" when input = "0110" else
"00011111" when input = "0111" else
"00000001" when input = "1000" else
"00001001";
end Behavioral;

----------------------------------------testbench------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY tb IS
END tb;

ARCHITECTURE Behavioral_tb OF tb IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT btoled
PORT(
output : OUT std_logic_vector(7 downto 0);
input : IN std_logic_vector(3 downto 0)
);
END COMPONENT;

--Inputs
signal input : std_logic_vector(3 downto 0) := (others => '0');

--Outputs
signal output : std_logic_vector(7 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: btoled PORT MAP (
output => output,
input => input
);
 process
begin
input <= "0000";
wait for 5 ns;
input <= "0001";
wait for 5 ns;
input <= "0010";
wait for 5 ns;
input <= "0011";
wait for 5 ns;
input <= "0100";
wait for 5 ns;
input <= "0101";
wait for 5 ns;
input <= "0110";
wait for 5 ns;
input <= "0111";
wait for 5 ns;
input <= "1000";
wait for 5 ns;
input <= "1001";
wait for 5 ns;
end process;
end Behavioral_tb;
5. Xây dựng mạch chuyển mã nhị phân sang Gray

-----------------------------------mã nhị phân sang mã Gray--------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity BtoG is
Port(
output: out std_logic_vector(3 downto 0);
input: in std_logic_vector(3 downto 0)
);
end BtoG;

architecture Behavioral of BtoG is

begin
output(3) <= input(3);
output(2) <= input(3) xor input(2);
output(1) <= input(2) xor input(1);
output(0) <= input(1) xor input(0);
end Behavioral;

----------------------------------------testbench------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY tb IS
END tb;

ARCHITECTURE Behavioral_tb OF tb IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT BtoG
PORT(
output : OUT std_logic_vector(3 downto 0);
input : IN std_logic_vector(3 downto 0)
);
END COMPONENT;

--Inputs
signal input : std_logic_vector(3 downto 0) := (others => '0');

--Outputs
signal output : std_logic_vector(3 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: BtoG PORT MAP (
output => output,
input => input
);

process
begin
input <= "0000";
wait for 5 ns;
input <= "0001";
wait for 5 ns;
input <= "0010";
wait for 5 ns;
input <= "0011";
wait for 5 ns;
input <= "0100";
wait for 5 ns;
input <= "0101";
wait for 5 ns;
input <= "0110";
wait for 5 ns;
input <= "0111";
wait for 5 ns;
input <= "1000";
wait for 5 ns;
input <= "1001";
wait for 5 ns;
end process;
end Behavioral_tb;