MDSRIC - 2018 Proceedings, 29-30 August, 2018 Wah/Pakistan

Modeling a High Resolution ADC for Underwater Sensors using ∆∑ modulator

Sohail Ahmed, Arshad Hussain
Department of Electronics
Quaid-i-Azam University
sakr289@gmail.com

ABSTRACT
Delta-Sigma Modulator has the features of high output signal-to-noise ratio (SNR), high
work efficiency and low total harmonic distortion (THD). Because of these extraordinary
features, this type of modulator has been widely used in ADC designs. In this paper, a new
model of 100dB, 3rd order Delta-Sigma Modulator for sensor system bandwidth of 15kHz,
with a sampling frequency of 3.84 MHz, has been proposed. The modulator is presented
for underwater sensor applications. To meet the required performances, a third order
delta-sigma (∑∆) modulator with loop filter composed of both feedback and feedforward
paths, has been implemented using fully differential, switched capacitor techniques. The
simulation results using a 4-bit quantizer, will be showing that the proposed modulator
structure can achieve the required outputs.

Keywords: analog to digital converter (ADC), delta-sigma (∑∆) modulator, underwater

sensor, switched-capacitor

1. INTRODUCTION: The technology have been found to be very useful in this

has brought us new ways to monitor and
sense aquatic environments. Underwater
sensors are therefore, designed to
acquire the information at the very first
stage. This sensor network consists of
sensors, which are interconnected
through either wired or wireless means.
These sensors further demand analog to
digital converter (ADC) according to its
application. Data converters, ADC and
digital to analog converter (DAC), play a
vital role in interfacing the digital
processing core with the outer real
analog world. At the input node,
underwater sensors sense the analog
signal and feed it to the ADC, which
further converts the signal into its digital
form and then the digital signal is
processed by a DAC at the output node.
These sensors require high resolution
ADCs to perform with high precision and
accuracy. Delta-Sigma (∆∑) modulators
regard. These modulators are found in
huge number of integrated circuits and
system applications. These converters are
highly appreciated because they provide
low cost and robust implementation for
achieving wide dynamic range and high
resolution in converting low bandwidth
input signals [1].
The combination of oversampling and
quantization noise shaping techniques
allow ∆∑ modulators to be immune to
many analog circuit limitations, thus
making them extensively used to realize
embedded analog-to-digital interfaces
[2]. These converters are power efficient
and flexible to incorporate with the
digital technology. A high power efficient
12-bit ADC for Underwater sensors is
designed for bandwidth of 15 kHz with
power dissipation of 37.1µW [3]. Our key
contributions are a comprehensive

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 MDSRIC - 2018 Proceedings, 29-30 August, 2018 Wah/Pakistan
modeling and simulation results that are
presented to estimate noise-shaping ADC
for the network of underwater sensors,
also to realize switched-capacitor
implementation system level non-
idealities like thermal noise, and
capacitor mismatch [2]. In section II, the
ADC design theory and modeling will be
presented. In section III, Delta-Sigma
modulator design with non-idealities and
simulation results will be presented and
the last section (IV) gives the conclusion.
2. ADC Design Theory
Almost all analog signals in the real world
require converting them into digital
form, for digital processing and storage
by the machine. The ADC converter
needs to be very efficient and for this
purpose, it requires low power
consumption with high accuracy and
precision. ADCs are of two types; the
Nyquist ADC and Oversampling ADC or the
Delta-Sigma modulator. Nyquist ADC
requires sampling frequency two times
greater than the signal bandwidth. For
the ADC signals, bandwidth achieved can
be higher while the accuracy is limited.
Delta-Sigma modulator utilizes
oversampling and noise shaping to
achieve high-resolution digital output. It
is a closed negative feedback system with
a feedback loop, which contains a
delayed, but otherwise unchanged
replica of the analog input signal and a
differential version of the quantization
error [3]. Signal is not changed by
modulation and the demodulation
operation does not need an integrator
while the loop filter has a high gain in
the signal band due to which the in-band
quantization noise strongly attenuated,
hence the property “noise shaping”. The
in-band quantization noise is reduced by
oversampling and noise shaping and
hence the accuracy of the modulator is
improved [2],[3]. The modulator consists
2
of a feedback loop, containing a loop
filter with an internal low-resolution ADC
and DAC, and a quantizer before the
output node. Loop filter consists of an
integrator which is connected in the
feedforward path. The conceptual block
diagram of basic first order ∆∑ ADC is
shown in Figure 1 and is built around
summers, integrators, quantizers, DACs
and digital filters [4].
Figure 1: 1st order ∆∑ ADC block
diagram
More quantization noise will be shaped at
higher frequencies by using higher order
modulators and this is done by increasing
the number of integrators inside the
loop. The quantizer can be a single bit or
multi-bit depending on the requirements
and resolution. The noise shaping ADC is
insensitive to component variation as the
front end is analog while the back end is
digital with pulse coded modulation
(PCM) output. The loop filter can have
two different architectures; the cascade
of integrator with multiple feedback
(CIFB) and the cascade of integrator with
multiple feedforward (CIFF) structures
[5]. The CIFB structure has multiple
feedback paths from the quantizer
output node to the input of every
integrator in the loop filter. This
structure ensures higher loop stability
and higher swing inside the loop filter as
integrator is dealing with both signal and
quantization noise. To suppress the non-
idealities in the real circuit
implementation, the integrator needs
more power hungry op-amp. The CIFF
structure has multiple feedforward paths
 MDSRIC - 2018 Proceedings, 29-30 August, 2018 Wah/Pakistan
at the adder in front of quantizer, which
ultimately results in reduced swing inside
the loop filter. The integrator inside the
loop filter is subjected to process only
the quantization noise, which requires a
low-gain op-amp design. The
disadvantage of CIFF is an extra adder in
front of quantizer that also demands op-
amp [5], [6].
This work will explore the design and
simulation of delta-sigma modulator ADC
for underwater sensor applications with a
bandwidth of 15 kHz with 23 bits of
resolution. The design phase will cover
the basic requirements and choices
followed by architectural characteristics
and structure. By simulating the order of
modulator for different number of bits in
the quantizer with OSR of 128, the design
requirement for the proposed ADC is
explored. Peak SNR and modulator order
for different bits of quantizer are shown
in Fig 2.
Figure 2: Order of modulator versus
SNR
From the Figure 1, it can be seen that
the 3rd order modulator with 4 bit
quantizer can achieve peak SNR of 128
3
dB, while for 3 bit quantizer it can
achieve peak SNR of 102 dB, for the 2 bit
quantizer it can achieve peak SNR of 97
dB. Finally, 3rd order 4-bit modulator is
selected by considering the stability of
the modulator for small quantization
steps and higher order of noise shaping
due to three integrators inside the loop.
Thus, the peak SNR of the selected third
order modulator is 128 dB. Dynamic
element matching is used for the
feedback digital to analog (DAC) for the
proper matching [7]. The design is
thermal noise limited, i.e., the achieved
SNR will depend on the capacitor size.
This work focuses on the CIFF structure.
The key advantage of this structure is
that only one feedback DAC is required,
which is more simple and easy to
implement. The NTF zero optimization
technique is also implemented across
second and third integrators to reduce in-
band quantization noise [7],[8].
3. MODELING AND SIMULATION
The simulink model single loop CIFF
delta-sigma modulator shown in Figure 3.
The coefficients of feedback and
feedforwards loop filter integrators are
calculated using the capacitor values of
the differential switched capacitors
which is to be used in the real circuit
design architecture [7], [8]. Table 1
shows these values.
g1
U V
b1 c2 c3 a3
c1 a2
a1
Figure 3: Third order multi-bit CIFF
Delta-Sigma Modulator
The loop filter coefficients of the
proposed modulator obtained for CIFF
structure are given as ai , bi , and ci and
the zero optimization across third and
 MDSRIC - 2018 Proceedings, 29-30 August, 2018 Wah/Pakistan

second integrator is given by coefficient optimization with maximum quantization

g [3]. noise suppression.

TABLE 1: CIFF coefficients

i ai bi ci g

1 0.4852 0.4852 0.3039 0.0028

2 0.3807 0 1.4671 0
Figure 5: NTF pole-zero plot with
3 1.0000 0 0.1298 0 zero optimization

4. MATLAB SIMULATION RESULTS

These coefficients are the initial The output of the Delta-Sigma modulator
information to realize the CIFF is shown in Figure 6. Analyzing the output
modulator. Dynamic range scaled of the modulator in time domain is not
coefficients are obtained and signal-to- very informative and it is much more
quantization noise ratio (SQNR) is plotted helpful to instead view the output in the
to estimate the modulator performance frequency domain as a power spectral
using Delta-Sigma Toolbox. The NTF pole density (PSD) as shown in Figure 7. The
zero plot (with and without zero PSD clearly shows the noise shaping and
optimization) in z-domain is shown in the null at DC [8]. The quantization noise
Figure 4 and Figure 5 respectively. floor rises at 40 dB/dec and the in-band
SNR is 102.9 dB and very closed to the
required SNR i.e., 100 dB and completely
dominated by a third order distortion
component with amplitude -131.1 dBFS.

Figure 4 : NTF pole zero plot without

zero optimization

The NTF zeroes are at z=1 and provide a

quantization attenuation at dc. The poles
are away from the origin. This results in a
lower high frequency NTF gain. The NTF
zeroes are spread for NTF zero

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 MDSRIC - 2018 Proceedings, 29-30 August, 2018 Wah/Pakistan
Figure 6: The output of 3rd order ∆∑
modulator which is only visible when
the time scale is adjusted
Figure 7: The output PSD showing the
3rd order noise shaping in addition to
a 3rd order distortion component.
With NTF zero optimization the power
spectral density is plotted in Figure 8.
Now the in-band SNR is increased to 107
dB with a relative decrease in 3rd order
distortion component with the amplitude
of -110.6 dBFS.
Figure 8: The output PSD with zero
optimization, showing the 3rd order
noise shaping in addition to a 3rd order
distortion component.
5
The modulator SNR as a function of input
amplitude is shown in Figure 9. The state
variables of the modulator x1 and x2,
which are also the integrator outputs, are
shown in figure 10 [7]. The plot
demonstrates that the dynamic range
scaling step has had the intended impact
on the signal swings [7]. The modulator
SNR as a function of input amplitude with
zero optimization level is shown in Figure
11.
Figure 9: The SNR or the DS
modulator improves as the input
amplitude is increased until the
maximum stable input.
Figure 10: The modulator’s two state
variables remain within acceptable
signal swings with the help of dynamic
range scaling performed by the delsig
Toolbox function scaleABCD.
 MDSRIC - 2018 Proceedings, 29-30 August, 2018 Wah/Pakistan

performance typically it is useful to keep

the slew-rate 20% of each period and
must reach 60% of the full-scale
integrator output. Thermal noise injected
at the input sampling path and the
feedback path of the modulator, thermal
noise sources that are inside the loop
filter will be noise shaped. Op-amp
noise is also injected in front of the first
integrator sampling capacitor, while
second and third integrator noise will be
shaped and it does not affect much the
performance of the modulator [7], [8].

6. CONCLUSION
Figure 11: SNR versus Amplitude with
NTF zero optimization where the peak A low power delta-sigma modulator is
SNR increased to 128.2 dB. used with cascade of integrators with
multiple feedforward structure to
5. NON IDEALITIES AND NOISE
implement a ADC for underwater sensors
The low power front-end of the application. The CIFF multi-bit modulator
modulator is analog while the back-end is with zero optimization has been modeled
digital as it responds with pulse code and simulation has been presented.
modulation (PCM) output that is Power consumption of the overall ADC
insensitive to many non-idealities [6]. reduced, which is expected to
The real transistor level circuits have substantially improve the battery
non-ideal effects that need to be duration for this proposed sensor.
simulated during MATLAB System level
simulation to get an estimate of the
performance at the real switched- 7. REFERENCES
capacitor implementation. Ideal
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G.C.Temes, 1997. Delta-Sigma
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drop of the SNR. To ensure best

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[6] L.Dai, R. Harjani. 2002. CMOS

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