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Vlsi (R2017) - Tanner Expt
Vlsi (R2017) - Tanner Expt
1. To launch S-Edit in PC, go to START > PROGRAMS > TANNER > S-EDIT
2. Click on Module > Symbol Browser or click on to launch the symbol browser
window. Choose your device and click on Place.
3. Once the main parts are in place, it is time to add I/O pins and wire the parts together.
Select and place an Input Pad and an Output pad on the schematic and give the pads a
unique name.
AIM
To design a CMOS inverter using the Schematic entry tool, Tanner and verify its
functioning.
APPARATUS REQUIRED:
1. Tanner tool
2. PC
THEORY:
CMOS Inverter consists of nMOS and pMOS transistor in series connected between
VDD and GND. The gate of the two transistors are shorted and connected to the input. When the
input to the inverter A = 0, nMOS transistor is OFF and pMOS transistor is ON. The output is
pull-up to VDD. When the input A = 1, nMOS transistor is ON and pMOS transistor is OFF. The
Output is Pull-down to GND.
PROCEDURE
CMOS INVERTER:
OUTPUT
RESULT
Thus the CMOS inverter has been designed and simulated using S-Edit of
Tanner EDA Tools.
11. DESIGN AND SIMULATE BASIC COMMON SOURCE, COMMON GATE AND
COMMON DRAIN AMPLIFIERS.
AIM
To design and simulate basic common source, common Gate and common drain using
the Schematic entry tool, Tanner and verify its functioning.
APPARATUS REQUIRED:
1. Tanner tool
2. PC
THEORY:
Tspice commands:
.print ac vdb(Out,Gnd)
.end
Output:
To add analysis,
Input impedance:
Output impedance:
Gain:
Av = -gm (RD || r0) (Ri /Ri+Rsi), gm = 1.41 mA/V, Rsi = 4 Kilo ohm
Net List:
* Design: dhivya
* Cell: Cell2
* View: view0
* Exclude .model: no
* Exclude .end: no
* Wrap lines: no
* Root path: C:\Users\Administrator\Desktop\dhivya
.probe
.option probev
MNMOS_1 Out In N_1 N_1 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
.end
OUTPUT WAVEFORM:
COMMON DRAIN:
Tspice commands:
MNMOS_1 Vdd N_3 Out Out NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
.print ac vdb(Out,gnd)
.end
OUTPUT:
Input impedance:
Output impedance:
R0 = RS || r0 || 1/gm
Gain:
Av = [gm (RS || r0) /(1+ gm (RS || r0))] * (Ri /Ri+Rsi), gm = 11.3 mA/V, Rsi = 4 Kilo ohm
Result:
Thus the Basic Common source, Common Gate and Common Drain Amplifiers are
designed and simulated using S-Edit of Tanner EDA Tools.
12. DESIGN AND SIMULATE SIMPLE 5 TRANSISTOR DIFFERENTIAL AMPLIFIER.
ANALYZE GAIN, BANDWIDTH AND CMRR BY PERFORMING SCHEMATIC
SIMULATIONS.
AIM
To design a simple 5 transistor Differential Amplifier using the Schematic entry tool, Tanner
and verify its functioning.
APPARATUS REQUIRED:
1. Tanner tool
2. PC
THEORY:
A differential amplifier is a type of electronic amplifier that multiplies the difference between two inputs
by some constant factor (the differential gain). Many electronic devices use differential amplifiers
internally. The output of an ideal differential amplifier is given by:
Where Vin+ and Vin- are the input voltages and Ac is the differential gain. In practice,
however, the gain is not quite equal for the two inputs. This means that if Vin+ and Vin- are equal, the
output will not be zero, as it would be in the ideal case. A more realistic expression for the output of a
differential amplifier thus includes a second term.
Ac is called the common-mode gain of the amplifier. As differential amplifiers are often used when it is
desired to null out noise or bias-voltages that appear at both inputs, a low common-mode gain is usually
considered good.
The common-mode rejection ratio, usually defined as the ratio between differential-mode gain and
common-mode gain, indicates the ability of the amplifier to accurately cancel voltages that are common
to both inputs. Common-mode rejection ratio (CMRR):
PROCEDURE
1. Draw the schematic of CMOS Inverter using S-edit.
2. Perform Transient Analysis of the CMOS Inverter.
3. Obtain the output waveform from W-edit.
4. Obtain the spice code using T-edit.
RESULT
Thus the 5 transistor Differential Amplifier has been designed and simulated performed using
Tanner EDA Tools.