CHAPTER 4. SOFTWARE PORTION 33 4.2 Creating A New Project Click on ‘Vivado 2014.2’ software. The window shown in Figure 4.2 will pop-up. VIVADO! - XUN Figure 4.2: Vivado 2014.2 opening window. Click on ‘Create New Project’ and then click ‘Next’ on the new pop-up window and then the window shown in Figure 4.3 will pop-up. Select your project name and its location and click on ‘Create project sub-directory’ and then click ‘Next’ to continue. Your project name must not start with numbers or special characters (5, :,!, /, etc.) and there should be no spaces in your name. You may use hyphen (_ ) to represent spaces in your name. Rian ET a ver eanaaayreniricor via mica aX Elownerapa niet Figure 4.3: New Project window.CHAPTER 4. SOFTWARE PORTION 34 Then click ‘RTL project’ and proceed by clicking the ‘Next’ button as shown in Figure 4.4. Ewer © Serene oe Figure 4.4: Project type window. Now ‘Add Sources’ window will pop-up. Verify and check that whether the target as well as. simulator language is ‘Verilog’ or not. If not then set these to ‘Verilog’. Now click on ‘Create File’ icon to proceed as shown in Figure 4.5, ry Deachttareeemnmecantrencnemnnn gl Figure 4.5: Add Sources window. Now select the name of your module and click ‘OK’ to continue as shown in Figure 4.6. The source file shall now be added (o the ‘Sources. Now press ‘Next’ (o continue as shown inCHAPTER 4. SOFTWARE PORTION 35 BL Create Source File x ® ceeate anew source fe and addi to your project Fie type, name and location. lle type: ® Verilog ¥ Flenane: [Outpt vlogs] Filg location: @) . ae Figure 4.6: Create Source File window. Figure 4.7. Skip the ‘Add Existing IP’ and ‘Add Constraint File’ window by clicking next on these popped-up windows. = SSS an Seamorenacen tenn ‘ | i a lo Figure 4.7: Add Sources window with a source file module. Now choose the FPGA part number by applying filters according to the Figure 4.8 and click ‘Next’, Now the ‘Project Summary’ shall appear. Click ‘Finish’ to create the Project. Now the software will demand the 1/0 ports for the module. Specify these in the list as shown. in Figure 4.9. You can specify multiple I/O through this list also you can specify the length of 1/0CHAPTER 4. SOFTWARE PORTION a ew Figure 4.8: Part selection. ports by enabling the ‘Bus’ command and then specify the MSBs and LSBs of the I/O ports. Figure 4.9: 1/0 ports specification. 36 Now click ‘OK’ to go to the ‘Main Project Window’ as shown in Figure 4.10 where you can edit your modules, add or remove sources from your existing modules, add or remove constraint files from them, add or remove IPs from your project, synthesize your code, implement the code, generate its bit-stream file and then upload it to the board through the Hardware Manager win- dow. Coming sections shall discuss each portion separately. Now let us make a simple clock divider and show its waveform on hardware. Let us divide the 100MHz built-in clock to SOkHz clock.CHAPTER 4. SOFTWARE PORTION Figure 4.10: Project Manager Window. 4.3 Coding the Module 37 To make the clock divider we will require a counter which will count up-to a certain value after which falling edge shall be triggered and again after counting up-to that value, the rising edge shall be triggered and so on. The value of count increments after every rising edge of the 10OMHz clock. So the value of counter comes out to be:- GivenClockFrequency 2 RequiredClockFrequency count50kHz max value= 1 100ME; count50kHz max value= > wees count50kHz max value= 999 The length of ‘count50kHz’ register is determined from following formula:- No. of bits of count50kHz register = loge(countS0kHz max value) aD (42) (43) (a)CHAPTER 4. SOFTWARE PORTION 38 No. of bits of countS0kHz register = logz(999) 45) No. of bits of count50kHz register =9.9643 bits 46) No. of bits of countS0kHz register = 10 bits a7 Hence count50kH. can be represented in 10 bits starting from Oth bit as LSB and 9th bit as MSB. Hence the declaration of the register is commenced as “reg [9:0] count50kEz;". Zamodule Oanput_voieages ( 24 inpuc CLKTooMHZ, 25 inpur RST, 26 output reg CLESOKHZ 27 oe 2e 2s reg [$20] councsoxi= — 07 30 31 always@(posedge ciELoomnz) 32 begin 33 LE (RST) 34 begin 38 ‘CLKSORMZ = 1; 37 ent 30 Af (countsoKAz == 999) an begin 42 CLESORHZ = ~cLKSOKHZ? 44 ena 45 elec begin coUNESOKHE = counesolHs + 17 ena Si endmodule Figure 4.11: Code for Clock Divider, ‘Then click ‘Open Elaborated Design’ and assign 1/0 ports to the pins on FPGA and then save the constraint file. Now run the Synthesis and then run the Implementation. Now click ‘Gen- crate BitStream’ (o generate the bit-stream file of the code and then upload it to the hardware through the ‘Hardware Manager’ as shown in Figure 4.12CHAPTER 4. SOFTWARE PORTION 39 Figure 4.12: Flow Navigator window. Last but not the least, connect the board to your PC and then open a new target device through hardware manager and burn the bit-stream file to your FPGA board and test your code. Hardware results are shown in Figure 4.13 RGR STF awh rene i FO 1 A nani 3.500 Frevi)aS0.00\e_sOutsaoS0. ae Seow Tiwe 10.0@ue 00.0002 Figure 4.13: CLK50KHZ signal from FPGA. This is the basic coding scheme of the FPGA. Now we will discuss the overall architecture of the software portion of the project in coming sections. 4.4 Analog To Digital Conversion Basys 3 board offers four XADC differential channels. The sampling rate of the XADC peripheral is IMSPS (Million Samples Per Second). ‘To enable the XADC peripheral, we make use of theCHAPTER 4. SOFTWARE PORTION 40 ‘XADC wizard available in ‘IP Catalog’ in ‘Project Manager. mem 5 az romain Gmscao susce Figure 4.14: Selection of IP Catalog from Project Manager Window. Then go to ‘FPGA Features and Designs, ‘XADC’ and then click ‘XADC Wizard’ Figure 4.15: IP Catalog window. ‘Then click the ‘XADC Wizard’ and do the following settings in the XADC wizard menu. Figure 4.16: XADC wizard basic window. ‘Then goto 'ADC Setup Window’ and do the settings shown by figure 4.17. ‘Then goto ‘Channel Sequencer Window’ and select the channels shown by figure 4.18. After completing above steps, goto the summary window shown by figure 4.19. This will show the complete description of the XADC module that is going to be used in the project. TheCHAPTER 4. SOFTWARE PORTION 4l & Poe Sita Figure 4.17: XADC wizard, ADC Setup window. name of the module is written at top of the window and to call this module, the exact module name must be used. In this case, the module name in xadc_ wiz_0. Then clicking ’Generate’ icon shown in figure 4.20, generates the IP wizard to be used in the code, The FPGA Board used in the project offers four differential XADC channels namely channel 6, channel 7, channel 14 and channel 15 according to the XADC wizard which has been added to the main module. Now we will discuss the I/O ports and functions of the XADC wizard IP separately. Refer to the figure 4.21 for the information about the 1/O ports used in the project. The Dynamic Reconfigurable Port (DRP) handles basic conversion operations such as XADG channel selection, start and end of conversion command and signal respectively, converted data output etc. Vaux6 represents channel 6 having two differential input ports at JXADC pin 1 (+ve) and 7 (-ve). Similarly, Vaux7, Vaux14 and Vaux15 are connected to JKADC pin 3 (+ve) and 9 (-ve}, pin 2 (+ve) and pin 8 (-ve), pin 4 (+ve) and pin 10 (-ve} respectively. ‘The XADC Wizard is available in the Vivado IDE IP catalog that instantiates an XADC block configured to your requirements. Using the wizard, you can explicitly configure the XADC to operate in the desired mode. XADC Wizard allows you to select the channels, enable alarms, and set the alarm limits. XADC supports the following interfaces: + AXI4CHAPTER 4. SOFTWARE PORTION 42 a ie Figure 4.18: XADC wizard, Channel Sequencer window. a eg Summary Interface Selected pee XADE operating made channel_sequencer ‘xt4Stream Interface ‘aloe ming Node Continuous DCL FreqQis) 100 Sequencer Mode Continuous Chane! Averaging None Enable External Mux false Figure 4.19: XADC wizard, Summary window. + Dynamic Reconfigurable Port (DRP) + AXI4-Stream For convenience, we chose Dynamic Reconfigurable Port (DRP} 4.4.1 Dynamic Reconfigurable Port (DRP) This port handles basic conversion operations such as XADC channel selection, start and end of conversion command and signal respectively, converted data output etc. The various ports and their functions are discussed below in table 4.1. The I/O ports shown in figure 4.21 areCHAPTER 4. SOFTWARE PORTION 43 A Generate Output Products x ® Tre otweg output products willbe generated. [aD mde ms cS] |B ipetntoton Tenoiate Syreszed Creckoont (4D) i] | eevee onset ‘0 Change toe QutoF Content Settings dod {6:01 or Pin(5.0} [eae sce Figure 4.23: XADC Configuration Registers. Note: Bits shown as 0 should always be left set to 0. atone 46 ‘The configuration registers can be modified through the DRP after the FPGA has been con- figured, For example, a soft microprocessor or state machine can be used to alter the contents of the XADC control registers at any time during normal operation. Table 4.3 through table 4.5 define the bits for the three configuration registers. DRP port contains 32 channels in which 16 are internal and the other 16 are auxiliary ex- ternal but the Basys 3 board supports four uni/bi-polar differential ADC channels. These ex- temal channels are VAUXP(6] / VAUXN(6], VAUXP(7] / VAUXN{7], VAUXP(14] / VAUXN(14] and VAUXP[15] / VAUXN(15] corresponding to DRP ADC channel number 22,23,30 and 31. These channels can be selected by amending last five bits of Configuration Register 0 as shown by ta- ble 4.6,CHAPTER 4. SOFTWARE PORTION aT ‘Test Registers (43h to 47h) These registers, intended for factory test purposes only, have a default status of zero, You must not write to these registers. Channel Sequencer Registers (48h to 4Fh) These registers are used to program the channel sequencer functionality. Alarm Registers (50h to SFh) ‘These registers are used to program the alarm thresholds for the automatic alarms on the inter- nally monitored channels, temperature, VCCINT, VCCAUX, and VCCBRAM. XADC Wizard Connectivity Before we go into the connections, we first declare some wires and I/O variables of our XADC module. Following are the variables and wires used for this purpose: + wire enable: This connection is made solely for the purpose of continuous conversion. Whenever XADC completes a conversion of sample, the End of Conversion flag is raised and the bit e0c_out is set. The conversion can be made continuous if we set den_in at the same time when the eoc_out bit is set. This is done by using a wire (enable) originating from eoc_out bit and terminating at den_in bit. This is shown in Figure 4.24. + wire ready: This wire carries the information about the completion of conversion from drdy_out bit. Ifset, then it means that the data is ready to be read from do_out register otherwise not. * wire [15:0] data: Once the conversion is complete, the data is sent to the do out register. The data wire is used to carry the converted data to the rest of the program from where other modules can act accordingly.CHAPTER 4. SOFTWARE PORTION 48 + reg Address_in: The daddr_in register is used to access different internal registers of the XADC peripheral. The most important task is to change the channels of XADC which is done by changing the last five bits of Configuration Register 0, located at address 40h, according to table 4.6. For this purpose, Address_in reg is used and its value in hexadecimal corresponding to auxiliary channels along with hardware inputs and constraint assignment is given in table 4.12. + input VauxpX/VauxnX: These are used for the physical connectivity of XADC channels as shown in table 4.12. ‘The clock given to the XADC peripheral can be set in Configuration Register 2 by adjusting first eight MSBs according to Table 4.11 through delk_in port. All other ports are unused for our project and this pretty much wraps up our chapter of Software Introduction,CHAPTER 4. SOFTWARE PORTION 49 ‘Table 4.3: Configuration Register 0 Bit Definitions DI0to DB. Name Description When operating in single channel mode or external CHOtoCH4 | multiplexer mode, these bits are used to select the ADC input channel. DIS When using single channel mode, this bit is used to increase the setting time available on external analog. inputs in continuous sampling mode by six ADCCLK cycles Acg pie This bit is used to select either continuous or event-driven | sampling mode for the ADC aC ‘A logic I places the ADC in event-driven sampling modeand a logic places the ADC in continuous | sampling mode. pio This bit is used in single channel mode to select either unipolar or bipolar operating mode for the ADC analog BU inputs A logic 1 places the ADC in bipolar mode and a logic U places the ADC. in unipolar mode. pit This bit should be set to a logic 1 toenable external MUX multiplexer mode. Bit Dii2, Du3 Name Description "These bits are used to set the amount of sample averaging on selected channels in both single channel and sequence Avo, aver | Mais pus This bit is used to disable averaging for the calculation oF the calibration coefficients. Averaging is enabled by CAVE | default (logic 0) To disable averaging, set this bit to logic 1. Averaging is fied at 16 samples,CHAPTER 4. SOFTWARE PORTION ‘Table 4.4: Configuration Register 1 Bit Definitions Bit bio Name or Description ] "This bit is used to disable the aver-temperature signal. ‘The alarm is disabled by setting this bit to logic 1. Dil to D3, DIS ALMO to ALM3 “These bits are used to disable individual alarm outputs for temperature, Veer, Vecaux, and Vecasam respectively. A logic | disables an alarm output. “These bits are used to disable individual alarm outputs DIgto DI | ALMA to ALM6 | for Vecpnst. Vecpaux, and Veco por, respectively. A logic 1 disables an alarm output. ‘These bits enable the application of the calibration coefficients to the ADC and on-chip supply sensor Dito DIT | CALD® CALS |) rpeasurements. Alogic 1 enables calibration and a logic 0 | disables calibration, | ‘These bits enable the channel-sequencer function. DN2to DUS | SEQD to EQS Table 4.5: Configuration Register 2 Bit Definitions Bit Ni Description Power-down bits for the XADC. The entire XADC block 7 can be powered down permanently by setting PD1 = PDO DH.DIs PO0/PO1 1. ADC B can also be powered down permanently by setting PDI = 2 and PDO = 0. These bits select the division ratio between the DRP clock (DCLK) and the lower frequency ADC clock (ADCCLK) pistopns | CDotocn7 | Deand ee 50CHAPTER 4. SOFTWARE PORTION ‘Table 4.6: ADC Channel Select che | che] cs | cH2 | cHi | cHo Description v o [0 | 0 | 0 | 0 |Onchip temperature 1 ofe fo fo [1 [vem 2 oto fof a | 0 |Vecaux 3 0 [| 0 | 0 [ @ | 1 |Va.V\ Dedicated analog inputs 4 ofo fa [0 | 0 |Vewaav 5 ope fa [© [2 [ven ov 6 o fo ft ft [6 [vec 7 a0 | 0 | 1 [ 1 | 1 [invalid channel selection 8 0 [i [0 [| 0 | © | CaryoutanXADC calibration oz Tnvalid channel selection 13 ofa 1 [0 | 1 [Veomr uw fo |i 1 [1 [0 |Vecaux re o >a r | |b [ves 2 1 [oo | o | o | o | ¥AXPia, vauxsto)— Ansar ii tf oo fo | o | a | YACxRL VAUXNTT~Assitny 1831 enn chanel 2105 Table 4.7: Averaging Filter Settings AVGI ‘AGO Function 0 0 No averaging 0 7 Average Iesamples T 0 Average samples T 7 Average 256 samplesCHAPTER 4. SOFTWARE PORTION 52 ‘Table 4.8: Sequencer Operation Settings SEQ3 | SEQ2 | SEGi | SEGO Function a 0 v 0 [Default mode 7 0 1 _[ Single pass sequence 0 a 0 __ | Continuous sequence mode 0 0 i 1__ | Single channel mode (sequencer off) 0 1 x X_| Simultaneous sampling mode 1 0 x X_| independent ADC mode T 1 x X_ [Default mode Table 4.9: Calibration Enables Name Description CALI ADCs offset correction enable CALI "ADCs offset and gain correction enable CAL Supply sensor offset comeection enable CALS Supply sensor offset and gain correction enable Table 4.10: Power Down Selection Description Default, All XADC blocks powered up Not valid — do net select ‘ADCB powered down XADC powered dawnCHAPTER 4. SOFTWARE PORTION Table 4.11: DCLK Division Selection co7 | cde | cds | cpa | co3 | coz | cDi | cDo Division 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 1 2 0 0 0 0 0 1 0 0 0 0 a 0 1 3 0 0 0 0 0 1 0 0 4 1 1 1 AL 1 1 1 0 254 1 1 1 1 1 1 1 1 255 Notes: 1. Minimum division ratio is 2, for example, ADCCLK = DCLK/2. 2. DCLK division must be selected to keep the ADC clock in its supported frequency range as specified in the applicable data sheet. Table 4.12: Correspondance of Address-in register Address_ial Hardware Pins Register Value Auxiliary Channel | (JXADC port pins) (hexadecimal sve | -ve 16h ‘Vauxp6 / Vauxn6 17h ‘Vausp7 / Vauxn7 1Eh ‘Vauxpl4 /Vauxnl4 ifh Vauxol5 /Vauxnl5CHAPTER 4. SOFTWARE PORTION XLXL7 iii CtCtid ik_in in lai in[15:0] ™ldwe_in alarm_out= "’lreset_in busy_out vauxnS channel_outf4:0]2° rn do_out[15:0]|-__ vauxnl4 drdy_out = auxniS e0c_out vauxp6 eos_outl" —->-—wauxp? jwauxpl4 jvauxplS lve in “lp _in wadc_wiz_0 Figure 4.24: XADC wizard connectivity.