TAS5631B

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300-W STEREO / 400-W MONO PurePath™ HD DIGITAL-INPUT POWER STAGE

Check for Samples: TAS5631B

1FEATURES APPLICATIONS
23 • PurePath™ HD Enabled Integrated Feedback • Mini Combo System
Provides: • AV Receivers
– Signal Bandwidth up to 80 kHz for High- • DVD Receivers
Frequency Content From HD Sources • Active Speakers
– Ultralow 0.03% THD at 1 W Into 4 Ω
– Flat THD at All Frequencies for Natural DESCRIPTION
Sound The TAS5631B is a high-performance PWM input
– 80-dB PSRR (BTL, No Input Signal) class-D amplifier with integrated closed-loop
feedback technology (known as PurePath HD
– >100-dB (A-weighted) SNR
technology) with the ability to drive up to 300 W (1)
– Click- and Pop-Free Start-Up stereo into 4-Ω to 8-Ω speakers from a single 50-V
• Multiple Configurations Possible on the Same supply.
PCB With Stuffing Options: PurePath HD technology enables traditional AB-
– Mono Parallel Bridge-Tied Load (PBTL) amplifier performance (<0.03% THD) levels while
– Stereo Bridge-Tied Load (BTL) providing the power efficiency of traditional class-D
amplifiers.
– 2.1 Single-Ended Stereo Pair and Bridge-
Tied Load Subwoofer Unlike traditional class-D amplifiers, the distortion
– Quad Single-Ended Outputs curve does not increase until the output levels move
into clipping. PurePath HD™
• Total Output Power at 10% THD+N
PurePath HD technology enables lower idle losses,
– 400 W per Channel in Mono PBTL
making the device even more efficient.
Configuration
– 300 W per Channel in Stereo BTL Note 1. Achievable output power levels are
Configuration dependent on the thermal configuration of the target
– 145 W per Channel in Quad Single-Ended application. A high-performance thermal interface
Configuration material between the package exposed heat slug
• High-Efficiency Power Stage (>88%) With 60- and the heat sink should be used to achieve high
mΩ Output MOSFETs output-power levels.
• Two Thermally Enhanced Package Options:
– PHD (64-Pin QFP) ♫♪
DIGITAL TAS5518C TM
– DKD (44-Pin PSOP3) AUDIO Digital PWM PurePath HD
Processor TAS5630
TAS5631B
• Self-Protection Design (Including
INPUT
♫♪
Undervoltage, Overtemperature, Clipping, and
Short-Circuit Protection) With Error Reporting
• EMI Compliant When Used With
Recommended System Design

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2 PurePath HD is a trademark of Texas Instruments.
3 All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2010–2012, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

DEVICE INFORMATION

Pin Assignment
Both package types contains a heat slug that is located on the top side of the device for convenient thermal
coupling to the heat sink.

PHD PACKAGE DKD PACKAGE

(TOP VIEW) (TOP VIEW)
PSU_REF

GVDD_B
GVDD_A

PVDD_A
PVDD_A
GND_A
OUT_A
OUT_A
BST_A
GND
GND
VDD

NC
NC
NC
NC

PSU_REF 1 44 GVDD_AB
VDD 2 43 BST_A
OC_ADJ 3 42 PVDD_A
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49

RESET 4 41 PVDD_A
OC_ADJ 1 48 GND_A
RESET C_STARTUP 5 40 OUT_A
2 47 GND_B
C_STARTUP 3 46 GND_B INPUT_A 6 39 OUT_A
INPUT_A 4 45 OUT_B INPUT_B 7 38 GND_A
INPUT_B 5 44 OUT_B VI_CM 8 37 GND_B
VI_CM 6 43 PVDD_B
GND 9 36 OUT_B

44 pins PACKAGE
GND 7 42 PVDD_B
AGND 8 41 BST_B AGND 10 35 PVDD_B

(TOP VIEW)
VREG 9 40 BST_C VREG 11 34 BST_B
INPUT_C 10 39 PVDD_C
INPUT_D 11 38 PVDD_C INPUT_C 12 33 BST_C
TEST 12 37 OUT_C INPUT_D 13 32 PVDD_C
NC 13 36 OUT_C TEST 14 31 OUT_C
NC 14 35 GND_C
15 34 GND_C
_ NC 15 30 GND_C
SD 64-pins QFP package
OTW1 16 33 GND_D NC 16 29 GND_D
26
17
18
19
20
21
22
23
24
25

27
28
29
30
31
32

SD 17 28 OUT_D
OTW 18 27 OUT_D
READY 19 26 PVDD_D
OTW2

READY
M1
M2
M3
GND
GND
GVDD_C
GVDD_D
BST_D
OUT_D
OUT_D
PVDD_D
PVDD_D
GND_D
CLIP

M1 20 25 PVDD_D
M2 21 24 BST_D
M3 22 23 GVDD_CD

PIN ONE LOCATION PHD PACKAGE

Electrical Pin 1
Pin 1 Marker
White Dot

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MODE SELECTION PINS

MODE PINS OUTPUT
PWM INPUT (1) DESCRIPTION
M3 M2 M1 CONFIGURATION
0 0 0 2N 2 × BTL AD mode
0 0 1 — — Reserved
0 1 0 2N 2 × BTL BD mode
0 1 1 1N 1 × BTL +2 × SE AD mode
1 0 0 1N 4 × SE AD mode
INPUT_C (2) INPUT_D (2)
2N
1 0 1 1 x PBTL 0 0 AC mode
IN
1 0 BD mode
1 1 0
Reserved
1 1 1

(1) The 1N and 2N naming convention is used to indicate the number of PWM lines to the power stage per channel in a specific mode.
(2) INPUT_C and INPUT_D are used to select between a subset of AD and BD mode operations in PBTL mode.

THERMAL INFORMATION
TAS5631B
THERMAL METRIC (1) (2) UNITS
PHD (64 Pins) DKD (44 Pins)
θJA Junction-to-ambient thermal resistance 8.5 9.3
θJCtop Junction-to-case (top) thermal resistance 0.2 0.6
θJB Junction-to-board thermal resistance 20.6 3.7
°C/W
ψJT Junction-to-top characterization parameter 0.2 1.3
ψJB Junction-to-board characterization parameter 0.73 3.5
θJCbot Junction-to-case (bottom) thermal resistance 8.2 19.1

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) Thermal model data was performed using a 40 x 40 x 90mm heat-sink

Table 1. ORDERING INFORMATION (1)

TA PACKAGE DESCRIPTION
0°C–70°C TAS5631BPHD 64-pin HTQFP
0°C–70°C TAS5631BDKD 44-pin PSOP3

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.

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ABSOLUTE MAXIMUM RATINGS

(1)
over operating free-air temperature range unless otherwise noted
TAS5631B UNIT
VDD to AGND –0.3 to 13.2 V
GVDD to AGND –0.3 to 13.2 V
PVDD_X to GND_X (2) –0.3 to 69 V
PVDD_X to GND_X; DC voltage -0.3 to 57 V
(2)
OUT_X to GND_X –0.3 to 69 V
BST_X to GND_X (2) –0.3 to 82.2 V
BST_X to GVDD_X (2) –0.3 to 69 V
VREG to AGND –0.3 to 4.2 V
GND_X to GND –0.3 to 0.3 V
GND_X to AGND –0.3 to 0.3 V
GND to AGND –0.3 to 0.3 V
OC_ADJ, M1, M2, M3, OSC_IO+, OSC_IO–, FREQ_ADJ, VI_CM, C_STARTUP, –0.3 to 4.2 V
PSU_REF to GND
INPUT_X, RESET, SD, OTW1, OTW2, CLIP, READY to GND –0.3 to 7 V
Maximum continuous sink current (SD, OTW1, OTW2, CLIP, READY) 9 mA
Maximum operating junction temperature range, TJ 0 to 150 °C
Storage temperature, Tstg –40 to 125 °C
(3)
Human-body model (all pins) ±2 kV
Electrostatic discharge
Charged-device model (3) (all pins) ±500 V

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) These voltages represents the dc voltage + peak ac waveform measured at the terminal of the device in all conditions.
(3) Failure to follow good anti-static ESD handling during manufacture and rework contributes to device malfunction. Make sure the
operators handling the device are adequately grounded through the use of ground straps or alternative ESD protection.

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
PVDD_x Half-bridge supply DC supply voltage 25 50 52.5 V
GVDD_x Supply for logic regulators and gate-drive circuitry DC supply voltage 10.8 12 13.2 V
VDD Digital regulator supply voltage DC supply voltage 10.8 12 13.2 V
RL(BTL) 3.5 4
(2) (1) Output filter according to schematics in the
RL(SE) Load impedance 1.8 2 Ω
application information section.
(2)
RL(PBTL) 2.4 3
LOUTPUT(BTL) 7 10
(2) (1)
LOUTPUT(SE) Output filter inductance Minimum output inductance at IOC 7 15 μH
LOUTPUT(PBTL) (2) 7 10
fPWM PWM frame rate 352 384 500 kHz

Overcurrent-protection-programming resistor, 64-pin QFP package (PHD) 22 33

cycle-by-cycle mode 44-Pin PSOP3 package (DKD) 24 33
ROCP kΩ
Overcurrent-protection-programming resistor,
PHD or DKD 47 68
latching mode
TJ Junction temperature 0 125 °C

(1) Values are for actual measured impedance over all combinations of tolerance, current and temperature and not simply the component
rating.
(2) See additional details for SE and PBTL in the System Design Considerations section.

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PIN FUNCTIONS
PIN
Function (1) DESCRIPTION
NAME PHD NO. DKD NO.
AGND 8 10 P Analog ground
BST_A 54 43 P HS bootstrap supply (BST); external 0.033-μF capacitor to OUT_A required
BST_B 41 34 P HS bootstrap supply (BST); external 0.033-μF capacitor to OUT_B required
BST_C 40 33 P HS bootstrap supply (BST); external 0.033-μF capacitor to OUT_C required
BST_D 27 24 P HS bootstrap supply (BST); external 0.033-μF capacitor to OUT_D required
CLIP 18 — O Clipping warning; open drain; active-low
C_STARTUP 3 5 O Start-up ramp requires a charging capacitor of 4.7 nF to AGND.
TEST 12 14 I Connect to VREG node
GND 7, 23, 24, 57, 58 9 P Ground
GND_A 48, 49 38 P Power ground for half-bridge A
GND_B 46, 47 37 P Power ground for half-bridge B
GND_C 34, 35 30 P Power ground for half-bridge C
GND_D 32, 33 29 P Power ground for half-bridge D
GVDD_A 55 — P Gate drive voltage supply requires 0.1-μF capacitor to AGND.
GVDD_B 56 — P Gate drive voltage supply requires 0.1-μF capacitor to AGND.
GVDD_C 25 — P Gate drive voltage supply requires 0.1-μF capacitor to AGND.
GVDD_D 26 — P Gate drive voltage supply requires 0.1-μF capacitor to AGND.
GVDD_AB — 44 P Gate drive voltage supply requires 0.22-μF capacitor to AGND.
GVDD_CD — 23 P Gate drive voltage supply requires 0.22-μF capacitor to AGND.
INPUT_A 4 6 I Input signal for half-bridge A
INPUT_B 5 7 I Input signal for half-bridge B
INPUT_C 10 12 I Input signal for half-bridge C
INPUT_D 11 13 I Input signal for half-bridge D
M1 20 20 I Mode selection
M2 21 21 I Mode selection
M3 22 22 I Mode selection
NC 59–62 – — No connect; pins may be grounded.
NC 13, 14 15, 16 — No connect; pins may be grounded.
OC_ADJ 1 3 O Analog overcurrent programming pin requires resistor to ground.
OTW — 18 O Overtemperature warning signal, open-drain, active-low
OTW1 16 — O Overtemperature warning signal, open-drain, active-low
OTW2 17 — O Overtemperature warning signal, open-drain, active-low
OUT_A 52, 53 39, 40 O Output, half-bridge A
OUT_B 44, 45 36 O Output, half-bridge B
OUT_C 36, 37 31 O Output, half-bridge C
OUT_D 28, 29 27, 28 O Output, half-bridge D
PSU_REF 63 1 P PSU reference requires close decoupling of 4.7 μF to AGND.
Power-supply input for half-bridge A requires close decoupling with 2.2μF capacitor to
PVDD_A 50, 51 41, 42 P
GND_A.
Power-supply input for half-bridge B requires close decoupling with 2.2μF capacitor to
PVDD_B 42, 43 35 P
GND_B.
Power-supply input for half-bridge C requires close decoupling with 2.2µF capacitor to
PVDD_C 38, 39 32 P
GND_C.
Power-supply input for half-bridge D requires close decoupling with 2.2μF capacitor to
PVDD_D 30, 31 25, 26 P
GND_D.
READY 19 19 O Normal operation; open-drain; active-high
RESET 2 4 I Device reset input; active-low
SD 15 17 O Shutdown signal; open-drain, active-low
Power supply for digital voltage regulator requires a 47-μF capacitor in parallel with a 0.1-
VDD 64 2 P
μF capacitor to GND for decoupling.
VI_CM 6 8 O Analog comparator reference node requires close decoupling of 4.7 μF to AGND.

(1) I = Input, O = Output, P = Power

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PIN FUNCTIONS (continued)

PIN
Function (1) DESCRIPTION
NAME PHD NO. DKD NO.
VREG 9 11 P Digital regulator supply filter pin requires 0.1-μF capacitor to AGND.

TYPICAL SYSTEM BLOCK DIAGRAM

Caps for
System External
microcontroller Filtering
and
AMP RESET (2) Startup/Stop

I2C

/OTW1, /OTW2, /OTW

/SD

/CLIP

READY

VI_CM

PSU_REF

C_STARTUP
TAS5518/ *NOTE1
TAS5508/
TAS5086 RESET
VALID BST_A
Bootstrap
BST_B Caps

PWM_A INPUT_A OUT_A 2nd Order

Left- L-C Output
Input Output 2
Channel PWM_B Filter for
INPUT_B H-Bridge 1 H-Bridge 1 OUT_B
Output each
2
H-Bridge

2-CHANNEL
H-BRIDGE
BTL MODE

PWM_C INPUT_C OUT_C

2nd Order
Right- Input Output L-C Output
2
Channel PWM_D INPUT_D H-Bridge 2 H-Bridge 2 OUT_D
Filter for
Output each
2
H-Bridge
M1
GVDD_A, B, C, D

BST_C
PVDD_A, B, C, D

Hardwire
GND_A, B, C, D

M2 Bootstrap
Mode
M3 BST_D Caps
OC_ADJ

Control
VREG

AGND

TEST
VDD
GND

8 8 4

PVDD PVDD GVDD, VDD, Hardwire

50V Power Supply Over-
and VREG
Decoupling Current
SYSTEM Power Supply
Power Decoupling Limit
Supplies
GND
GND
GVDD (12V)/VDD (12V)
12V

VAC

(1) Logic AND is inside or outside the microcontroller.

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FUNCTIONAL BLOCK DIAGRAM

CLIP

READY

OTW1

OTW2

SD

M1

PROTECTION & I/O LOGIC

M2 VDD

M3
POWER-UP
UVP VREG VREG
RESET
RESET
AGND
TEMP GVDD_A GVDD_C
STARTUP SENSE
GND
CONTROL GVDD_B GVDD_D
C_STARTUP

OVER-LOAD CURRENT
CB3C OC_ADJ
PROTECTION SENSE

4
PVDD_X
4
PPSC OUT_X
4
GND_X

GVDD_A

PWM
ACTIVITY BST_A
DETECTOR

PVDD_A

PWM TIMING
CONTROL GATE-DRIVE OUT_A
RECEIVER CONTROL

GND_A

PSU_REF
GVDD_B
VI_CM

ANALOG - BST_B
LOOP FILTER
INPUT_A +
PVDD_B

PWM TIMING
ANALOG + RECEIVER
CONTROL
CONTROL
GATE-DRIVE OUT_B
LOOP FILTER
INPUT_B -
ANALOG COMPARATOR MUX

GND_B
ANALOG INPUT MUX

4
PVDD_X GVDD_C
AGC
GND

BST_C

INPUT_C
ANALOG - PVDD_C
LOOP FILTER
+ PWM TIMING
CONTROL GATE-DRIVE OUT_C
RECEIVER CONTROL

INPUT_D
ANALOG + GND_C
LOOP FILTER
-
GVDD_D

BST_D

PVDD_D

PWM TIMING
CONTROL GATE-DRIVE OUT_D
RECEIVER CONTROL

GND_D

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AUDIO CHARACTERISTICS (BTL)

Audio performance is recorded as a chipset consisting of a TAS5518 PWM processor (modulation index limited to 97.7%)
and a TAS5631B power stage. PCB and system configurations are in accordance with recommended guidelines. Audio
frequency = 1 kHz, PVDD_X = 50 V, GVDD_X = 12 V, RL = 4 Ω, fS = 384 kHz, ROC = 22 kΩ, TC = 75°C;
output filter: LDEM = 10 μH, CDEM = 680 nF, MODE = 000, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RL = 4 Ω, 10% THD+N, clipped input signal 300
RL = 6 Ω, 10% THD+N, clipped input signal 210
RL = 8 Ω, 10% THD+N, clipped input signal 160
PO Power output per channel W
RL = 4 Ω, 1% THD+N, unclipped input signal 240
RL = 6 Ω, 1% THD+N, unclipped input signal 160
RL = 8 Ω, 1% THD+N, unclipped input signal 125
THD+N Total harmonic distortion + noise 1W 0.03%
Vn Output integrated noise A-weighted, TAS5518 modulator 180 μV
|VOS| Output offset voltage No signal 15 40 mV
SNR Signal-to-noise ratio (1) A-weighted, TAS5518 modulator 103 dB
A-weighted, input level –60 dBFS using TAS5518
DNR Dynamic range 103 dB
modulator
Power dissipation due to idle losses
Pidle PO = 0, all channels switching (2) 3.9 W
(IPVDD_X)

(1) SNR is calculated relative to 1% THD-N output level.

(2) Actual system idle losses also are affected by core losses of output inductors.

AUDIO SPECIFICATION (Single-Ended Output)

Audio performance is recorded as a chipset consisting of a TAS5086 PWM processor (modulation index limited to 97.7%)
and a TAS5631B power stage. PCB and system configurations are in accordance with recommended guidelines. Audio
frequency = 1 kHz, PVDD_X = 50 V, GVDD_X = 12 V, RL = 2 Ω, fS = 384 kHz, ROC = 22 kΩ, TC = 75°C;
output filter: LDEM = 7 μH, CDEM = 470 nF, MODE = 100, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RL = 2 Ω, 10%, THD+N, clipped input signal 145
RL = 3 Ω, 10%, THD+N, clipped input signal 100
RL = 4 Ω, 10%, THD+N, clipped input signal 75
PO Power output per channel W
RL = 2 Ω, 1% THD+N, unclipped input signal 110
RL = 3 Ω, 1% THD+N, unclipped input signal 75
RL = 4 Ω, 1% THD+N, unclipped input signal 55
THD+N Total harmonic distortion + noise 1W 0.04%
Vn Output integrated noise A-weighted, TAS5086 modulator 140 μV
(1)
SNR Signal-to-noise ratio A-weighted, TAS5086 modulator 100 dB
A-weighted, input level –60 dBFS using TAS5086
DNR Dynamic range 100 dB
modulator
Pidle Power dissipation due to idle losses (IPVDD_X) PO = 0, 4 channels switching (2) 3 W

(1) SNR is calculated relative to 1% THD-N output level.

(2) Actual system idle losses are affected by core losses of output inductors.

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AUDIO SPECIFICATION (PBTL)

Audio performance is recorded as a chipset consisting of a TAS5086 PWM processor (modulation index limited to 97.7%)
and a TAS5631B power stage. PCB and system configurations are in accordance with recommended guidelines. Audio
frequency = 1 kHz, PVDD_X = 50 V, GVDD_X = 12 V, RL = 3 Ω, fS = 384 kHz, ROC = 22 kΩ, TC = 75°C;
output filter: LDEM = 10 μH, CDEM = 680 nF, MODE = 100-00, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RL = 3 Ω, 10%, THD+N, clipped input signal 400
RL = 4 Ω, 10%, THD+N, clipped input signal 300
PO Power output per channel W
RL = 3 Ω, 1% THD+N, unclipped input signal 310
RL = 4 Ω, 1% THD+N, unclipped input signal 230
THD+N Total harmonic distortion + noise 1W 0.03%
Vn Output integrated noise A-weighted, TAS5518 modulator 170 μV
(1)
SNR Signal-to-noise ratio A-weighted, TAS5518 modulator 103 dB
A-weighted, input level –60 dBFS using TAS5086
DNR Dynamic range 103 dB
modulator
Pidle Power dissipation due to idle losses (IPVDD_X) PO = 0, 4 channels switching (2) 3.7 W

(1) SNR is calculated relative to 1% THD-N output level.

(2) Actual system idle losses are affected by core losses of output inductors.

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ELECTRICAL CHARACTERISTICS
PVDD_X = 50V, GVDD_X = 12 V, VDD = 12V, TC (case temperature) = 75°C, fS = 384 kHz, unless otherwise specified.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INTERNAL VOLTAGE REGULATOR AND CURRENT CONSUMPTION
Voltage regulator, only used as reference
VREG VDD = 12 V 3 3.3 3.6 V
node, VREG
VI_CM Analog comparator reference node, VI_CM 1.5 1.75 1.9 V
Operating, 50% duty cycle 22.5
IVDD VDD supply current mA
Idle, reset mode 22.5
50% duty cycle 12.5
IGVDD_x Gate-supply current per half-bridge mA
Reset mode 1.5
50% duty cycle without output filter or
19.5 mA
IPVDD_x Half-bridge idle current load
Reset mode, no switching 750 μA
OUTPUT-STAGE MOSFETs
Drain-to-source resistance, low side (LS) TJ = 25°C, excludes metallization 60 100 mΩ
RDS(on) resistance,
Drain-to-source resistance, high side (HS) GVDD = 12 V 60 100 mΩ

I/O PROTECTION
Vuvp,G Undervoltage protection limit, GVDD_X, VDD 9.5 V
(1)
Vuvp,hyst 0.6 V
OTW1 (1) Overtemperature warning 1 95 100 105 °C
OTW2 (1) Overtemperature warning 2 115 125 135 °C
(1) Temperature drop needed below OTW temperature for OTW to be inactive after OTW
OTWhyst 25 °C
event
Overtemperature error 145 155 165 °C
OTE (1)
OTE-OTW differential 30 °C
(1)
OTEHYST A reset must occur for SD to be released following an OTE event 25 °C
OLPC Overload protection counter fPWM = 384 kHz 2.6 ms
Nominal peak current in 1-Ω load,
64-pin QFP package (PHD) 15 A
ROCP = 22 kΩ
Overcurrent limit
Nominal peak current in 1-Ω load,
IOC 44-pin PSOP3 package (DKD) 15 A
ROCP = 24 kΩ
Nominal peak current in 1-Ω load,
Overcurrent latched 15 A
ROCP = 47 kΩ
Connected when RESET is active to
Internal pulldown resistor at output of each
IPD provide bootstrap charge. Not used in SE 3 mA
half-bridge
mode.
STATIC DIGITAL SPECIFICATIONS
VIH High-level input voltage 1.9 V
INPUT_X, M1, M2, M3, RESET
VIL Low-level input voltage 1.45 V
Ilkg Input leakage current 100 μA
OTW/SHUTDOWN (SD)
Internal pullup resistance, OTW, OTW1,
RINT_PU 20 26 33 kΩ
OTW2, CLIP, READY, SD to VREG
Internal pullup resistor 3 3.3 3.6
VOH High-level output voltage V
External pullup of 4.7 kΩ to 5 V 4.5 5
VOL Low-level output voltage IO = 4 mA 200 500 mV
Device fanout OTW, OTW1, OTW2, SD,
FANOUT No external pullup 30 devices
CLIP, READY

(1) Specified by design

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TYPICAL CHARACTERISTICS, BTL CONFIGURATION

TOTAL HARMONIC DISTORTION + NOISE OUTPUT POWER
vs vs
OUTPUT POWER SUPPLY VOLTAGE
10 320
4Ω 4Ω
300
6Ω 6Ω
THD+N − Total Harmonic Distortion + Noise − %

8Ω 280 8Ω
260
240
1 220

PO − Output Power − W
200
180
160
140
0.1
120
100
80
60
40
0.01 TC = 75°C
TC = 75°C 20 THD+N at 10%
0.005 0
0.02 0.1 1 10 100 400 25 30 35 40 45 50
PO − Output Power − W PVDD − Supply Voltage − V

Figure 1. Figure 2.

UNCLIPPED OUTPUT POWER SYSTEM EFFICIENCY

vs vs
SUPPLY VOLTAGE OUTPUT POWER
280 100
4Ω 95
260 6Ω 90
240 8Ω 85
220 80
75 4Ω
200 70 6Ω
PO − Output Power − W

65 8Ω
180
Efficiency − %

60
160
55
140 50
45
120
40
100 35
80 30
25
60 20
40 15
10 TC = 25°C
20
TC = 75°C 5 THD+N at 10%
0 0
25 30 35 40 45 50 0 100 200 300 400 500 600 650
PVDD − Supply Voltage − V 2 Channel Output Power − W

Figure 3. Figure 4.

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TYPICAL CHARACTERISTICS, BTL CONFIGURATION (continued)

SYSTEMS POWER LOSS OUTPUT POWER
vs vs
OUTPUT POWER CASE TEMPERATURE
100 360
95 TC = 25°C 340
90 THD+N at 10%
320
85 300
80
280
75
260
70

PO − Output Power − W
65 240
Power Loss − W

60 220
55 200
50 180
45 160
40 140
35 120
30
100
25
80
20
15 60
4Ω 4Ω
10 40
6Ω 6Ω
5 8Ω 20 8Ω THD+N at 10%
0 0
0 100 200 300 400 500 600 650 −50−40−30−20−10 0 10 20 30 40 50 60 70 80 90 100110
2 Channel Output Power − W TC − Case Temperature − °C

Figure 5. Figure 6.

NOISE AMPLITUDE
vs
FREQUENCY
+0
-10 TC = 75°C,
-20 VREF = 31.7 V,
-30 Sample Rate = 48 kHz,
-40 FFT Size = 16384
Noise Amplitude - dB

-50
-60
-70
-80
-90
-100
-110
-120
-130 4W
-140
-150
-160
0k 2k 4k 6k 8k 10k 12k 14k 16k 18k 20k 22k
f - Frequency - Hz
Figure 7.

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TYPICAL CHARACTERISTICS, SE CONFIGURATION

1 Channel Driven

TOTAL HARMONIC DISTORTION + NOISE OUTPUT POWER

vs vs
OUTPUT POWER SUPPLY VOLTAGE
10 160
2Ω 2Ω
150
3Ω 3Ω
THD+N − Total Harmonic Distortion + Noise − %

4Ω 140 4Ω
130
120
110

PO − Output Power − W
1
100
90
80
70
60
0.1
50
40
30
20
TC = 75°C
TC = 75°C 10 THD+N at 10%
0.01 0
0.02 0.1 1 10 100 200 25 30 35 40 45 50
PO − Output Power − W PVDD − Supply Voltage − V

Figure 8. Figure 9.

OUTPUT POWER
vs
CASE TEMPERATURE
170
160
150
140
130
120
PO − Output Power − W

110
100
90
80
70
60
50
40
30
20 2Ω
3Ω
10 4Ω THD+N at 10%
0
−10 0 10 20 30 40 50 60 70 80 90 100 110
TC − Case Temperature − °C

Figure 10.

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TYPICAL CHARACTERISTICS, PBTL CONFIGURATION

TOTAL HARMONIC DISTORTION + NOISE OUTPUT POWER
vs vs
OUTPUT POWER SUPPLY VOLTAGE
10 500
3Ω 3Ω
4Ω 450 4Ω
THD+N − Total Harmonic Distortion + Noise − %

6Ω 6Ω
8Ω 8Ω
400

1 350

PO − Output Power − W
300

250
0.1
200

150

100
0.01
50 TC = 75°C
TC = 75°C THD+N at 10%
0.003 0
0.02 0.1 1 10 100 700 25 30 35 40 45 50
PO − Output Power − W PVDD − Supply Voltage − V
G001 G001

Figure 11. Figure 12.

OUTPUT POWER
vs
CASE TEMPERATURE
500

450

400

350
PO − Output Power − W

300

250

200

150

100
3Ω
4Ω
50 6Ω
8Ω THD+N at 10%
0
−10 0 10 20 30 40 50 60 70 80 90 100 110
TC − Case Temperature − °C
G001

Figure 13.

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APPLICATION INFORMATION

PCB MATERIAL RECOMMENDATION

FR-4 2-oz. (70 μm) glass epoxy material is recommended for use with the TAS5631B. The use of this material
can provide for higher power output, improved thermal performance, and better EMI margin (due to lower PCB
trace resistance).

PVDD CAPACITOR RECOMMENDATION

The large capacitors used in conjunction with each full bridge are referred to as the PVDD capacitors. These
capacitors should be selected for proper voltage margin and adequate capacitance to support the power
requirements. In practice, with a well-designed system power supply, 1000 μF, 63 V support more applications.
The PVDD capacitors should be low-ESR type due to high ripple current.

DECOUPLING CAPACITOR RECOMMENDATION

To design an amplifier that has robust performance, passes regulatory requirements, and exhibits good audio
performance, good-quality decoupling capacitors should be used. In practice, X7R should be used in this
application.
The voltage of the decoupling capacitors should be selected in accordance with good design practices.
Temperature, ripple current, and voltage overshoot must be considered. This fact is particularly true in the
selection of the 2.2-μF capacitor that is placed on the power supply to each half-bridge. It must withstand the
voltage overshoot of the PWM switching, the heat generated by the amplifier during high power output, and the
ripple current created by high power output. A minimum voltage rating of 63 V is required for use with a 50-V
power supply.

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SYSTEM DESIGN RECOMMENDATIONS

The following schematics and PCB layouts illustrate best practices in the use of the TAS5631B.

GVDD/VDD (+12V)

R30 PVDD

1
1 2
C64
3.3R
R31 1000uF
1 2 C40

2
1

1
33nF
3.3R
C25 C26 1 2 L10

1
10uF 100nF 10uH GND
C30 C31 1 2 OUT_LEFT_P

2
100nF 100nF

1
2

2
GND GND C60 R70
C23
2.2uF 3.3R

1
GND 2 1 GND

1 2
C50 C70
VREG 680nF 1nF
4.7uF C74

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

2
1
GND 10nF
R19 +

PSU_REF

PVDD_A

PVDD_A
BST_A

OUT_A

OUT_A

GND_A
GVDD_B

GVDD_A
VDD

NC

NC

NC

NC

GND

GND

2
R18 47k
2 1
/RESET
2
1

1
-
100R C18 C75 GND
100pF R20 GND 10nF
GND 2 1 1 48
2

1 2
OC_ADJ GND_A

1
22.0k 2 47 C51 C71
GND C20 /RESET GND_B 680nF 1nF R71
R10
2 1 GND 2 1 3 46 L11 3.3R
IN_LEFT_P

2
C_STARTUP GND_B GND 10uH

2
100R 4.7nF 4 45 1 2
INPUT_A OUT_B OUT_LEFT_M

2
5 44
C21 INPUT_B OUT_B C61 C41
R11
2 1 GND 2 1 6 43 2.2uF 33nF
IN_LEFT_N VI_CM PVDD_B

1
100R 4.7uF 7 42 PVDD
GND PVDD_B

1
U10

1
8 41 C68 R74
C22 VREG GND AGND BST_B 1000uF 1000uF 47uF C69 3.3R
R12
IN_RIGHT_P
2 1 GND 1 2 9 TAS5631BPHD 40 C65 C66 63V 2.2uF

12
VREG BST_C
GND

2
100R 100nF 10 39 C78
INPUT_C PVDD_C 10nF

2
11 38 GND GND GND GND

2
VREG INPUT_D PVDD_C C62 C42 GND
R13
2 1 12 37 2.2uF 33nF
R_RIGHT_N TEST OUT_C GND

1
100R 13 36 1 2 OUT_RIGHT_P
NC OUT_C

1
14 35 10uH R72
NC GND_C L12 3.3R
15 34

1 2
/SD GND_C

1
GND
16 33 C52 C72
/OTW1 GND_D 680nF 1nF C76
10nF

2
GVDD_C

GVDD_D

2
PVDD_D

PVDD_D
+

GND_D
READY

OUT_D

OUT_D
BST_D
/OTW2

/CLIP

GND

GND

1
M1

M2

M3 C77 GND -
10nF
/SD
17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32
GND

1 2
/OTW1

1
C63 C53 C73 R73
/OTW2
2.2uF 680nF 1nF 3.3R
L13
/CLIP

2
GND 10uH
1 2
READY
OUT_RIGHT_R
VREG
1 2 PVDD

1
C43 C67
33nF 1000uF

2
R32
GND 1 2
3.3R GND
R33
2 1 GVDD/VDD (+12V)
2

3.3R

C33 C32
100nF 100nF
1

GNDGND

Figure 14. Typical Differential (2N) BTL Application With BD Modulation Filters

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3.3R
VDD (+12V) 1 2 GVDD (+12V)
3.3R
1 2 PVDD

1
100nF 100nF 3.3R

1
10uF 100nF 33nF 10uH
1 2 1 2 1000uF 47uF 2.2uF

12
63V 63V 63V
10nF

2
GNDGND GNDGND 63V

1
VREG

2
2.2uF

1
4.7uF 63V
GND
2 1 GND GND GND GND GND
47k

2
100R
2 1 6.3V
/RESET

2
1

54
64

63

62

61

60

59

58

57

56

55

53

52

51

50

49

1
100pF GND
1000uF

BST_A
VDD

PSU_REF

NC

NC

NC

NC

GND

GND

GVDD_B

GVDD_A

OUT_A

OUT_A

PVDD_A

PVDD_A

GND_A
63V

2
GND 22.0k
2 1 GND
100R 1 48
48
2 1 OC_ADJ GND_A
IN_P GND 4.7nF 2 47
2 1 /RESET GND_B OUT_LEFT_P
3 46
6.3V C_STARTUP GND_B GND 10uH

1
GND 4 45 1 2
INPUT_A OUT_B
3.3R

1
100R 5 44
44
2 1 4.7uF INPUT_B OUT_B 2.2uF 1uF
33nF

1 2
IN_N 2 1 43 63V 250V
6 43
VI_CM PVDD_B

1
2

2
6.3V 77 42 1nF 10nF
GND GND PVDD_B 63V 63V
100nF VREG 8 41 +

2
AGND BST_B
1 2 GND
9
VREG
TAS5631BPHD BST_C
40

1
VREG -
GND 10
10 39 GND 1nF 10nF GND
INPUT_C PVDD_C 63V 63V

1
11 38

1 2
VREG INPUT_D PVDD_C 2.2uF 1uF
33nF
12 37 63V 250V
GND TEST OUT_C 10uH
3.3R

2
13 36 1 2
NC OUT_C

2
14 35
35
NC GND_C
15 34 OUT_LEFT_M
/SD GND_C GND
16
16 33
/OTW1 GND_D

GVDD_C

GVDD_D

PVDD_D

PVDD_D

GND_D
READY

OUT_D

OUT_D
BST_D
/OTW2

/CLIP

GND

GND

1
M1

M2

M3
1000uF
63V

27
17

18

19

20

21

22

23

24

25

26

28

29

30

31

32
24

26

28

29

30

31
27

2
1
2.2uF GND
63V
/SD PVDD

1
GND GND
1000uF
/OTW1
VREG 10uH 63V
1 2 1 2
/OTW2

2
33nF
/CLIP
3.3R GND
2 1
READY
3.3R
2 1 2 GVDD (+12V)

2
100nF 100nF
1

GNDGND

Figure 15. Typical Differential (2N) BTL Application With BD Modulation Filters

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3.3R
1 2
VDD (+12V)
3.3R
1 2

1
GVDD (+12V)
100nF 100nF
10uF 100nF 33nF 10uH
1 2 1 2
A

2
GND GND GNDGND PVDD

1
VREG
2.2uF

1
4.7uF 63V
2 1 GND
47k GND

2
100R
2 1 6.3V
/RESET

2
1

64

63

62

61

60

59

58

57

54

53

52

51

50
56

55

49
100pF GND

PSU_REF

BST_A
VDD

NC

NC

NC

NC

GND

GND

GVDD_B

GVDD_A

OUT_A

OUT_A

PVDD_A

PVDD_A

GND_A
2
GND 22.0k
2 1
1 48
48
OC_ADJ GND_A
GND 10nF 2 47
47
100R 2 1 /RESET GND_B
2 1 3 46
46
IN_A C_STARTUP GND_B
6.3V GND 10uH
GND 4 45
45 1 2
INPUT_A OUT_B B

2
5 44
44
100R 4.7uF INPUT_B OUT_B 2.2uF
33nF
2 1 2 1 6 43
43 63V
IN_B VI_CM PVDD_B

1
6.3V 7
7 42
42 PVDD

1
GND GND PVDD_B
100nF VREG 8 41
41 3.3R

1
AGND BST_B

IN_C
2
100R
1
1 2 GND
9 TAS5631BPHD 40
40 47uF 2.2uF

12
VREG BST_C 63V 63V
GND 10
10 39
39 10nF

2
INPUT_C PVDD_C 63V

2
11 38
38

2
100R VREG INPUT_D PVDD_C 2.2uF 33nF
2 1 12 37
37 63V
IN_D TEST OUT_C 10uH GND GND GND

1
13 36
36 1 2
NC OUT_C C
14 35
35
NC GND_C
15 34
34
/SD GND_C GND
16
16 33
33
/OTW1 GND_D

GVDD_C

GVDD_D

PVDD_D

PVDD_D

GND_D
READY

OUT_D

OUT_D
BST_D
/OTW2

/CLIP

GND

GND
M1

M2

M3
17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32
24

26

28

29

30

31
27

1
2.2uF
63V
/SD PVDD

2
GND
/OTW1
VREG 10uH
1 2 1 2
/OTW2 D
33nF
/CLIP
GND 3.3R
2 1
READY GVDD (+12V)
3.3R
1 2

2
100nF 100nF

1
10nF 10nF
63V GNDGND 63V
1 2 1 2

1
3.3R GND 3.3R GND

2
OUT_A_P OUT_B_P
A B
2

1
100nF 100nF
R_COMP
2

R_COMP

1
63V + 63V +
470nF 470nF
1 1

10k
1 2

1 1
10k

1 2
PVDD 250V PVDD 250V
2

2
- -
1

2
470uF 10k 100nF GND 470uF 10k 100nF GND
50V 1% 63V 50V 1% 63V
12

21

12

21

2
OUT_A_M OUT_B_M
1

1
470uF 10k 470uF 10k
50V 1% 3.3R 50V 1% 3.3R
PVDD R_COMP
2

1
2

2
1 2 1 2
50 V 150 kOhm GND GND
63V 63V
10nF GND 10nF GND
49 V 169 kOhm
48 V 191 kOhm 10nF 10nF
47 V 191 kOhm 63V 63V
1 2 1 2
<47 V 196 kOhm
1

1
3.3R GND 3.3R GND
2

2
OUT_C_P OUT_D_P
C D
2

1
100nF 100nF
R_COMP
2

R_COMP

1
63V + 63V +
470nF 470nF
1 1

10k
1 2

1 1

10k

1 2
PVDD 250V PVDD 250V
2

- -
1

2
470uF 10k 100nF GND 470uF 10k 100nF GND
50V 1% 63V 50V 1% 63V
12

21

12

21

2
OUT_C_M OUT_D_M
1

1
470uF 10k 470uF 10k
50V 1% 3.3R 50V 1% 3.3R
2

1
2

2
1 2 1 2
GND GND
63V 63V
10nF GND 10nF GND

Figure 16. Typical SE Application

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GVDD (+12V)

PVDD

1
3.3R
VDD (+12V) 1 2 1000uF
63V
3.3R

2
1 2

1
100nF 100nF GND
10uF 100nF 33nF 10uH
1 2 1 2 OUT_CENTER_P

1
GND GND GNDGND

1
VREG
3.3R

1
2.2uF

1
4.7uF 63V 680nF

1 2
GND 2 1 GND 250V
47k

1
100R

2
2 1 6.3V 1nF 10nF
/RESET

2
1 63V 63V

54
64

63

62

61

60

59

58

57

56

55

53

52

51

50

49
100pF GND +

2
BST_A
VDD

PSU_REF

NC

NC

NC

NC

GND

GND

GVDD_B

GVDD_A

OUT_A

OUT_A

PVDD_A

PVDD_A

GND_A
2

1
-
GND 1nF 10nF GND
GND 22.0k 63V 63V

1
2 1

1 2
1 48
48 680nF
OC_ADJ GND_A 250V
GND 10nF 2 47
3.3R

2
2 1 /RESET GND_B
3 46

2
100R 6.3V C_STARTUP GND_B GND 10uH
2 1 GND 4 45 1 2
IN_CENTER INPUT_A OUT_B
VREG OUT_CENTER_M

2
5 44
44
4.7uF INPUT_B OUT_B 2.2uF
33nF
2 1 6 43
43 63V
VI_CM PVDD_B

1
6.3V 77 42 PVDD
GND PVDD_B

1
GND
100nF VREG 8
AGND TAS5631BPHD BST_B
41 3.3R

1
100R 1 2 GND
2 1 9 40 1000uF 47uF 2.2uF
IN_LEFT

12
VREG BST_C 63V 63V 63V 10nF
GND 10
10 39 10nF 63V

2
INPUT_C PVDD_C 63V 2 1

1
11 38

2
100R VREG INPUT_D PVDD_C 2.2uF 33nF 3.3R
2 1 12 37 63V GND GND GND GND
IN_RIGHT TEST OUT_C 10uH GND

2
13 36 1 2 OUT_LEFT_P
NC OUT_C

1
14 35
35
NC GND_C 100nF
R_COMP

1
15 34 63V +
/SD GND_C GND 470nF
10k

1 1

1 2
16
16 33 PVDD 250V
/OTW1 GND_D

2
-

2
470uF 10k 100nF GND
50V 1% 63V

GVDD_C

GVDD_D

PVDD_D

PVDD_D

GND_D
READY

OUT_D

OUT_D
BST_D
/OTW2

12

21

12
OUT_LEFT_M
/CLIP

GND

GND
470uF 10k
M1

M2

M3
3.3R
50V 1%
2 1

27
17

18

19

20

21

22

23

24

25

26

28

29

30

31

32

2
24

26

28

29

30

31
27
63V

1
GND GND 10nF
2.2uF
VREG 63V 10nF
63V
/SD

2
GND GND 2 1

1
/OTW1
3.3R
1 2 10uH GND
/OTW2
1 2 OUT_RIGHT_P

1 2
33nF
/CLIP

2
3.3R
2 1 100nF
READY R_COMP

1
3.3R 63V +
1 2 470nF
10k

1 1

1 2
PVDD 250V
2

2
-

2
470uF 10k 100nF GND
100nF 100nF
PVDD R_COMP 50V 1% 63V
1

12

21

12
OUT_RIGHT_M
470uF 10k
50 V 150 kOhm 3.3R
GNDGND 50V 1%
49 V 169 kOhm 2 1

2
63V
48 V 191 kOhm 10nF
GND GND
47 V 191 kOhm
PVDD
<47 V 196 kOhm
GVDD (+12V)

Figure 17. Typical 2.1 System (2N) Input BTL and (1N) Input SE Application

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R34
2 1 GVDD (+12V)
1.5R

1
C38 C87 PVDD
100nF 100nF

1
2

2
1000uF
VDD (+12V) 63V
GND

2
1

1
C44 C35
10uF 100nF 10uH GND
1 2 OUT_LEFT_P

1
GND GND
C86 3.3R

1
VREG 2 1 680nF
GND
U16

1 2
250V

1
TAS5631BDKD

2
R44 4.7uF 1nF 10nF
R13 47k 100V 100V
2 1 1 44 +
/RESET

2
1 PSU_REF GVDD_AB C33
100R C78 2 43 1 2
VDD BST_A

1
100pF R14 -
2 1 3 42 33nF GND 1nF 10nF GND
GND
2

OC_ADJ PVDD_A 100V 100V

1
24k 4 41

1 2
/RESET PVDD_A

1
GND C45 680nF
R45
2 1 2 1 5 40 C83 250V
IN_LEFT_P GND C_STARTUP OUT_A 2.2uF
3.3R

2
100R 4.7nF 6 39

2
INPUT_A OUT_A

2
7 38 10uH
C85 INPUT_B GND_A 1 2
R54
2 1 GND 2 1 8 37 OUT_LEFT_M
IN_LEFT_N VI_CM GND_B GND
100R 4.7uF 9 36 PVDD
GND OUT_B

1
1
C42 VREG 10 35
AGND PVDD_B 3.3R

1
R53 GND 1 2 GND C41 C90 1000uF 1000uF
33nF 47uF
2 1 11 34 2 1 2.2uF 2.2uF
IN_RIGHT_P

12
100nF VREG BST_B 63V 100V
63V 63V

12
100R 12 33 2 1 10nF

2
INPUT_C BST_C C91 100V
C37 33nF
13 32 2.2uF GND

2
VREG INPUT_D PVDD_C
R60

2
2 1 14 31 GND GND GND GND
IN_RIGHT_N TEST OUT_C GND
100R 15 30 10uH
NC GND_C 1 2 OUT_RIGHT_P
16 29
NC GND_D

1
17 28
/SD OUT_D

1
GND
3.3R

1
18 27 C34
/OTW OUT_D 2.2uF 680nF

1 2
19 26 250V

2
READY PVDD_D

1
2
20 25 1nF 10nF
VREG M1 PVDD_D 100V 100V
21 24 1 2 +

2
M2 BST_D
22 23 33nF
M3 GVDD_CD

1
C88 -
GND 1nF 10nF GND
100V 100V

1
GND
/SD

1 2
680nF
250V
/OTW
3.3R

2
READY

2
10uH
1 2
OUT_RIGHT_M
PVDD

1
1.5R 1000uF
2 1 63V
R31

2
2

2
100nF 100nF
C89 C84 GND
GVDD (+12V)

1
GND

Figure 18. Typical Differential Input BTL Application With BD Modulation Filters, DKD Package

20 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated

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 TAS5631B
www.ti.com SLES263C – NOVEMBER 2010 – REVISED SEPTEMBER 2012

THEORY OF OPERATION

POWER SUPPLIES
To facilitate system design, the TAS5631B needs only a 12-V supply in addition to the (typical) 50-V power-stage
supply. An internal voltage regulator provides suitable voltage levels for the digital and low-voltage analog
circuitry. Additionally, all circuitry requiring a floating voltage supply, e.g., the high-side gate drive, is
accommodated by built-in bootstrap circuitry requiring only an external capacitor for each half-bridge.
To provide outstanding electrical and acoustical characteristics, the PWM signal path, including gate drive and
output stage, is designed as identical, independent half-bridges. For this reason, each half-bridge has separate
gate-drive supply pins (GVDD_X), bootstrap pins (BST_X), and power-stage supply pins (PVDD_X).
Furthermore, an additional pin (VDD) is provided as a supply for all common circuits. Although supplied from the
same 12-V source, it is highly recommended to separate GVDD_A, GVDD_B, GVDD_C, GVDD_D, and VDD on
the printed-circuit board (PCB) by RC filters (see application diagram for details). These RC filters provide the
recommended high-frequency isolation. Special attention should be paid to placing all decoupling capacitors as
close to their associated pins as possible. In general, inductance between the power supply pins and decoupling
capacitors must be avoided. (See reference board documentation for additional information.)
For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin
(BST_X) to the power-stage output pin (OUT_X). When the power-stage output is low, the bootstrap capacitor is
charged through an internal diode connected between the gate-drive power-supply pin (GVDD_X) and the
bootstrap pin. When the power-stage output is high, the bootstrap capacitor potential is shifted above the output
potential and thus provides a suitable voltage supply for the high-side gate driver. In an application with PWM
switching frequencies in the range from 300 kHz to 400 kHz, it is recommended to use 33-nF ceramic capacitors,
size 0603 or 0805, for the bootstrap supply. These 33-nF capacitors ensure sufficient energy storage, even
during minimal PWM duty cycles, to keep the high-side power stage FET (LDMOS) fully turned on during the
remaining part of the PWM cycle.
Special attention should be paid to the power-stage power supply; this includes component selection, PCB
placement, and routing. As indicated, each half-bridge has independent power-stage supply pins (PVDD_X). For
optimal electrical performance, EMI compliance, and system reliability, it is important that each PVDD_X pin is
decoupled with a 2.2-μF ceramic capacitor placed as close as possible to each supply pin. It is recommended to
follow the PCB layout of the TAS5631B reference design. For additional information on recommended power
supply and required components, see the application diagrams in this data sheet.
The 12-V supply should be from a low-noise, low-output-impedance voltage regulator. Likewise, the 50-V power-
stage supply is assumed to have low output impedance and low noise. The power-supply sequence is not critical
as facilitated by the internal power-on-reset circuit. Moreover, the TAS5631B is fully protected against erroneous
power-stage turnon due to parasitic gate charging. Thus, voltage-supply ramp rates (dV/dt) are non-critical within
the specified range (see the Recommended Operating Conditions table of this data sheet).

SYSTEM POWER-UP/POWER-DOWN SEQUENCE

Powering Up
The TAS5631B does not require a power-up sequence. The outputs of the H-bridges remain in a high-
impedance state until the gate-drive supply voltage (GVDD_X) and VDD voltage are above the undervoltage
protection (UVP) voltage threshold (see the Electrical Characteristics table of this data sheet). Although not
specifically required, it is recommended to hold RESET in a low state while powering up the device. This allows
an internal circuit to charge the external bootstrap capacitors by enabling a weak pulldown of the half-bridge
output.

Powering Down
The TAS5631B does not require a power-down sequence. The device remains fully operational as long as the
gate-drive supply (GVDD_X) voltage and VDD voltage are above the undervoltage protection (UVP) voltage
threshold (see the Electrical Characteristics table of this data sheet). Although not specifically required, it is a
good practice to hold RESET low during power down, thus preventing audible artifacts including pops or clicks.

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ERROR REPORTING
The SD, OTW, OTW1, and OTW2 pins are active-low, open-drain outputs. Their function is for protection-mode
signaling to a PWM controller or other system-control device.
Any fault resulting in device shutdown is signaled by the SD pin going low. Likewise, OTW and OTW2 go low
when the device junction temperature exceeds 125°C and OTW1 goes low when the junction temperature
exceeds 100°C (see the following table).

OTW2,
SD OTW1 DESCRIPTION
OTW
0 0 0 Overtemperature (OTE) or overload (OLP) or undervoltage (UVP)
Overload (OLP) or undervoltage (UVP). Junction temperature higher than 100°C (overtemperature
0 0 1
warning)
0 1 1 Overload (OLP) or undervoltage (UVP)
1 0 0 Junction temperature higher than 125°C (overtemperature warning)
1 0 1 Junction temperature higher than 100°C (overtemperature warning)
1 1 1 Junction temperature lower than 100°C and no OLP or UVP faults (normal operation)

NOTE
Aasserting RESET low forces the SD signal high, independent of faults being present. TI
recommends monitoring the OTW signal using the system microcontroller and responding
to an overtemperature warning signal by, e.g., turning down the volume to prevent further
heating of the device resulting in device shutdown (OTE).

To reduce external component count, an internal pullup resistor to 3.3 V is provided on both SD and OTW
outputs. Level compliance for 5-V logic can be obtained by adding external pullup resistors to 5 V (see the
Electrical Characteristics table of this data sheet for further specifications).

DEVICE PROTECTION SYSTEM

The TAS5631B contains advanced protection circuitry carefully designed to facilitate system integration and ease
of use, as well as to safeguard the device from permanent failure due to a wide range of fault conditions such as
short circuits, overload, overtemperature, and undervoltage. The TAS5631B responds to a fault by immediately
setting the power stage in a high-impedance (Hi-Z) state and asserting the SD pin low. In situations other than
overload and overtemperature error (OTE), the device automatically recovers when the fault condition has been
removed, i.e., the supply voltage has increased.
The device functions on errors, as shown in the following table.

BTL Mode PBLT Mode SE Mode

Local Error In Turns Off Local Error In Turns Off Local Error In Turns Off
A A A
A+B A+B
B B B
A+B+C+D
C C C
C+D C+D
D D D

Bootstrap UVP does not shut down according to the table; it shuts down the respective half-bridge.

NOTE
In PBTL mode the device is protected against overload and load shorts, but shorting to
GND or PVDD during high load is not recommended

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PIN-TO-PIN SHORT-CIRCUIT PROTECTION (PPSC)

The PPSC detection system protects the device from permanent damage if a power output pin (OUT_X) is
shorted to GND_X or PVDD_X. For comparison, the OC protection system detects an overcurrent after the
demodulation filter, whereas PPSC detects shorts directly at the pin before the filter. PPSC detection is
performed at startup, i.e., when VDD is supplied; consequently, a short to either GND_X or PVDD_X after
system startup does not activate the PPSC detection system. When PPSC detection is activated by a short on
the output, all half-bridges are kept in a Hi-Z state until the short is removed; the device then continues the start-
up sequence and starts switching. The detection is controlled globally by a two-step sequence. The first step
ensures that there are no shorts from OUT_X to GND_X; the second step tests that there are no shorts from
OUT_X to PVDD_X. The total duration of this process is roughly proportional to the capacitance of the output LC
filter. The typical duration is <15 ms/μF. While the PPSC detection is in progress, SD is kept low, and the device
does not react to changes applied to the RESET pin. If no shorts are present, the PPSC detection passes, and
SD is released. A device reset does not start a new PPSC detection. PPSC detection is enabled in BTL and
PBTL output configurations; the detection is not performed in SE mode. To make sure not to trip the PPSC
detection system, it is recommended not to insert resistive load between OUT_X and GND_X or PVDD_X.

OVERTEMPERATURE PROTECTION
The two different package options have individual overtemperature protection schemes.

PHD Package
The TAS5631B PHD package option has a three-level temperature-protection system that asserts an active-low
warning signal (OTW1) when the device junction temperature exceeds 100°C (typical), (OTW2) when the device
junction temperature exceeds 125°C (typical) and, if the device junction temperature exceeds 155°C (typical), the
device is put into thermal shutdown, resulting in all half-bridge outputs being set in the high-impedance (Hi-Z)
state and SD being asserted low. OTE is latched in this case. To clear the OTE latch, RESET must be asserted.
Thereafter, the device resumes normal operation. For highest reliability, the RESET should not be asserted until
OTW1 has cleared.

DKD Package
The TAS5631B DKD package option has a two-level temperature-protection system that asserts an active-low
warning signal (OTW) when the device junction temperature exceeds 125°C (typical) and, if the device junction
temperature exceeds 155°C (typical), the device is put into thermal shutdown, resulting in all half-bridge outputs
being set in the high-impedance (Hi-Z) state and SD being asserted low. OTE is latched in this case. To clear the
OTE latch, RESET must be asserted. It is recommended to wait until OTW has cleared before asserting RESET.
Thereafter, the device resumes normal operation.

UNDERVOLTAGE PROTECTION (UVP) AND POWER-ON RESET (POR)

The UVP and POR circuits of the TAS5631B fully protect the device in any power-up/down and brownout
situation. While powering up, the POR circuit resets the overload circuit (OLP) and ensures that all circuits are
fully operational when the GVDD_X and VDD supply voltages reach values stated in the Electrical
Characteristics table. Although GVDD_X and VDD are independently monitored, a supply-voltage drop below the
UVP threshold on any VDD or GVDD_X pin results in all half-bridge outputs immediately being set in the high-
impedance (Hi-Z) state and SD being asserted low. The device automatically resumes operation when all supply
voltages have increased above the UVP threshold.

DEVICE RESET
When RESET is asserted low, all power-stage FETs in the four half-bridges are forced into a high-impedance
(Hi-Z) state.
In BTL modes, to accommodate bootstrap charging prior to switching start, asserting the reset input low enables
weak pulldown of the half-bridge outputs. In the SE mode, the output is forced into a high-impedance state when
asserting the reset input low. Asserting the reset input low removes any fault information to be signaled on the
SD output, i.e., SD is forced high. A rising-edge transition on the reset input allows the device to resume
operation after an overload fault. To ensure thermal reliability, the rising edge of reset must occur no sooner than
4 ms after the falling edge of SD.

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Product Folder Links: TAS5631B
TAS5631B
SLES263C – NOVEMBER 2010 – REVISED SEPTEMBER 2012 www.ti.com

SYSTEM DESIGN CONSIDERATIONS

A rising-edge transition on the reset input allows the device to execute the startup sequence and start switching.
Apply only audio when the state of READY is high; that starts and stops the amplifier without having audible
artifacts that are heard in the output transducers. If an overcurrent protection event is introduced, the READY
signal goes low; hence, filtering is needed if the signal is intended for audio muting in non-microcontroller
systems.
The CLIP signal indicates that the output is approaching clipping. The signal can be used either to activate a
volume decrease or to signal an intelligent power supply to increase the rail voltage from low to high for optimum
efficiency.
The device inverts the audio signal from input to output.
The VREG pin is not recommended to be used as a voltage source for external circuitry.

Click and Pop in SE-Mode

The BTL startup has low click and pop due to the trimmed output dc offset, see the AUDIO CHARACTERISTICS
(BTL) table.
The startup of the BTL+2 x SE system (Figure 17) or 4xSE (Figure 16) is more difficult to get click and pop free,
than the pure BTL solution; therefore, evaluating the resulting click and pop before designing in the device is
recommended.

PBTL Overload and Short Circuit

The TAS5631B has extensive overload and short circuit protection. In BTL and SE mode, it is fully protected
against speaker terminal overloads, and terminal-to-terminal short circuit, and short circuit to GND or PVDD. The
protection works by limiting the current, by flipping the state of the output MOSFET’s; thereby, ramping currents
down in the inductor. This only works when the inductor is NOT saturated, the recommended minimum inductor
values are listed in RECOMMENDED OPERATING CONDITIONS table. In BTL mode, the short circuit currents
can reach more than 15A, so when connecting the device in PBTL mode (Mono), the currents double – that is
more than 30 A, and with these high currents, the protection system will limit PBTL speaker overloads, terminal-
to-terminal shorts, and terminal-to-GND shorts. PBTL mode short circuit to PVDD is not recommended.

PRINTED CIRCUIT BOARD RECOMMENDATION

Use an unbroken ground plane to have good low-impedance and -inductance return path to the power supply for
power and audio signals. PCB layout, audio performance and EMI are linked closely together. The circuit
contains high, fast-switching currents; therefore, care must be taken to prevent damaging voltage spikes. Routing
for the audio input should be kept short and together with the accompanying audio source ground. It is important
to keep a solid local ground area underneath the device to minimize ground bounce. It is always good practice to
follow the EVM layout as a guideline,
Netlist for this printed circuit board is generated from the schematic in Figure 15.

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 TAS5631B
www.ti.com SLES263C – NOVEMBER 2010 – REVISED SEPTEMBER 2012

Note T1: PVDD decoupling bulk capacitors C60–C64 should be as close as possible to the PVDD and GND_X pins;
the heat sink sets the distance. Wide traces should be routed on the top layer with direct connection to the pins and
without going through vias. No vias or traces should be blocking the current path.
Note T2: Close decoupling of PVDD with low-impedance X7R ceramic capacitors is placed under the heat sink and
close to the pins. This is valid for C60, C61, C62, and C63.
Note T3: Heat sink must have a good connection to PCB ground.
Note T4: Output filter capacitors must be linear in the applied voltage range, and preferably metal film types.

Figure 19. Printed Circuit Board – Top Layer

Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback 25

Product Folder Links: TAS5631B
TAS5631B
SLES263C – NOVEMBER 2010 – REVISED SEPTEMBER 2012 www.ti.com

Note B1: It is important to have a direct, low-impedance return path for high current back to the power supply. Keep
impedance low from top to bottom side of PCB through a lot of ground vias.
Note B2: Bootstrap low-impedance X7R ceramic capacitors placed on bottom side provide a short low-inductance
current loop.
Note B3: Return currents from bulk capacitors and output filter capacitors

Figure 20. Printed Circuit Board – Bottom Layer

26 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated

Product Folder Links: TAS5631B

 TAS5631B
www.ti.com SLES263C – NOVEMBER 2010 – REVISED SEPTEMBER 2012

REVISION HISTORY

Changes from Original (October 2010) to Revision A Page

• Changed Title From: 600-W MONO To 400-W MONO ........................................................................................................ 1

• Changed Feature From: 600 W per Channel in Mono PBTL Configuration To: 400 W per Channel in Mono PBTL
Configuration ......................................................................................................................................................................... 1
• Changed the DKD package to Product Preview ................................................................................................................... 2
• Changed the Mode Selection Pins table .............................................................................................................................. 3
• Replaced the PACKAGE HEAT DISSIPATION RATINGS table with the Thermal Information table .................................. 3
• Changed TAS5631BDKD From: Product Preview To; Active .............................................................................................. 3
• Added PVDD_X to GND_X; DC voltage to the Abs Max Table ........................................................................................... 4
• Changed the Abs Max storage Temperature From: –40 to 150 To: –40 to 125 .................................................................. 4
• Added footnotes to the ROC table ........................................................................................................................................ 4
• Changed RL(PBLT) Min value From: 1.8 To 2.4 Ω, Typ Value From: 2 To 3 Ω ................................................................... 4
• Added ROCP information to the ROC Table ........................................................................................................................... 4
• Changed the description of Pins PVDD_A, PVDD_B, PVDD_C, PVDD_D ......................................................................... 5
• AUDIO CHARACTERISTICS (BTL) table -Changed LDEM = 7 μH, to 10 µH (Conditions statement). Changed |VOS|
values From Typ = 20 Max = 50 To: Typ = 15 MAx = 40. Changed Pidle test conditions From: PO = 0 To: PO = 4 ............. 8
• Changed AUDIO CHARACTERISTICS (BTL), |VOS| - From: Typ = 20 MAx = 50 To: Typ = 15 Max = 40 .......................... 8
• Changed AUDIO CHARACTERISTICS (BTL), PIdle - PO = 4, four channels To: PO = 0, all channels ................................. 8
• Changed LDEM = 7 μH To: LDEM = 10 μH in the AUDIO SPECIFICATION (Single-Ended Output) conditions
statement .............................................................................................................................................................................. 8
• Electrical Characterics - Changed Vuvp,G Typ value From: 10 To: 9.5, changed the IOC Test Conditions, Deleted IOCT .... 10
• Changed IOC Typical valuesFrom: 19A To: 15A ................................................................................................................. 10
• Changed the TYPICAL CHARACTERISTICS, BTL CONFIGURATION graphs ................................................................ 11
• Changed the TYPICAL CHARACTERISTICS, BTL CONFIGURATION graphs ................................................................ 12
• Replaced the TYPICAL CHARACTERISTICS, PBTL CONFIGURATION graphs ............................................................. 14
• Changed the PVDD CAPACITOR RECOMMENDATION section ...................................................................................... 15
• DECOUPLING CAPACITOR RECOMMENDATION section - Changed From: 0.1-μF capacitor To: 2.2-μF capacitor ..... 15
• Changed Figure 14, Figure 15, Figure 16, Figure 17, and Figure 18 ................................................................................. 16
• Added Note to the DEVICE PROTECTION SYSTEM section ........................................................................................... 22
• Added section - Click and Pop in SE-Mode ....................................................................................................................... 24
• Added section - PBTL Overload and Short Circuit ............................................................................................................. 24

Changes from Revision A (November 2010) to Revision B Page

• ChangedRINT_PU parameters From: OTW1 to VREG, OTW2 to VREG, SD to VREG To: OTW, OTW1, OTW2, CLIP,
READY, SD to VREG ......................................................................................................................................................... 10
• Added text to the PHD Package section ............................................................................................................................ 23
• Added text to the DKD Package section ............................................................................................................................ 23

Changes from Revision B (November 2011) to Revision C Page

• Deleted - RL = 2 Ω, 10%, THD+N, clipped input signal From PO in the Audio Specification (PBTL) table .......................... 9

Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback 27

Product Folder Links: TAS5631B
 PACKAGE OPTION ADDENDUM

www.ti.com 28-Feb-2019

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

TAS5631BDKD ACTIVE HSSOP DKD 44 29 Green (RoHS CU NIPDAU Level-4-260C-72 HR 0 to 70 TAS5631B

& no Sb/Br)
TAS5631BDKDR ACTIVE HSSOP DKD 44 500 Green (RoHS CU NIPDAU Level-4-260C-72 HR 0 to 70 TAS5631B
& no Sb/Br)
TAS5631BPHD ACTIVE HTQFP PHD 64 90 Green (RoHS CU NIPDAU Level-4-260C-72 HR 0 to 70 TAS5631B
& no Sb/Br)
TAS5631BPHDR ACTIVE HTQFP PHD 64 1000 Green (RoHS CU NIPDAU Level-4-260C-72 HR 0 to 70 TAS5631B
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 28-Feb-2019

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 14-Feb-2019

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TAS5631BDKDR HSSOP DKD 44 500 330.0 24.4 14.7 16.4 4.0 20.0 24.0 Q1
TAS5631BPHDR HTQFP PHD 64 1000 330.0 24.4 17.0 17.0 1.5 20.0 24.0 Q2

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 14-Feb-2019

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TAS5631BDKDR HSSOP DKD 44 500 350.0 350.0 43.0
TAS5631BPHDR HTQFP PHD 64 1000 350.0 350.0 43.0

Pack Materials-Page 2
 GENERIC PACKAGE VIEW
PHD 64 HTQFP - 1.20 mm max height
14 x 14, 0.8 mm pitch QUAD FLATPACK

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4224851/A

www.ti.com
 PACKAGE OUTLINE
PHD0064B HTQFP - 1.2 mm max height
PLASTIC QUAD FLATPACK
14.05
13.95 B
NOTE 3
PIN 1 ID
8.00
64 6.68 49

48
1
THERMAL PAD
4

14.05 8.00 16.15

13.95 6.68 15.85
NOTE 3 TYP

16
33
17 32

A 60 X 0.8 64 X 0.40
0.30
4 X 12 0.2 C A B

SEE DETAIL A
C
1.2 MAX
SEATING PLANE
(0.127) TYP

17 32

16 33

0.25
GAGE PLANE
(1)
0°-7°

0.15
0.75 0.05
0.1 C
0.45

DETAIL A
TYPICAL
1 48

64 49 4224850/A 05/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed
0.15 per side.
4. See technical brief. PowerPad Thermally Enhanced Package, Texas Instruments Literature No. SLMA002
(www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004) for information regarding recommended board layout.

www.ti.com
 EXAMPLE BOARD LAYOUT
PHD0064B HTQFP - 1.2 mm max height
PLASTIC QUAD FLATPACK
SYMM

64 49

64 X (1.5)

1
48

64 X (0.55)

60 X (0.8)

SYMM
(15.4)

33
(R0.05) TYP 16

17 32
(15.4)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 6X

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

METAL SOLDER MASK

OPENING
EXPOSED
EXPOSED METAL
METAL
SOLDER MASK METAL UNDER
OPENING SOLDER MASK
NON SOLDER MASK SOLDER MASK
DEFINED DEFINED

SOLDER MASK DETAILS 4224850/A 05/2019

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
7. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged
or tented.

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 EXAMPLE STENCIL DESIGN
PHD0064B HTQFP - 1.2 mm max height
PLASTIC QUAD FLATPACK

SYMM

64 49

64 X (1.5)

1
48

64 X (0.55)

60 X (0.8)

SYMM
(15.4)

33
(R0.05) TYP 16

17 32
(15.4)

SOLDER PASTE EXAMPLE

SCALE: 6X

4224850/A 05/2019

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.

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