Multiplication acceleration through booth’s and
modified booth’s multiplier
G.Himasaila(17495a0410)
G.Renuka(17495a0409)
P.Sravani(17495a0412)
G.Anusha(16491a04i7)
Abstract— A binary multiplier is a combinational logic
circuit used in digital systems to perform the multiplication of two
binary numbers. These are most commonly used in various
applications especially in the field of digital signal processing to
perform the various algorithms. Commercial applications like
computers, mobiles, high speed calculators and some general purpose
processors require binary multipliers. Compared with addition and
subtraction, multiplication is a complex process. In multiplication
process, the number which is to be multiplied by the other number is
called as multiplicand and the number multiplied is called as
multiplier. Similar to the multiplication of decimal numbers, binary
multiplication follows the same process for producing a product
result of the two binary numbers. The binary multiplication is much
easier as it contains only 0s and 1s
I. INTRODUCTION
As in decimal system, the multiplication of binary
numbers is carried out by multiplying the
multiplicand by one bit of the multiplier at a time and
the result of the partial product for each bit is placed
in such a manner that the LSB is under the
corresponding multiplier bit.
Finally the partial products are added to get the
complete product. The placement of the binary point
in the product of two binary numbers having
fractional representation is determined in the same
way as in the product of decimal numbers with
fractional representation. The total number of places
after the binary point in the multiplicand and the
multiplier is counted.
The binary point in the product is then placed before
this total number of places counted from right. It
should be noted that a multiplication by zero makes
Under the Guidance of
T. Sriram murthy M.Tech,(ph.D)
Asistant Professor, Department of ECE
QIS College of Engg and technology
ongole, A.P.,India
srirama.talakola@gmail.com
all the bits of the partial product zero and may thus be
ignored in intermediate steps.
Also, a multiplication by 1 leaves the bits of
multiplicand unchanged but shifts it towards the left
by one bit position. The multiplication of binary
numbers becomes more convenient by carrying out
intermediate sums of partial products.
In the case of binary multiplication there are certain
advantages. The multiplication is actually the
addition of multiplicand with itself after some
suitable shift depending upon the multiplier. Thus
multiplication is actually a process of shifting and
adding. This process is to be continued until the
shifting due to MSB of the multiplier is done and
final addition is made.
This scheme has several drawbacks:
i) The total area of the multipliers would increase,
since several multiplier units are used.
ii) The use of several multipliers increases the fan out
of the signals that drive the inputs of the multipliers
.Higher fan out means longer delays and/or higher
power dissipation.
iii) There would be a need for multiplexers that
connect the active multiplier to the Result route.
These disadvantages can be overcome by using
booths and modified booths algorithm.
II. EXISTING APPROACH
4*4 multiplier:
This multiplier carries out the multiplication in two
steps.
First is four 2 by 2 bit multiplications carried out,
creating four partial 4-bit products. The four 4-bit
partial products are added together to create the final
8-bit product. With this method is the hardware cost
kept low to implement the multiplier. Also the work
to implement the multiplier can be kept low, since
only three different types of non-complex blocks are
needed to be used to build up the entire multiplier.
8*8 MULTIPLIER: 00000010 00111100
An 8X8 multiplier is to be designed using Verilog. The 7 No 00000001 00011110
multiplier accepts two 8-bit numbers; multiplicand and
multiplier and results in 16-bit multiplication. The design is to operation
be optimised for speed.
00000001 00011110
Wallace tree multiplier is made up of mainly two components,
namely, half-adder and full-adder. So firstly, a half-adder and 8 No 00000000 10001111
a full-adder are designed. For constructing an 8X8 multiplier,
operation
we need 8 half-adders and 48 full-adders i.e. a total of 56
adders. Hence, the half adder and the full adder is instantiated 00000000 10001111
for each computation as per the requirement by passing the
appropriate parameters. The final result is obtained from the
sum and carry bits of the adder. 0000000010001111 = 27 x 2 3 x22 x21 =143 (11*13=143)
Modified Booth Algorithm:
III PROPOSED METHODS For requirements of smaller area occupation and
faster operation, Modified Booth’s algorithm is practically
used .This encoding algorithm is suitable for 2’s
In order to overcome the disadvantages in normal multiplier complementary and signed number multiplication.
there are two methods are proposed those are…. Multiplication by modified booth algorithm reduces the
1.Booth’s algorithm number of partial products to half when compared to general
2.Modified booth’s algorithm multiplication.
Booth Multiplication Algorithm: Bits xi and xi-1 recoded into yi and yi-1 - xi-2 serves as
reference bit
Booth's multiplication algorithm is a multiplication Separately - xi-2 and xi-3 recoded into yi-2 and yi-3 - xi-4
algorithm that multiplies two signed binary numbers in two's serves as reference bit
Groups of 3 bits each overlap - rightmost being x1 x0 (x-1),
complement notation. next x3 x2 (x1), and so on
Let us consider an example with two unsigned numbers 11*13
11---------- 00001011(m) subtraction => a<=a-m (if 10)
13---------- 00001101(q) addition=> a<=a+m (if 01)
No Operations Accumulator Multiplier(q)
of done content(a) 00001101
steps 00000000
1 subtraction 11110101 00001101
Right shift 11111010 10000110
2 addition 00000101 10000110
Right shift 00000010 11000011
3 sub 11110111 11000011
Right shift 11111011 11100001
4 No 11111101 11110000
operation
11111101 11110000
5 addition 00001000 11110000
Right shift 00000100 01111000
6 No 00000010 00111100
operation
 IV MERITS & DEMERITS VII COMPARISION TABLE
Merits:
Booth multiplier:
 Can perform both signed and unsigned multiplication
 Consumes less power than 8 bit multiplier
Type of Multiplier Time consumption
Modified booth multiplier:
 It can overcome the disadvantages of booths 4*4 multiplier 16ns
algorithm.
 It can perform both signed and unsigned 8*8 multiplier 4.283 ns
multiplication.
 It can perform multiplication up to 16 bit. Booths multiplier 4.08ns
Demerits:
Booth multiplier: Modified booths multiplier 3.235ns
 due to general both algorithm hard multiplier are
generated.
 For lower radix multiplier this booth algorithm yields APPENDIX A
 Correct results but,,if we go for higher radix this
algorithm yields wrong output.
 So we go for modified booth algorithm. Source codes:
Modified booth multiplier:
 For un signed higher radix multipliers this modified Booths multiplier:
booth algorithm works properly. but we go for
higher radix signed multipliers this modified booth module multiplier(prod, busy, mc, mp, clk, start);
algorithm does not work properly and produces hard output [15:0] prod;
multiples. output busy;
input [7:0] mc, mp;
input clk, start;
reg [7:0] A, Q, M;
V FUTURE SCOPE reg Q_1;
reg [3:0] count;
In this project we are not reducing any partial products. So, in wire [7:0] sum, difference;
feature we can reduce partial products by adding extra
circuitry.
always @(posedge clk) begin if (start) begin
A <= 8'b0;
VI CONCLUSION M <= mc;
Q <= mp;
The modified booth technique allows for flexible architectural Q_1 <= 1'b0;
solutions, where the variation in operand bit width can be used count <= 4'b0;
to decrease power dissipation and to increase throughput of end
multiplications. else begin
The booth algorithm is particularly suitable for a case ({Q[0], Q_1})
modified booth implementation. Due to the simplicity of this 2'b0_1 : {A, Q, Q_1} <= {sum[7], sum, Q};
algorithm, only minor modifications are needed to comply 2'b1_0 : {A, Q, Q_1} <= {difference[7], difference,
with the modified booth technique. This makes for an efficient Q};
modified booths implementation, capable of both signed and default: {A, Q, Q_1} <= {A[7], A, Q};
unsigned multiplications. endcase
count <= count + 1'b1;
end
end

alu adder (sum, A, M, 1'b0);

 alu subtracter (difference, A, ~M, 1'b1); p=p+ans;
end
assign prod = {A, Q}; -1:
assign busy = (count < 8); begin
ans=~a+1;
endmodule ans=ans<<(i-1);
p=p+ans;
assign out = a + b + cin; end
endmodule -2:
begin
modified booths multiplier: ans=a<<1;
ans=~ans+1;
module MBA_module(p,a,b,clock); ans=ans<<(i-1);
output [15:0] p; p=p+ans;
input [7:0] a, b; end
input clock; endcase
reg [15:0] p,ans; end
end
integer i, lookup_tbl; endmodule
integer operate;
BIBLIOGRAPHY
initial
begin
p=16'b0; Currently a lot of research is done on reconfigurable
ans=16'b0;
end architectures, where the architecture can be adapted to the
applications to be executed. Some of these proposed
always @(negedge clock)
begin architectures can adapt their arithmetic logic units to operate
p=16'b0; with different bit width, depending on the application.
for(i=1;i<=7;i=i+2)
begin 1. https://www.slideshare.net/saikiranpanjala/design-
if(i==1) and-simulation-of-different-8bit-multipliers-using-
lookup_tbl = 0;
else verilog-code
lookup_tbl = b[i-2];
lookup_tbl = lookup_tbl + 4*b[i] + 2*b[i-1];
2. http://murali-mm.blogspot.com/2014/06/4-bit-array-
if(lookup_tbl == 0 || lookup_tbl == 7) multiplier-verilog-code.html
operate = 0;
else if(lookup_tbl == 3 || lookup_tbl == 4) 3. https://www.slideshare.net/saikiranpanjala/design-
operate = 2; and-simulation-of-different-8bit-multipliers-using-
else
operate = 1; verilog-code
if(b[i] == 1) 4. https://www.edaboard.com/showthread.php?233431-
operate = -1*operate;
structural-8x8-bit-multiplier
case(operate)
1: https://www.youtube.com/watch?v=QFXaddi-Ag8
begin
ans=a;
ans=ans<<(i-1);
p=p+ans;
end
2:
begin
ans=a<<1;
ans=ans<<(i-1);