Scan Insertion & ATPG For Design Falcon for 28nm Technology

by using Synopsis Tool

ABSTRACT
DFT is a technique, which facilitates a design to become testable after fabrication. “Extra”logic which
we put along with the design logic during implementation process, which helps post-production testing.
Post-production testing is necessary because, the process of manufacturing is not 100% error free. DFT
is needed because for a company to reap profit, it needs to sell its products to customers and for the
customers to buy the product, the product needs to be reliable. So, for the product to be reliable, it
needs to be tested in depth to screen out defective ones. To test and screen out defective ones post-
silicon, test architecture needs to be implemented pre-silicon design. For any modern chip design with
a considerably large portion of logic, design for test (DFT) and in particular implementing scan test are
mandatory parts of the design process that helps to reduce the complexity of testing sequential circuits.
The basic concept of a scan test is to connect memory elements like flipflops or latches forming chains,
so that shifting through scan chains allows to control and observe the states of the DUT. Since scan
vectors are based on regular and uniform structures, basic knowledge about scan designs, scan test
modes and targeted fault models helps to interpret scan vectors. Therefore, in this project a scan test
features are added, so that a test engineer who debugs scan test on an ATE can be more efficient in a
first level of fault analysis - beyond just being able to do logging of failing pins and cycles.
In this project falcon I am going to perform Scan Insertion and DRC analysis for a design about 11k
flops using 28 nm technology with 2 clocks by defining all scan constraints and configurations and
performed DRC analysis by using DFT Compiler. For the design I also perform ATPG Drcs and Pattern
generation and simulations for Chain, Parallel and Serial simulations for Stuck-at Fault model using
Tetramax and VCSCompiler by using Synopsis Tool.
KEYWORDS:
Scan Insertion, Scan Drcs, ATPG Drcs, ATPG pattern generation, ATPG pattern simulations.