Circuits Syst Signal Process

DOI 10.1007/s00034-016-0431-3

A Low-Power and High-Gain Ultra-Wideband

Down-Conversion Active Mixer in 0.18-µm SiGe
Bi-CMOS Technology

Jun-Da Chen1 · Song-Hao Wang1

Received: 27 January 2016 / Revised: 19 September 2016 / Accepted: 21 September 2016

© Springer Science+Business Media New York 2016

Abstract This paper presents an ultra-wideband down-conversion mixer chip cover-

ing the frequency range from 3.1 to 10.6 GHz by using TSMC 0.18 µm SiGe BiCMOS
technology. The architecture used is based on Gilbert-cell mixer, the combination
of MOS transistors and HBT BJT transistor device characteristics. In the proposed
circuit, a LO CMOS series-parallel switched topology is adopted to reduce the supply
voltage and dc consumption for UWB system. The measured results of the proposed
mixer achieve: Gain = 9.8–10.6 dB, flatness = 0.8 dB, IIP3 = −8 dBm at 7.26 GHz,
and so on. Port-to-port isolations (LO–RF, LO–IF, and RF–IF) are better than about
−40 dB, and the total dc power consumption with output buffers is 4.3 mW from a
1 V supply voltage. The current output buffer is about 3.7 mW. The mixer topology
presented in this paper results suitable for low-power UWB system applications.

Keywords SiGe · BiCMOS · Gilbert-cell mixers · UWB · IIP3

1 Introduction

UWB wireless communication systems have been widely used in short distance
wireless local area networks, for high data rates. Ultra-wideband (UWB) technol-
ogy with target data range up to 480 Mb/s within 10-m communication distance
becomes more and more attractive. In 2002, the Federal Communications Commis-

B Jun-Da Chen
chenjd@nqu.edu.tw
Song-Hao Wang
kingaiiey123@yahoo.com.tw

1 Department of Electronic Engineering, National Quemoy University, University Road 1,

Jinning Township 892, Kinmen, Taiwan
 Circuits Syst Signal Process

Group 1 Group 2 Group 3 Group 4 Group 5

Band Band Band Band Band Band Band Band Band Band Band Band Band Band
#1 #2 #3 #4 #5 #6 #7 #8 #9 #10 #11 #12 #13 #14

3432 3960 4488 5016 5544 6072 6600 7128 7656 8184 8712 9240 9768 10296 MHz

Fig. 1 IEEE 802.15.3a spectrum

Antenna I-channel mixer Mixer

LPF VGA ADC
Balun
LPF VGA ADC
BPF Filter LNA LO 0 LO 180

Quad -VCO
RF
LO 90 LO 270
LPF VGA ADC
Balun
LPF VGA ADC
Q-channel mixer
Mixer

Fig. 2 A block diagram of the direct-conversion receiver including the proposed mixers

sion (FCC) made 3.1–10.6 GHz accessible for UWB applications. The multi-band
orthogonal frequency-division multiplexing (OFDM) UWB system operates across a
wide range of frequency band (3.1–5 or 3.1–10.6 GHz) to access data [2,10,23,25].
Two ultra-wideband (UWB) specifications, multi-band orthogonal frequency divi-
sion multiplexing (MB-OFDM) and direct-sequence code division multiple-access
(DS-CDMA), become an international standard for high-speed wireless personal area
networks (WPAN). According to the multi-band OFDM UWB specification, the UWB
spectrum is divided into 14 bands, which has 528 MHz bandwidth individually. Each
band has 128 OFDM sub-channels with a channel bandwidth of 4.125 MHz [25].
The band structure of the MB-OFDM UWB applications is shown in Fig. 1. The
focus of this research is to design a low-power direct-conversion down-conversion
mixer for an MB-OFDM UWB RF receiver, as shown in Fig. 2. The down-conversion
mixer can be passive or active. The main advantage of the passive mixer is higher
linearity. Unfortunately, it cannot provide a conversion gain and exhibits higher noise
figure. The traditional active mixer includes a single-balanced Gilbert-cell mixer and a
double-balanced Gilbert-cell mixer. Active mixers are usually preferred for monolithic
integration of these functions due to their high conversion gain over a broad frequency
band, and good port-to-port isolation [1,13,20]. The paper presents a novel topology
of active mixer. The architecture used is based on Gilbert-cell mixer, the combination
of MOS transistors and BJT transistors device characteristics using the TSMC 0.18 µm
SiGe BiCMOS process technology. Traditional SiGe HBT Gilbert-cell mixer shows
a high conversion gain over a broad frequency band, but it needs high supply volt-
age which then increases the power consumption. The specification is barely satisfied,
when the supply voltage is below 1 V. This paper describes a theoretical analysis of the
novel conversion gain of SiGe BiCMOS HBT based on the Gilbert mixer cell topology
Circuits Syst Signal Process

for low voltage operation which can operate at 1-V supply voltage and presents the
measured results.
In Sect. 2, the traditional SiGe HBT double-balanced down-conversion Gilbert-
cell mixer is reviewed. In Sect. 3, we present the wideband down-conversion mixer
design. In Sect. 4, the implementation and measured results are presented. Finally, the
conclusion is summarized in the last section.

2 Traditional SiGe HBT Double-Balanced Down-Conversion

Gilbert-Cell Mixers

Traditional SiGe HBT double-balanced Gilbert-cell mixer topologies can be divided

into two categories, namely, the double-balanced Gilbert-cell (GmSw) mixer [13] and
the double-balanced Gilbert-cell switched (SwGm) mixer [15]. In this section, the
advantages and disadvantages, as well as the design and optimization techniques for
the two different kinds of mixers, are presented. Figure 3 shows the main elements
of the SiGe HBT double-balanced Gilbert mixer, including transconductance stage
(Q 1 − Q 2 ), switching stage (Q 3 − Q 6 ), and the load stage [9]. The transconductance
stage converts the input voltage signal at the RF frequency into a current signal. To
accomplish high conversion gain, good linearity, and low noise, transistors (Q 1 − Q 6 )
are designed to operate in the forward-active region. The switching stage is driven by
a local oscillation signal (VLO ). The VLO sinusoidal waveform can be considered as a
square wave to drive ideal switches. The switching quad (Q 3 − Q 6 ) ideally multiplies
(Q 1 − Q 2 ) this current at the rate of the LO signal, which then enables the anticipated
frequency conversion. IRF is multiplied by an ideal square wave current ILO . IRF is
the current through the RF stage. ILO is the current through the LO stage. The output
current signal at the IF frequency from the switching quad is finally converted into a
voltage signal by the load circuit. The conversion gain of the mixer can be estimated
by

Fig. 3 SiGe HBT

double-balanced Gilbert-cell
VDD
Load stage
mixer (GmSw)
RL RL

IF+ -IF
Switching stage

LO+ Q3 Q4 Q5 Q6 +LO
VB1
LO-
RB
RF+ Q1 Q2 -RF

Transconductance stage
 Circuits Syst Signal Process

Fig. 4 SiGe HBT VDD

double-balanced switched Load stage
transconductor mixer (SwGm)
RL RL

IF+ -IF
Transconductance
stage

RF+ Q3 Q4 Q5 Q6 +RF
RB -RF
VB3
LO+ Q1 Q2 -LO

Switching stage

 
2
G ≈ 20 log gm RL (1)
π
ICQ1 β × IB1
gm = = (2)
VT VT
VB1 − VBE1
IB1 = (3)
RB
 
2 β × (VB1 − VBE1 )
G ≈ 20 log RL (4)
π VT RB

where gm is the transconductance of Q 1 and Q 2 , RL represents the load resistance,

ICQ1 is the collector current, VT is the thermal voltage, β is the common-emitter
current gain, IB1 is the Q 1 base bias current, VB1 is the Q 1 base bias voltage, and
RB is the Q 1 base bias resistor. The transconductance stage (Q 1 − Q 2 ) is operated in
the “forward-active” region which can act as a fairly linear amplifier. In this region,
VCE > 0.2–0.3 V, VBE  0.7 V, the collector current is proportional to the base
current. The supply voltage of the mixer can be obtained:

VDD = ICQ3 RL + VCE3 + VCE1 (5)

According to Eq. (5), transconductance stage (Q 1 − Q 2 ) is operated in the satura-

tion region when the supply voltage is below 1 V. Although this is possible in the
forward-active region, it is difficult to obtain bias conditions and an adequate level
of voltage swing under a restricted supply voltage. Thus, the traditional SiGe HBT
double-balanced Gilbert-cell mixer with 1 V supply voltage specification can not be
satisfied. The traditional SiGe HBT double-balanced Gilbert-cell switched transcon-
ductor (SwGm) mixer is shown in Fig. 4. The transconductance stage (Q 3 − Q 6 ) is
designed so the transistors can be operated in the forward-active region. Moreover,
switching stage (Q 1 − Q 2 ) is designed so the transistors can be operated in the satu-
ration region when the supply voltage is below 1 V. The (Q 1 − Q 2 ) transistor couple
Circuits Syst Signal Process

may be used as a switch. The conversion gain value of the mixer can be conservatively
estimated by
 
2
G≈ 20 log gm RL (6)
π
ICQ3 β × IB3
gm = = (7)
VT VT
VB3 − VBE3 − VCE1
IB3 = (8)
RB
VDD = ICQ3 RL + VCE3 + VCE1 (9)
 
2 β × (VB3 − VBE3 − VCE1 )
G≈ 20 log RL (10)
π VT RB

where gm is the transconductance of Q 3 and Q 4 , RL represents the load resistance,

ICQ3 is the Q 3 collector current, VT is the thermal voltage, β is the common-emitter
current gain, IB3 is the Q 3 base bias current, VB3 is the Q 3 base bias voltage, and
RB is the Q 3 base bias resistor. When the switching stage (Q 1 − Q 2 ) is in saturation
region, the transistors appear as a near short circuit between the collector and emitter
terminals. This implies that the correspondent VCE1 voltage is close to 0 V (<0.2 V).

VDD ∼
= ICQ3 RL + VCE3 (11)

Comparing Eqs. (5)–(11), on the Eq. (11) the supply voltage (VDD ) reduces a VCE1
voltage. The main advantage of the SiGe HBT Gilbert-cell switched transconductor
(SwGm) mixer is that it can work even with a supply voltage lower than 1 V. Comparing
Eqs. (4)–(10), on the Eq. (4) the conversion gain equation reduces a VBE3 voltage. The
conversion gain of the SiGe HBT Gilbert-cell (GmSw) mixer is higher than the SiGe
HBT Gilbert-cell switched transconductor (SwGm) mixer. The main advantage of the
SiGe HBT Gilbert-cell (GmSw) mixer is higher conversion gain with a supply voltage
more than 1 V. However, the main disadvantage of the SiGe HBT (GmSw) mixer is
that it can not work with a supply voltage lower than 1 V.

3 The Proposed SiGe HBT Mixer Analysis

A complete schematic of the proposed SiGe HBT series-parallel switched transcon-

ductor (SwGm) mixer is shown in Fig. 5. It consists of a switching stage (M1 − M8 ), a
transconductance stage (Q 1 − Q 4 ), and load stage (RL ). The design of the on transcon-
ductance stage is based on BJT (HBT) transistors to improve the conversion gain. The
rest of the circuit uses MOS transistors to reduce power consumption, so that this mixer
at the RF parameters has excellent performance properties. BJT (HBT) is a part of
the current control transistor. The main disadvantage of the BJT (HBT) must be input
to the base bias current. However, this process results in power consumption. BJT
(HBT)’s electrical properties include a high frequency response, high-current charac-
teristics, and low flicker noise [13]. The MOS transistor is the voltage control device.
 Circuits Syst Signal Process

Fig. 5 SiGe HBT

double-balanced switched Load stage VDD
series-parallel transconductor
mixer (SwGm) RL RL

IF+ -IF
Transconductance
stage

RF+ Q1 Q2 Q3 Q4 +RF
RB -RF
VB1
M5 M6 M7 M8
LO+ -LO
M1 M2 M3 M4

Switching stage

Fig. 6 A MOS transistor D

simplified triode region Cgd Cdb
small-signal model

rd B

Cgs S
Csb

It operates like a resistor, controlled by the gate voltage relative to both the source and
drain voltages. When in the stationary state, there are almost no gate current flows.
Therefore, the main advantage of the MOS transistor is that it has very low power
consumption. However, the main disadvantage of the MOS transistor is that it has
poor frequency response characteristics. When it operates at high frequency, the gain
effectiveness will deteriorate. The design of the mixer uses SiGe BiCMOS process
technology, whose characteristics combines the features from both BJT(HBT) and the
MOS. The transconductance stage (Q 1 − Q 4 ) is designed so the transistors can be
operated in the forward-active region. Moreover, the switching stage (M1 − M8 ) is
designed so the transistors can be operated between the OFF and triode region when
the supply voltage is below 1 V. Due to the choice of large W /L ratio for M5 − M8 ,
large sizes in M5 − M8 will produce great parasitic capacitance [3–6].
A MOS transistor simplified triode, as shown in Fig. 6. Cgs , is the gate to source
capacitance and Cgd is the gate to drain capacitance. The primary junction capacitances
of interest are the source–bulk, Csb , and drain–bulk, Cdb , capacitance. The intrinsic
capacitance value can be conservatively estimated as

 
εo εsio2
CO = WL (12)
tox
Circuits Syst Signal Process

Fig. 7 A MOS transistor D

simplified OFF region Cdb
small-signal model

G B

Cgb SCsb

where εo is the permittivity of free space, εsio2 is the dielectric constant, and tox is the
oxide thickness. WL is the area of the gate. Now, we consider junction capacitance
source-substrate and drain-substrate junction, Csb and Cdb , respectively. Due to the
bulk–source connection, the Csb will approximate zero. The drain–bulk capacitance
can be estimated as
Cdb = ADCJa + PDCjp (13)
where Cdb is the drain–bulk capacitance, AD is the area of the drain diffusion, CJa
is the drain–bulk capacitance per unit area under bias Vdb , PD is the perimeter of the
drain diffusion, and Cjp is the sidewall capacitance per unit length under bias Vdb .
According to Eqs. (12), (13), these capacitances are proportional to the width of the
transistor.
The MOS can be approximated as a linear resistor in triode region with a resistance
value inversely proportional to the excess gate voltage. The resistance value can be
conservatively expressed as
 
1 L
rds = (14)
μn Cox (VGS − Vth ) W

where rds is the small-signal drain–source resistance, Cox is the gate capacitance per
unit area. Based on the Eqs. (12), (13), (14) in the above descriptions, the choice
of large sizes in M5 − M8 will reduce resistance and produce a large capacitance.
When the transistor turns off, the model changes considerably. A reasonable model is
shown in Fig. 7. The biggest difference is that rds is Infinity. Another major difference
is that Cgs and Cgd are now much smaller. They will approximate zero. Cgb is the
gate to substrate capacitance. This capacitor is highly nonlinear and dependent on the
gate voltage. If the gate voltage has been very negative for some time and the gate is
accumulated, the Cgb capacitance value can be conservatively estimated as
 
εo εsio2
Cgb = C O = WL (15)
tox

Table 1 summarizes the approximate gate intrinsic capacitance values in two different
operating models [24]. According to the above description, a simplified series-parallel
switched triode region small-signal model is shown in Fig. 8. The parallel path will
reduce the resistance value by half and produce two times the capacitance value. A
simplified series-parallel switched OFF region small-signal model is shown in Fig. 9.
 Circuits Syst Signal Process

Table 1 Approximation of intrinsic MOS gate capacitance

Operation region Cgb Cgs Cgd Cg = Cgb + Cgs + Cgd

Cutoff Co 0 0 Co
Triode 0 Co /2 Co /2 Co

D M3=64/0.18
Cgd3 Cgd4 M1=8/0.18
M3/M1=8 18Cgd1
D
D D
Cdb3 rd4 Cdb3= G
rd3 Cgd3=8Cgd1 Cgd3=8Cgd1 16/9
8Cdb1 9/16 rds1
rds3 rds3 Cdb1
Cgs3=8Cgs1 =1/8rds1 Cdb3= Cgs3=8Cgs1 =1/8rds1
G Cgs3 Cgs4 8Cdb1 S
Cgd1 Cgd2 S S 18Cgs1
G D D
Cgd1 Cgd1 9Co
D
rd1 Cdb1 rd2 rds1 rds1
Cgs1 Cgs1
Cdb1 Cdb1 G 16/9
S S 9/16 rds1
Cgs1 S S Cdb1
Cgs2
S
9Co

Fig. 8 A simplified switched series-parallel triode region small-signal model

D M3=64/0.18
M1=8/0.18 D D
M3/M1=8 D
Cdb3=8Cdb1 Cdb4=8Cdb2 Cdb3=16Cdb1
Cdb3 Cdb4 Cdb3=16Cdb1
Cgb3=8Cgb1 Cgb4=8Cgb2 Cgb3=16Cgb1
Cgb3=16Co
Cgb3 Cgb4
G G G
Cdb1 Cdb2
Cgb2
2Cdb1 G
Cgb1 2Cgb1 2Cdb1
2Co
S S S
Cdb1 Cdb1 S

Cgb1 S S
Cgb2

Fig. 9 A simplified switched series-parallel OFF region small-signal model

Figure 10 shows the use of the series switching sinusoidal waveforms current ILO .
Figure 10a–c shows that the supply voltages of the simulated switching are 62.4,
63.6, and 48.5 mV, respectively. The parallel path will reduce the supply voltage of
the switching. Figure 10a, b shows the switching waveforms with and without M3 −
M4 .The circuit will discharge a negative current during the negative half cycle of the
input voltage in Fig. 10b. Figure 10a–c shows that the simulated switching waveforms
current ILO+ are 0.2, 0.4, and 0.8 mA, respectively. Comparing Fig. 10a, b, the current
ILO of the proposed series switching stage is two times higher than the single switching
stage. Comparing Fig. 10b, c, the current ILO of the proposed series-parallel switched
mixer will produce two times the current of the series switched mixer. In Fig. 5, we
can describe the RF signal as a sinusoidal wave VRF = ±vRF sin ωRF t and the LO
signal as a square wave local oscillator sq(ωLO t). An ideal square wave current ILO
alternates between +4 and −4. The conversion gain of the mixer can be approximated
by
Circuits Syst Signal Process

Frequency=3400 MHz M1-M2=8/0.18 M1-M4=8/0.18

LO Power=0dBm=0.223V M3-M4=64/0.18 M5-M8=64/0.18
Triode region DC 63.6mV DC 48.5mV
ILO+ ILO- ILO+ ILO-
M1=M2=8/0.18
DC 62.4 mV M3 M4 M5 M6 M7 M8
LO+ LO- LO+ LO-
ILO+ ILO- M1 M2
LO+ LO- DC 0.5V DC 0.5V DC 0.5V M1 M2 M3 M4 DC 0.5V
M1 M2
DC 0.5V DC 0.5V ILO ILO
ILO

1 1 1

-1 -1 -1
1 1 1

-1 -1 -1
1 1 2

-1 -1 -2
1 1 2

-1 -1 -2
1 2 4

-1 -2 -4
Without

(a) single switched stage (b) series switched stage (c) parallel-series switched stage

Fig. 10 Shows the use of the switching sinusoidal waveforms current ILO
 Circuits Syst Signal Process

VIF
G = 20 log (16)
VRF
VIF = IIF × Rload (17)

The intermediate-frequency (IIF ) current can be stand for by

  
IDC VRF
IQ1 = + gm × ILO (18)
4 4
  
IDC VRF
I Q2 = − gm × ILO (19)
4 4
  
IDC VRF
I Q3 = − gm × (−ILO ) (20)
4 4
  
IDC VRF
I Q4 = + gm × (−ILO ) (21)
4 4
       
IIF = IIF+ − IIF− = I Q1 + I Q3 − I Q2 + I Q4 = I Q1 − I Q2 − I Q4 − I Q3
(22)

The switching stage performs the mixing function which converts the RF signal down
to the IF as illustrated in the following equation:

IIF = gm VRF × ILO (23)

ILO = sq(ωLO t) (24)
IIF = gm vRF sin(ωRF t) × sq(ωLO t) (25)
  
4 1
IIF = gm vRF sin(ωRF t) × 4 × sin(ωLO t) + sin(3ωLO t) + · · · (26)
π 3
8
IIF = gm vRF [cos(ωRF − ωLO )t + cos(ωRF + ωLO )t + · · ·] (27)
π
8
IIF = gm vRF cos(ωRF − ωLO )t (28)
π

where gm the transconductance of Q 1 , ICQ1 is Q 1 collector current, and the sq(ωLO t)

is expanded as a Fourier series and the term containing the down-converted frequency
at (ωRF − ωLO ) is retained.

VB1 = IB1 RB + VBE1 + VDS5 + VDS1 (29)

VB1 − VBE1 − VDS5 − VDS1
IB1 = (30)
RB
ICQ1 β × IB1
gm = = (31)
VT VT

where VT is Q 1 thermal voltage, β is Q 1 common-emitter current gain, VB1 is Q 1

base bias voltage, RB is Q 1 base bias resistor, and IB1 is Q 1 base bias current.
Circuits Syst Signal Process

β × (VB1 − VBE1 − VDS5 − VDS1 )

gm = (32)
VT × RB

Thus, the IIF in Eq. (28) can be written

8 β (VB1 − VBE1 − VDS5 − VDS1 )

IIF = × × vRF cos(ωRF − ωLO )t (33)
π VT RB
8 β (VB1 − VBE1 − VDS5 − VDS1 )
VIF = × × Rload × VRF cos(ωRF − ωLO ) (34)
π VT RB

Due to the choice of large W /L ratio for M5 − M8 , the VDS5 will approximate zero
(VDS5 ∼= 0). Transconductance stage (Q 1 − Q 4 ) is operated in the forward-active
region when the supply voltage is below 1 V, and the conversion gain of the proposed
mixer can be approximated by
 
8 β (VB1 − VBE1 − VDS1 )
G∼
= 20 log × × R load (35)
π VT RB

Comparing Eqs. (10) and (35), the conversion gain of the proposed switched series-
parallel mixer is four times higher than the single switched (SwGm) mixer. The mixer
needs large power LO signal which is generated by the VCO. Therefore, the VCO
output power level is very important. We can express the LO signal as a approximated
sinusoidal wave local oscillator, the conversion gain of the proposed mixer can be
approximated by [22]

VIF 8 β (VB1 − VBE1 − VDS1 )
G novel ≈ = 20 log
VRF π VT RB
 √

2(VG − VDS1 − VTH )SW

× 1− RLoad (36)
π VLO

where VLO is the amplitude of the LO signal and (VG −VDS1 −VTH )SW is the over-drive
voltage of M1 − M8 .
The mixer is a common-mode structure circuit [8,15]. The noise current can be
eliminated in the differential voltage output. Therefore, the main advantage of the
mixer switching transistors 1/ f noise can be eliminated in the differential voltage
output.

4 Mixer Implementation and Measured Results

A complete schematic of the proposed mixer is presented in Fig. 11. The proposed
UWB mixer is implemented in the 1P6M 0.18 µm SiGe BiCMOS process. The mixer
consists of five major parts: transconductance stage (Q 1 − Q 4 ), switching stage (M1 −
M8 ), the load stage (M9 − M10 and R1 − R2 ), CMFB circuitry (M11 − M15 ), and
output buffer (M16 − M19 ). Transistors M11 through M15 serve as a CMFB circuit
to set up the common-mode voltage. With a sufficiently high loop gain, Vref and
 Circuits Syst Signal Process

M9 M10
M14 M15 M18 M19
Vload Vcont

M12 M13

R3 R4
Q1 Q2 Q3 Q4 M16 M17
M11

C1 L1 R5 M5 M6 M7 M8
R9 L3 C5
R7 R11
C2 C6
M1 M2 M3 M4

C3 L2 R6 R10 L4 C7
R8 R12
C4 C8

Fig. 11 Complete schematic of the proposed mixer

Fig. 12 The input matching

DC_BLOCK
networks of RF and LO L1
C1
Q1
RF+
R5 R7

C2
Vbias
DC_BLOCK
C5 L3 M5 M6

LO+ R9 M1 M2
R11
C6
Vbias

Vcont will be approximately equal [18]. The value of Vref is selected to optimize
the linearity and conversion gain. The Vref voltage is designated to be about 0.7 V.
Differential active PMOS transistor (M9 − M10 ) loads instead of resistive loads are
used here without sacrificing the voltage swing headroom. The resistive loads (R1 −R2 )
provides output impedance. The input matching networks of RF and LO are shown in
Fig. 12. The passive components metal–insulator–metal (MIM) capacitors (C1 − C2 ),
poly/diffusion resistor (R5 ), and spiral inductor (L 1 ) are adopted for matching the
network at the input RF stage to resonate over the entire frequency band. Furthermore,
we use one spiral inductor (L 3 ), one poly/diffusion resistor (R9 ), and MIM capacitors
(C5 − C6 ) to match the input LO stage to resonate over the entire frequency band.
The resistance R7 , R11 are added as a bias voltage resistance. Both RF and LO stage
impedances have a value of 50 . The buffer stage consisting of NMOS transistors
Circuits Syst Signal Process

Table 2 Pre-simulation device sizes of the proposed mixer

Device Design values Device Design values

Q N1 − Q N4 el = 10 µm, W = 0.2 µm, Base = 1 R7 − R8 1.51 K

MN1 − MN4 L = 0.18 µm, W = 2 µm, N = 4 R11 − R12 1.51 K
MN5 − MN8 L = 0.18 µm, W = 8 µm, N = 8 R5 − R6 93 
MP9 − MP10 L = 0.18 µm, W = 8 µm, N = 10 R9 − R10 100 
MN11 − MN13 L = 0.18 µm, W = 1.5 µm, N = 10 L1 − L2 1.35 nH
MP14 − MP15 L = 0.18 µm, W = 8 µm, N = 64 L3 − L4 1.35 nH
MN16 − MN17 L = 0.18 µm, W = 5 µm, N = 8 C1 , C3 1.99 pF
MN18 − MN19 L = 0.2 µm, W = 8 µm, N = 26 C2 , C4 2.85 pF
R1 − R2 4.13 K C5 , C7 1.99 pF
R3 − R4 1.51 K C6 , C8 2.85 pF

Fig. 13 Measured RF ports 0

return loss from 3 to 11 GHz Measured RF return loss
-5 Post-Simulated RF return loss
-10
-15
-20
dB

-25
-30
-35
-40
-45
-50
3 4 5 6 7 8 9 10 11
Frequency (GHz)

(M16 − M19 ) drive 50  loads for measurement. The device sizes of the mixer are
shown in Table 2.
Measurements of the differential RF/LO/IF signals were provided by the measure-
ment systems of the coplanar ground-signal-ground-signal-ground (GSGSG) 100 µm
pitch on-wafer probes. RF and LO ports use off-chip baluns for single-to-differential
conversion at the input signal. The supply and bias voltages are connected by 6-pin
power-ground-power-power-ground-power (PGPPGP) 100 µm pitch on-wafer probe.
The IF output differential signals were connected to a spectrum analyzer through two
off-chip DC blocking capacitors. The performance measurement of the UWB mixer
through on-wafer probe testing operates the LO signal with 0 dBm, RF signal with
−30 dBm. A fixed IF frequencies of 264 MHz were used and LO frequency was swept
from 3 to 11 GHz. The total dc power consumption with output buffers is 4.3 mW
from a 1V supply voltage. Both RF and LO port matching impedance is 50 . Fig-
ures 13 and 14 shows RF and LO ports return loss, from 3 to 11 GHz; the measured
return loss is less than −10 dB. Figure 15 shows the simulated conversion gain with
respect to the RF power. Figure 16 shows the measured conversion gain with respect
 Circuits Syst Signal Process

Fig. 14 Measured LO ports 0

return loss from 3 to 11 GHz Measured LO return loss
Post-Simulated LO return loss
-5

-10

dB
-15

-20

-25

-30
3 4 5 6 7 8 9 10 11
Frequency (GHz)

Fig. 15 Post-simulated TT 15
conversion gain versus RF 14
power with the IF frequency 13
Conversion Gain (dB)

264 MHz, LO power is 0 dBm, 12

TT represent the simulation 11
10
results of typical-NMOS 9
typical-PMOS 8 RF at 3GHz
7 RF at 5.4GHz
6 RF at 7.8GHz
5 RF at 10.2GHz
4
3
2
1
0
-32 -30 -28 -26 -24 -22 -20 -18 -16 -14 -12 -10 -8
RF Input Power (dBm)

Fig. 16 Measured conversion 11

gain versus RF power with the 10
IF frequency 264 MHz, LO
Conversion Gain (dB)

power is 0 dBm
9
8
7
6
5
4 RF at 3GHz
3 RF at 5.4GHz
2 RF at 7.8GHz
1 RF at 10.2GHz
0
-32 -30 -28 -26 -24 -22 -20 -18 -16 -14 -12 -10 -8
RF Input Power (dBm)
Circuits Syst Signal Process

Fig. 17 Conversion gain versus 14

RF power with the IF frequency
264 MHz, LO power is 0 dBm at 12

Conversion Gain (dB)

5.624 GHz. SS represents the 10
simulation results of
slow-NMOS and slow-PMOS 8
6
4
2 Post-Simulated TT
Measured
0 Post-Simulated SS
-2
-32 -30 -28 -26 -24 -22 -20 -18 -16 -14 -12 -10 -8
RF Input Power (dBm)

Fig. 18 Measured IIP3 at 10

7.26 GHz
0
Output Power (dBm)

-10
-20
-30
-40
Fundamental
-50
IMD3
-60
-70
-80
-35 -30 -25 -20 -15 -10 -5 0
RF Power (dBm)

to the RF power. As shown in this figure, the conversion gain displayed a 3-dB vari-
ation across the 3–11 GHz input frequency range. Figure 17 shows that measured
conversion gain was between TT and SS process corners. The plots of the measured
fundamental and third-order intermodulation output power versus input RF power at
7.26 GHz are shown in Fig. 18. IIP3 is −8 dBm. Figure 19 shows the measured port-
to-port isolations (LO–RF, LO–IF, and RF–IF) of better than about −40 dB from 3.1
to 10.6 GHz. The measured DSB NF is 12.2–14.1 dB from 3 to 11 GHz, as shown in
Fig. 20. Figure 21 shows the microphotograph of the fabricated circuit with a chip
area of 0.843 × 0.852 mm2 including the pad frames.
Table 3 summarizes the measurement results and compares published results. The
Gilbert-cell switched series transconductor (SwGm) mixer in [3,4] has been shown to
be effective in increasing conversion gain, and sufficient isolation under low voltage
supply. However, it only displays a narrowband response and is not suitable for UWB
system applications. The UWB Gilbert-cell switched series-parallel transconductor
(SwGm) mixer in [5] has been shown to be effective in increasing conversion gain under
low voltage supply. Comparing switched series stage to switched series-parallel stage,
 Circuits Syst Signal Process

Fig. 19 Measured port-to-port -35

isolation versus RF frequency
with RF of −30 dBm and LO of -40
0 dBm -45

Isolation (dB)
-50
LO-IF
-55
LO-RF
-60 RF-IF
-65
-70
-75
-80
3 4 5 6 7 8 9 10
Frequency (GHz)

Fig. 20 Measured and 15

simulated DSB noise versus RF Measured IF=264Mhz
frequency, LO power is 0 dBm, Post-Simulated IF=264Mhz
and RF power is −30 dBm 14
Noise Figure (dB)

13

12

11

10
3 4 5 6 7 8 9 10 11
RF Frequency (GHz)

Fig. 21 Chip microphotograph

(chip area of 0.843 × 0.852 mm2
including the pad frames)
Table 3 Performances of UWB mixers

References CMOS Freq. LO (dBm) Gain (dB) Gain IF (MHz) IIP3 NF (dB) Vsupply PDC (mW) Die area
Circuits Syst Signal Process

(µm) (GHz) flatness (dBm) (mm2 )

[3] 0.18 2.14 0 7 Narrow band 10 −2 10.4 (DSB) 1 2.2 1.22 × 1.22
[4] 0.18 5.25 0 7.6 Narrow band 10 3 11.4 (DSB) 1 2.45 1.22 × 1.17
[5] 0.18 3.4–8.4 0 6.5–9.5 ±3 10 −5 (7.4 GHz) 12.4–13.3 (DSB) 1 3.18 1.14 × 1.08
[6] 0.18 3.4–6.8 0 4.3–7.2 ±3 10 2–3 13.9–14.4 (DSB) 1 2.9 1.145 × 1.08
[16] 0.18 0.5–7.5 5 4.3–5.7 ±1.4 100 −5.7 15 0.77 0.48 0.86 × 0.72
[14] 0.18 2.1–12 5 6.9–9.9 ±3 264 −10 (10 GHz) 11.8-14 (DSB) 0.8 0.88 0.62 × 0.58
[19] 0.13 3.1–10.6 −3 9.8–14 ±4.2 264 −11 (10 GHz) 14–19.6 (DSB) 1.2 1.85 0.58 × 0.59
[17] 0.18 0.5–6 0 3.7–6.2 ±2.5 100 0 16–16.8 (SSB) 0.7 0.28 0.15 × 0.23
[12] 0.13 1–10 0 3–8 ±5 100 −7 (2 GHz) 11.3–15 (SSB) 1.2 8.4 0.7 × 0.4
[7] 0.25 0.9–10.6 N/A 7.6–9.6 ±2 100 −4 13.1–13.8 1.8 18.3 1.16 × 1.15
[21] SiGe 0.35 5.7 −3 7 Narrow band 35 −18 N/A 2.5 3.875 N/A
[11]a SiGe 0.35 3–11 N/A 11 N/A N/A N/A 5 (DSB) 2.5 15 N/A
This work SiGe 0.18 3–11 0 9.8–10.6 ±0.8 264 −8 (7.2 GHz) 12.2–14.1 (DSB) 1 4.3 0.84 × 0.85
a Simulation
 Circuits Syst Signal Process

the current ILO of the switched series-parallel mixer is two times higher than the series
switched mixer. The wideband input matching networks are applied to achieve a wide
operating frequency for UWB system applications. However, the linearity of Ref. [5] is
poor. In order to improve the linearity, in Ref. [6] multiple-gated-transistors (MGTR)
topology is added. The [5,6] mixers cannot achieve the specification gain flatness
±3 dB for 3.1–10.6 GHz frequency band when the supply voltage is below 1 V. The gain
is attenuated due to the transconductance stage which uses MOS element operating at
high frequencies. The [7,12] (GmSw) mixers cannot achieve the specification when
the supply voltage is below 1 V. The [14,16,17,19] mixers can achieve low power
consumption, but [14,16] require a large power LO signal. Reference [12,19] gain
flatness cannot achieve the specification ±3 dB. Reference [17] frequency band is
5 GHz. The chip area of the [14,17,19] mixers is very small because RF and LO port
have no matching network. RF circuit impedance matching is very important so that
we do not dissipate any power in the network and deliver all the available power to
the load. The [11,21] (GmSw) SiGe mixers cannot achieve the specification when the
supply voltage is below 1 V. The linearity of Ref. [21] is poor. Moreover, compared
with previously published literature, the proposed mixer consumed a relatively low
dc power of 4.3 mW under the supply voltage of 1 V. The current output buffer is
about 3.7 mW. The proposed SiGe BiCMOS mixer using double-balanced switched
series-parallel transconductor techniques has a wide bandwidth, high gain, very good
gain flatness ±0.8 dB.

5 Conclusion

The paper presents a novel SiGe BiCMOS HBT Gilbert-cell (SwGm) UWB mixer
topology, which can operate at 1-V supply voltage. The design of the on transconduc-
tance stage is based on BJT (HBT) transistors to improve the conversion gain. The
design of the on switching stage is based on CMOS switched series-parallel to reduce
the supply voltage and dc power consumption. The proposed mixer design based on
the modified Gilbert-cell topology for wide-band operation has been described. The
main advantage of the mixer topology contains a wide bandwidth, high gain, very
good gain flatness, low NF, low voltage, and low power.

Acknowledgments The authors thank National Science council (NSC) for its financial support (NSC 99-
2221-E-507-005), National Applied Research Laboratories National Chip Implementation Center (CIC)
for its technical support, and National Nano Device Laboratory for its supporting measurement. Taiwan,
ROC.

References
1. A. Amirabadi et al., High IIP3 and low-noise CMOS mixer using non-linear feedback technique.
Circuits Syst. Signal Process. 30, 721–739 (2011)
2. M. Cen et al., Low-power low-noise amplifier for ultra-wideband wireless systems. Circuits Syst.
Signal Process. 33, 3251–3262 (2014)
3. J.D. Chen et al., A 2-GHz low-power down-conversion mixer in 0.18-μm CMOS technology. IEICE
Trans. Electron. 91(c), 64–71 (2008)
Circuits Syst Signal Process

4. J.D. Chen et al., A 5.25-GHz low-power down-conversion mixer in 0.18-μm CMOS technology. J.
Analog Integr. Circuits Signal Process. 62(3), 301–312 (2010)
5. J.D. Chen, A low-voltage ultra-wideband down-conversion mixer with improved power conversion
gain. Int. J. Electron. 98(8), 1055–1073 (2011)
6. J.D. Chen, A. Low-Voltage, High-linearity ultra-wideband down-conversion mixer in 0.18-μm CMOS
technology. Microelectron. J. 42(1), 113–126 (2011)
7. I.Y. Chin et al., 0.9–10.6 GHz UWB mixer using current bleeding for multi-band application. Electron.
Lett. 50(3), 186–187 (2014)
8. H. Darabi, A.A. Abidi, Noise in RF-CMOS mixer: a simple physical model. IEEE J. Solid State Circuits
35(1), 15–25 (2000)
9. K.L. Fong, R.G. Meyer, Monolithic RF active mixer design. IEEE Trans. Circuits Syst. II Analog Digit.
Signal Process. 46(3), 231–239 (1999)
10. R. Harjani, et al., Analog/RF physical layer Issues for UWB systems, in Proceedings of 17th Interna-
tional Conference on VLSI Design (2004), pp. 941–948
11. E. Heves, et al., Design and implementation of SiGe-BiCMOS mixer for UWB applications, in Proceed-
ings of 14th International Conference on IEEE Signal Processing and Communications Applications
(2006), pp. 1–4
12. Z. Hu, M. Koe, A 1- to 10-GHz RF and wideband IF cross-coupled gilbert mixer in 0.13-μm CMOS.
IEEE Trans. Circuits Syst. II Express Br. 60(11), 726–730 (2013)
13. T.K. Johansen et al., Analysis and design of wide-band SiGe HBT active mixers. IEEE Trans. Microw.
Theory Tech. 53(7), 2389–2396 (2005)
14. M.G. Kim et al., Low-voltage, low-power, and low-noise UWB mixer using bulk-injection and switched
biasing techniques. IEEE Trans. Microw. Theory Tech. 60(8), 2486–2493 (2012)
15. E.A.M. Klumperink et al., A CMOS switched transconductor mixer. IEEE J. Solid State Circuits 39(8),
1231–1240 (2004)
16. K.H. Liang et al., A 0.5–7.5 GHz ultra low-voltage low-power mixer using bulk-Injection method by
0.18-μm CMOS technology. IEEE Microw. Wirel. Compon. Lett. 17(7), 531–533 (2007)
17. K.H. Liang, H.Y. Chang, 0.5–6 GHz low-voltage low-power mixer using a modified cascode topology
in 0.18-μm CMOS technology. IET Microw. Antennas Propag. 5(2), 167–174 (2011)
18. C.C. Meng, et al., A high isolation CMFB downconversion micromixer using 0.18-μm deep n-well
CMOS technology, in Proceedings of the IEEE Radio Frequency Integrated Circuits (RFIC) (2003),
pp. 619–622
19. J.B. Seo et al., A low-power and high gain mixer for UWB systems. IEEE Microw. Wirel. Compon.
Lett. 18(12), 803–805 (2008)
20. B. Shi et al., Design of a noise-canceling CMOS wideband receiver front-end with inherent active
balun. Circuits Syst. Signal Process. 38, 123–129 (2010)
21. J.S. Syu, C. Meng, 5.7 GHz Gilbert I/Q downconverter integrated with a passive LO quadrature
generator and an RF Marchand balun. IEEE Microw. Wirel. Compon. Lett. 18(2), 660–669 (2008)
22. C.C. Tang et al., A 2.4 GHz low voltage CMOS down conversion double-balanced mixer. IEICE Trans.
Electron. e84(c), 1084–1091 (2001)
23. X. Wang et al., A 3–10 GHz ultra wideband receiver LNA in 0.13 μm CMOS. Circuits Syst Signal
Process. 33, 1669–1687 (2014)
24. N.H.E. Weste, D. Harris, CMOS VLSI Design, 3rd edn. (Addison Wesley, Reading, 2005)
25. H. Zheng et al., A 3.1 GHz–8.0 GHz single-chip transceiver for MB-OFDM UWB in 0.18-μm CMOS
process. IEEE J. Solid State Circuits 44(2), 414–426 (2009)