40th May 2013 Why won't a PMOS pass a zero and a NMOS pass a one? This took me some time to first wrap my head around. To best understand it | looked at the problem using a simple CMOS inverter. Aydd -| Teer vy [nttp:/2.bp.blogspot.com/-xw1 TX1ty3hQ/UY yiGe4lHUUAAAAAAAABQB/- BFaNb63md0/s 1600/inverter.PNG] ‘When the voltage applied to the gate of the PMOS transistor is 0 it will fill C Load to Vdd (1) and when the NMOS gate voltage is 1 it will discharge C Load. Now the output of the inverter will be signal ground (0). Its a simple CMOS inverter, we all know it and love it. But why is it that a PMOS can pass a 1 but cannot pass a 0, and why can't an NMOS pass a 1 but can pass a 0. First imagine that we swapped the PMOS and NMOS transistors in the above inverter. Lets take a look at how the NMOS transistor might be situated nes Mesd3 ao On Phs PVE tine Vgs> deb Sat WONG VE ‘i [http://3.bp.blogspot. com/- dkWmOdpPcnQ/UY ybtybyF2VAAAAAAAABqQ/41HUQwRSjfw!s 1600/nmos1.PNG] Like the PMOS in the inverter the NMOS has Vdd to pass and charge C Load. The NMOS transistor will be ‘on’ when its gate voltage is greater or equal to the threshold voltage. When the gate voltage is first applied the NMOS. transistor will happily begin to pass Vdd to the capacitor and the capacitor voltage will begin to rise.Ags z\g-Vs = Sv-430: 0.90 Vas =Vt oFF {http:1/3.bp.blogspot.com/-30dbXyc6KRe/UYycY hu3_X/AAAAAAAABqY /paSl twbzM00/s 1600/nmos2, PNG] Eventually the load voltage will rise to a point that'll become of interest. if we take the threshold voltage to be equal to 0.7V we can see that when C Load reaches 4.3V that Vgs becomes equal to the threshold voltage and then our NMOS device should go into cutoff. You can see here that an NMOS device is unable to pass Vdd, it'll always pass. Vdd-Vt Now imagine that the PMOS transistor has been inserted into the space where the NMOS transistor was in our CMOS inverter. The NMOS transistor had one job, to discharge Vdd in C Load to ground (passing a 0). We'll see that a PMOS cannot do this just as an NMOS couldn't pass a 1 ow 24 ou hen gs VE Sap. {http://3.bp. blogspot. comi-1VLnt5eMoW VUY ydLIMDbiAAAAAAAAB gk/beAUuO4PrZEw's 1600/pmos1.PNG] As before, a 0 is applied to the gate of our PMOS transistor and since Vgs < Vt it will conduct, (Vt is negative for PMOS transistors.)Ve is negative (tt pm! ) ofr Vgsave. Fmos 15 oe [nttp:/2.bp.blogspot.com/- SRIANnAUW/UYyd6BGcool/AAAAAAAABQs/KbPCGgaHXIO/s 1600/pmos2. PNG] Eventually the voltage will keep dropping until it reaches 0.7V. At this time we'lnotice that Vgs = Vt and our PMOS transistor will turn off leaving 0.7V on our inverter output. This is why a PMOS transistor is cannot pass a 1 know this is all crude but hopefully itl point you in the right direction. tm not exactly sure on some of these equations (Maybe it's Vgs = Vt not Vgs => Vt) but the main concept is stands. PMOS transistors will pass a 1 but will not pass a 0, and NMOS transistors will pass a 0 but will not pass a 1 Posted 10th May 2013 by Eggot EBD View comments a Unknown July 21, 2016 at 5:13 AM Tank you s0 much... one o the best answer. Reply bd Vinay Pillay September 4, 2016 at 7:45 AM ‘Thank You! Simple and intuitive way of explaining. it helped a lot. Reply ‘Amaljith MK September 12, 2016 at 12:01 AM very good explanation. thanku very much. Reply Kranthi Kiran January 20, 2017 at 7:39 AM ‘There is small correction needed. in the last sentence of the last but one para, P-MOS cannot pass 0 (Not 1). Please check it. Reply Unknown October 17, 2017 at 7:20 AMThanks a lot. Reply Sergio Lemos February 3, 2018 al 9:05 AM Nice explanation! | would add that CMOS inverter uses common-source output configuration (amplifier) for both pMOS and nMOS, rail-to-rail output swing from the Drain terminal (VDD logic 1 or GRO logic 0), [Vgs|=IVal, [Vdsl=0V When exchanging one with the other, the configuration become a push-pull output configuration (Follower) where the ‘output is always less than source voltage by the threshold voltage. Reply EY May 6, 2018 at 10:41 PM Thanks for good post Reply Kuldeep Tayade June 25, 2018 at 10:00 PM best answer Reply subhajit July 26, 2018 at 9:56 AM Very good explanation thanks a lot Reply Unknown August 5, 2018 at 7:59 AM Thanks alot O 8B 8 0 Reply Enter your conment. Q connotes sgensetagn + sun = -.. neti me