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ADC: Successive Approximation Register Type

Block diagram of SAR ADC

A successive approximation ADC is a type of analog-to-digital converter that converts a continuous analog
waveform into a discrete digital representation via a binary search through all possible quantization levels
before finally converging upon a digital output for each conversion. It typically consists of four chief sub-
circuits:
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SAR-ADC: Algorithm / Working Principle

(i) A sample and hold circuit to acquire the input voltage (Vin).

(ii) An analog voltage comparator that compares Vin to the output of the internal DAC and outputs the
result of the comparison to the successive approximation register (SAR).

(iii) A successive approximation register sub-circuit designed to supply an approximate digital code of Vin
to the internal DAC.

(iv) An internal reference DAC that, for comparison with VREF, supplies the comparator with an analog
voltage equal to the digital code output of the SARin.

The successive approximation register is initialized so that the most significant bit (MSB) is equal to a
P
digital 1. This code is fed into the DAC, which then supplies the analog equivalent of this digital code
(Vref/2) into the comparator circuit for comparison with the sampled input voltage. If this analog voltage
exceeds Vin the comparator causes the SAR to reset this bit; otherwise, the bit is left as 1. Then the next
bit is set to 1 and the same test is done, continuing this binary search until every bit in the SAR has been
tested. The resulting code is the digital approximation of the sampled input voltage and is finally output by
the SAR at the end of the conversion (EOC).
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Shanon’s Sampling Theorem / Nyquist Sampling Frequency
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