8086 Microprocessor

Introduction
• 8086 is an enhanced version of 8085 that has
been developed by Intel in 1978.
• It is a 16 bit Microprocessor. It has a powerful
instruction set and it is capable to providing
multiplication and division operations directly.
It has 20 address lines and 16 data lines. So it
can access up to 1 MB of memory.
• It supports two modes of operation: first is
maximum mode and second is minimum
mode. Minimum mode is applicable for system
that has a single processor and maximum
mode is used for the multiprocessor system.
 Features of 8086
• 8086 has a 20 bit address bus can access up to
2²° memory locations ( 1 MB) .
• It can support up to 64K I/O ports.
• It has fourteen 16-bit registers.
• It has multiplexed address and data bus ADₒ-
AD₁₅ and A₁₆ – A₁₉
• 8086 is a 40 pin IC.
• Various versions of 8086 are operated on 5, 8,
10 MHz clock rates.
 Architecture of 8086
• The 8086 CPU is divided into two independent
functional units:
• Bus Interface Unit (BIU)
• Execution Unit (EU)
• The major reason for this separation is to
increase the processing speed of the
processor
• The BIU has to interact with memory and
input and output devices in fetching the
instructions and data required by the EU
• EU is responsible for executing the
instructions of the programs and to carry out
the required processing
 Execution Unit
• The Execution Unit (EU) has
– Control unit
– Instruction decoder
– Arithmetic and Logical Unit (ALU)
– General purpose registers
– Flag register
– Pointers
– Index registers
 BIU
• The BIU consists of
– Instruction queue
– Four 16 bit Segment Registers(CS, DS, SS, ES)
– Instruction pointer and address summation
 Segment Registers
•8086’s 1MB memory is divided into
segments of up to 64K bytes each.
•The 8086 can directly address four segments
at a particular time.
 Code Segment Register

• 16-bit
• CS contains the base or start of the current code
segment; IP contains the distance or offset from
this address to the next instruction byte to be
fetched.
• BIU computes the 20-bit physical address by
logically shifting the contents of CS 4-bits to the
left and then adding the 16-bit contents of IP.
• That is, all instructions of a program are relative
to the contents of the CS register multiplied by 16
and then offset is added provided by the IP.
 Data Segment Register
• 16-bit

• Points to the current data segment; operands for

most instructions are fetched from this segment.

• The 16-bit contents of the Source Index (SI) or

Destination Index (DI) or a 16-bit displacement
are used as offset for computing the 20-bit
physical address.
 Stack Segment Register
• 16-bit
• Points to the current stack.
• The 20-bit physical stack address is calculated
from the Stack Segment (SS) and the Stack
Pointer (SP) for stack instructions such as PUSH
and POP.
• In based addressing mode, the 20-bit physical
stack address is calculated from the Stack
segment (SS) and the Base Pointer (BP).
 Extra Segment Register
• 16-bit
• Points to the extra segment in which data (in
excess of 64K pointed to by the DS) is stored.
• String instructions use the ES and DI to
determine the 20-bit physical address for the
destination.
EU Registers
 Summary of architecture
• 8086 registers categorized into 4 groups
 Data Registers: AX, BX, CX, DX
• Instructions execute faster if the data is in a register
• AX, BX, CX, DX are the data registers
• Low and High bytes of the data registers can be accessed
separately
– AH, BH, CH, DH are the high bytes
– AL, BL, CL, and DL are the low bytes
• Data Registers are general purpose registers but they also
perform special functions
• AX
– Accumulator Register
– Preferred register to use in arithmetic, logic and data transfer
instructions because it generates the shortest Machine Language Code
– Must be used in multiplication and division operations
– Must also be used in I/O operations
• BX
– Base Register
– Also serves as an address register
– Used in array operations
– Used in Table Lookup operations (XLAT)
• CX
– Count register
– Used as a loop counter
– Used in shift and rotate operations
• DX
– Data register
– Used in multiplication and division
– Also used in I/O operations
 Pointer and Index Registers
• Contain the offset addresses of memory locations
• Can also be used in arithmetic and other operations
• SP: Stack pointer
– Used with SS to access the stack segment
• BP: Base Pointer
– Primarily used to access data on the stack
– Can be used to access data in other segments
• SI: Source Index register
– is required for some string operations
– When string operations are performed, the SI register points to memory
locations in the data segment which is addressed by the DS register.
Thus, SI is associated with the DS in string operations.
• DI: Destination Index register
– is also required for some string operations.
– When string operations are performed, the DI register points to memory
locations in the data segment which is addressed by the ES register.
Thus, DI is associated with the ES in string operations.
• The SI and the DI registers may also be used to access data
stored in arrays
 Segment Registers - CS, DS, SS and
ES
• Are Address registers
• Store the memory addresses of instructions and
data
Memory Organization of 8086 Microprocessors
 Memory Organization
• Each byte in memory has a 20 bit address starting
with 0 to 220-1 or 1 meg of addressable memory
• Addresses are expressed as 5 hex digits from
00000 - FFFFF
• Problem: But 20 bit addresses are TOO BIG to fit
in 16 bit registers!
• Solution: Memory Segment
• At each address we can store 8 bit address (1-
byte)but if want to write a word(16-bit)into a
memory segment to store data in byte form
then we write the data in two consecutive
memory address which are even(low) and
odd(high) memory.
• The 8086 memory address space can be
viewed as a sequence of one million bytes in
which any byte may contain an 8 bit data
element and any two consecutive bytes may
contain a 16 bit data element.
• The address space is physically connected to a
16 -bit data bus by dividing the address space
into two 8 bit banks of up to 512K bytes each.
• One bank is connected to the lower half of the
16 bit data bus (D0-D7 ) and contains even
address bytes.
• When A0 is high and BHE (Bus High Enable) is
low, the odd bank is selected.

• A specific byte within each bank is selected by

address lines A1-A19
• Data can be accessed from the memory in
four different ways.
– 8 -bit data from Lower (Even) address Bank.
– 8-bit data from Higher (Odd) address Bank.
– 16-bit data starting from Even Address.
– 16-bit data starting from Odd Address
Logical and Physical address of 8086
Microprocessors
 8086 Physical Memory
– The total memory (1MB) of 8086 is arranged in two
banks. An odd bank and an even bank. Both the banks
have equal no. of locations.

– The odd bank contains odd numbered memory

Locations. It is known as upper bank.

– The even bank contains only even numbered memory.

Locations. It is known as lower bank.

– This arrangement is done in order to speed up the

operation
– Every memory location has two kinds of address –
physical and logical.

– A physical address is the 20-bit value that uniquely

identifies each byte location in the Mega byte memory
space.

– These may range from 0 to FFFFF Hex.

– All exchanges between the CPU and memory

components use this physical address
• Programs deal with logical, rather than physical,
addresses.
• A logical address consists of a segment base value and
an offset value.
• For any given memory location, the segment base
value locates the first byte of the containing segment
and the offset value is the distance, in bytes, of the
target location from the beginning of the segment.
• Segment base and offset values are unsigned 16-bit
quantities; the lowest-addressed byte in a segment has
an offset of 0.Whenever memory is accessed, a
physical address is generated from a logical address.
• Block of 64K (65,536) consecutive memory bytes
• A segment number is a 16 bit number
• Segment numbers range from 0000 to FFFF
• Within a segment, a particular memory location is
specified with an offset
• An offset also ranges from 0000 to FFFF
Example
 Segment registers and default offset
register in 8086
Segment registers default offset register
CS IP
DS BX, SI, DI, 8 or 16 bit disp.
SS SP and BP
ES DI for string operation
 Example
• If the CS register has value 3000H and IP has
the value 2000H, Physical address (memory
address from where next instruction is taken)
is computed as:
CS×10H=30000H (Base address of code segment)
+ IP = 2000H (offset address)
_______
32000H (Physical address )
 Example
• If the DS register has value 1000H and BX has
the value 3000H, Physical address (memory
address from where next instruction is taken)
is computed as:
DS×10H=10000H (Base address of data segment)
+ BX = 3000H (offset address)
___________
13000H (Physical address )
ADDRESSING MODES
 Addressing Modes
• Every instruction of a program has to
operate on a data.
• The different ways in which a source
operand is denoted in an instruction
are known as addressing modes.
 Addressing Modes of 8086
1. Register Addressing Addressing modes for register and
immediate data
2. Immediate Addressing
3. Direct Addressing
Addressing modes for memory data
4. Register Indirect Addressing
5. Based Addressing
6. Indexed Addressing
7. Based Index Addressing
8. String Addressing
9. Direct I/O port Addressing
Addressing modes for I/O
10. Indirect I/O port Addressing ports
11. Relative Addressing
12. Implied Addressing
 Register Addressing
• Transfers a copy of a byte or word from the
source register or memory location to the
destination register or memory location.
• Use of registers to hold the data to be
manipulated
• Memory is not accessed when this addressing
mode is executed
• Example:
MOV BX, DX ; copy the contents of DX into BX
MOV ES, AX ; copy the contents of AX into ES
ADD AL, BH ; add the contents of BH to contents
of AL

Source and destination registers must have the

same size
 Immediate Addressing
• Transfers the source, an immediate byte or word
of data, into the destination register or memory
location
• The source operand is a constant . The operand
comes immediately after the opcode
• For this reason, this addressing mode executes
quickly
• Immediate addressing mode can be used to load
information into any of the registers except the
segment registers and flag registers.
• Example:
MOV AX, 2550H ; move 2550H into AX
MOV CX, 625 ; load the decimal value 625 into
CX
MOV BL, 40H ; load 40H into BL
• The data must first be moved to a general-
purpose register and then to the segment
register.
• Example:
MOV AX, 2550H
MOV DS, AX
MOV DS, 0123H ; illegal instruction
Examples of Immediate addressing
mode
 Addressing Modes : Memory Access
• Memory Address represented in the form –
Seg : Offset (Eg - 89AB:F012)

• Each time the processor wants to access

memory, it takes the contents of a segment
register, shifts it one hexadecimal place to the
left (same as multiplying by 1610), then add the
required offset to form the 20- bit address
• To access memory we use these four
registers: BX, SI, DI, BP
• Combining these registers inside [ ] symbols,
we can get different memory locations
(Effective Address, EA)
Supported combinations:
 Direct Addressing
• Moves a byte or word between a memory
location and a register.
• The data is in some memory location(s) and
the address of the data in memory comes
immediately after the instruction.This address
is the offset address
• Example:
MOV AX, [2400] ; move contents of DS:2400H
into AX

The physical address is calculated by combining

the contents of offset location 2400 with DS
• Example:

MOV BX, [2000H]

MOV BL, [0400H]

• The square brackets around the 2000H denotes

the contents of the memory location. When
executed, this instruction will copy the contents
of the memory location into BX register.

• This addressing mode is called direct because the

displacement of the operand from the segment
base is specified directly in the instruction.
• Example:
• Find the physical address of the memory
location and its contents after the execution
of the following, assuming that DS = 1512H.
MOV AL, 3BH
MOV [3518], AL
• First 3BH is copied into AL
• Then in line 2, the contents of AL are moved
to logical address DS:3518 which is 1512:3518.
• Shifting DS left and adding it to the offset
gives the physical address of 18638H (15120H
+ 3518H = 18638H).
• After the execution of the second instruction,
the memory location with address 18638H will
contain the value 3BH.
Examples of Direct Addressing
Register Indirect Addressing
• Transfers a byte or word between a register
and a memory location addressed by an index
or base register
• The address of the memory location where
the operand resides is held by a register
• The registers used for this purpose are SI, DI,
and BX
• They must be combined with DS in order to
generate the 20-bit physical address.
• Example:

• MOV CX, [BX]

EA = (BX)
BA = (DS) x 10
MA = BA + EA
Suppose [BX]=2000H, [DS]=3000H.
MA= 30000+2000=32000H
A word from memory address 32000H is read and stored in CX. Out
of which higher order byte is stored in CH and low order byte is stored in
CL
• Example:
MOV CL, [SI] ; move contents of DS:SI into CL

MOV [DI], AH ; move contents of AH into DS:DI

• Example:
Assume that DS = 1120, SI = 2498, and AX =
17FE. Show the contents of memory locations
after the execution of instruction
MOV [SI], AX ; move contents of AX into DS:SI
• The physical address starts at DS (shifted left)
+ SI = 13698.
• Low address 13698H contains FE, the low byte
• High address 13699H will contain 17, the high
byte.
Examples of Register Indirect
Addressing Mode
 Base Addressing
• In Based Addressing, an 8 bit or 16 bit
displacement is added to the content of a base
register (BX or BP) specified in the instruction.

• In case of 8-bit displacement, it is sign

extended to 16-bit before adding to the base
value.

• When BX holds the base value of EA, 20-bit

physical address is calculated from BX and DS.

• When BP holds the base value of EA, BP and SS

is used.
• Example:

MOV AX, [BX + 08H]

Operations:

0008H  08H (Sign extended)

EA = (BX) + 0008H
BA = (DS) x 10
MA = BA + EA
Suppose [BX]=2000H, [DS]=3000H.
MA= 30000+2000+0008=32008H
A byte from memory address 32008H is red and
stored in AX
(AX)  (MA) or,

(AL)  (MA)
(AH)  (MA + 1)
• Suppose [BX]=2000H, [DS]=3000H.

1. MOV AX, [BX+5]

2. MOV AL, [BX+15]
MA=30000+2000+000F (equivalent to decimal 15)
=3200F
 Indexed Addressing

• Similar to base addressing except

displacement is added to the index
value in SI or DI register to obtain
the EA.

• The data is taken from data segment

• Example:

MOV BL, [SI]

Suppose [SI]=1000H
Operations:

EA = [SI]
BA = (DS) x 10
MA = BA + EA= 30000+1000=31000H
A byte from memory address 32000H is read and
stored in BL
• MOV CL, [DI+10H]
Suppose [DI]=3000H
EA= [DI+10H]
MA= 30000H+3000H+10H=33010H
 Based Index Addressing
• In Based Index Addressing, the effective
address is computed from the sum of a
base register (BX or BP), an index register
(SI or DI)
• Combining based and indexed addressing modes.
• Examples:
MOV [BX+DI], CL ; move contents of CL into
DS:BX+DI
Physical Address = DSx10 + BX+DI
• MOV CH, [BX+SI] ; move contents of the
DS:BX+SI into CH
Physical Address = DSx10 + BX+SI
• MOV AH, [BP+DI] ; move contents of the
SS:BP+SI into AH
Physical Address = SSx10 + BP+DI
• Example:

MOV AX, [BX + SI ]

Operations:

EA= [BX] + [SI ]

MA=DS×10+ [BX] + [SI ]
=30000+2000+1000=33000H
A word from memory address 33000H is
taken and stored in AX
Examples of Based Index
Addressing
 Based Index with displacement
addressing mode
• Here, the effective address is computed from
the sum of a base register (BX or BP), an index
register (SI or DI) and displacement specified
by the instruction
• MOV CX, [BX+SI+50H]
EA= [BX]+[SI]+50H
MA= DS×10+EA
=30000H+2000H+1000H+50H
=33050H
A word from memory address 33050H
is read and stored in CX
Register Relative Addressing Mode
• Moves a byte or word between a register and
the memory location addressed by an index or
base register plus a displacement.
• The data in a segment of memory are
addressed by adding the displacement to the
contents of a base or an index register (BP, BX,
DI, or SI).
• Examples:
• MOV AX, [BX+4] ; move contents of DS:BX+4 into
AX Physical Address = DSx10 + BX+4
• MOV CH, [SI+5] ; move contents of the DS:SI+5
into CH Physical Address = DSx10 +SI+5
• MOV AH, [DI+1] ; move contents of the DS:DI+1
into AH Physical Address = DSx10 + DI+1
• MOV [BP+2], AL ; move contents of AL into
SS:BP+2 Physical Address = SSx10 + BP+2
• Example:
Assume that DS = 4500, SS = 2000, BX = 2100, SI =
1486, DI = 8500, BP= 7814, and AX = 2512. Show
the exact physical memory location where AX is
stored in each of the following. All values are in hex.
1- MOV [BX+20], AX
2- MOV [SI+10], AX
3- MOV [DI+4], AX
4- MOV [BP+12], AX
• Solution:
Physical Address = segment reg. x 10 + (offset reg.) +
displacement
1- DS:BX+20 location 47120 = (12) and 47121 =
(25)
2- DS:SI+10 location 46496 = (12) and 46497 =
(25 )
3- DS:DI+4 location 4D504 = (12) and 4D505
= (25)
4- SS:BP+12 location 27826 = (12) and 27827 =
(25)
 Implied Addressing
• Instructions using this mode have no
operands. The instruction itself will
specify the data to be operated by
the instruction.

• Example: CLC
This clears the carry flag to zero.
8086 INSTRUCTION SET
 Types of Instructions
• Data Transfer
• Arithmetic
• Logical
• String
• Rotate and Shift
• Control Transfer
 Data Transfer
• These instructions are used to transfer data
from source to destination.
• The operand can be a constant, memory
location, register or I/O port address.
 Data Transfer
• MOV Des, Src:
• Src operand can be register, memory location
or immediate operand.
• Des can be register or memory operand.
• Both Src and Des cannot be memory location
at the same time.
• MOV instruction does not affect any flag.
• XCHG : XCHG Destination, Source
• The XCHG instruction exchanges the content of a
register with the content of another register or with
the content of memory location(s).
• It cannot directly exchange the content of two memory
locations.
• The source and destination must both be of the same
type (bytes or words).
• The segment registers cannot be used in this
instruction.
• This instruction does not affect any flag.
• LEA – LEA Register, Source
• This instruction determines the offset of the
variable or memory location named as the
source and puts this offset in the indicated 16-
bit register.
• LEA does not affect any flag.
• LEA BX, [DI] This instruction loads the contents
of DI (offset) into the BX register.
• LDS Des, Src
• It loads 32-bit pointer from memory source to
destination register and DS.
• The word from two memory locations is
copied into the specified register and the
word from the next two memory locations is
copied into the DS registers.
• LDS does not affect any flag
• LES Des, Src:
• It loads 32-bit pointer from memory source to
destination register and ES.
• E.g.: LES BX, [0301 H]
• LAHF: It copies the lower byte of flag register
to AH.
• SAHF: It copies the contents of AH to lower
byte of flag register.
• PUSHF: Pushes flag register to top of stack.
• POPF: Pops the stack top to flag register
 Arithmetic Instructions
ADD – ADD Destination, Source
ADC – ADC Destination, Source
• These instructions add a number from some
source to a number in some destination and put
the result in the specified destination.
• The source may be an immediate number, a
register, or a memory location. The destination
may be a register or a memory location. The
source and the destination in an instruction
cannot both be memory locations.
• It effects AF, CF, OF, PF, SF, ZF flags.
SUB – SUB Destination, Source
SBB – SBB Destination, Source
• These instructions subtract the number in
some source from the number in some
destination and put the result in the
destination.
• The SBB instruction also subtracts the content
of carry flag from the destination.
• Flags affected: AF, CF, OF, PF, SF, ZF.
• MUL – MUL Source
• This instruction multiplies an unsigned byte in
some source with an unsigned byte in AL
register or an unsigned word in some source
with an unsigned word in AX register
• The source can be a register or a memory
location.
• When a byte is multiplied by the content of
AL, the result (product) is put in AX.
• When a word is multiplied by the content of
AX, the result is put in DX and AX registers.
• If the most significant byte of a 16-bit result or
the most significant word of a 32-bit result is
0, CF and OF will both be 0’s.
• If you want to multiply a byte with a word,
you must first move the byte to a word
location such as an extended register and fill
the upper byte of the word with all 0’s.
• IMUL – IMUL Source
• This instruction multiplies a signed byte from
source with a signed byte in AL or a signed
word from some source with a signed word in
AX. The source can be a register or a memory
location
• When a byte from source is multiplied with
content of AL, the signed result (product) will
be put in AX.
• When a word from source is multiplied by AX,
the result is put in DX and AX.
• If the upper byte of a 16-bit result or the
upper word of a 32-bit result contains only
copies of the sign bit (all 0’s or all 1’s), then CF
and the OF will both be 0
• If it contains a part of the product, CF and OF
will both be 1.
• AF, PF, SF and ZF are undefined after IMUL.
• To multiply a signed byte with a signed word,
first move the byte into a word location and
fill the upper byte of the word with copies of
the sign bit.
• If you move the byte into AL, you can use the
CBW instruction to do this.
• DIV – DIV Source
• This instruction is used to divide an unsigned
word by a byte or to divide an unsigned
double word (32 bits) by a word.
• When a word is divided by a byte, the word
must be in the AX register. The divisor can be
in a register or a memory location
• After the division, AL will contain the 8-bit
quotient, and AH will contain the 8-bit remainder.
• When a double word is divided by a word, the
most significant word of the double word must
be in DX, and the least significant word of the
double word must be in AX.
• After the division, AX will contain the 16-bit
quotient and DX will contain the 16-bit
remainder.
• IDIV – IDIV Source
• This instruction is used to divide a signed word
by a signed byte, or to divide a signed double
word by a signed word.
• When dividing a signed word by a signed byte,
the word must be in the AX register.
• The divisor can be in an 8-bit register or a
memory location.
• After the division, AL will contain the signed
quotient, and AH will contain the signed
remainder.
• The sign of the remainder will be the same as the
sign of the dividend.
• All flags are undefined after an IDIV
• INC – INC Destination
• It adds 1 to a specified register or to a
memory location. AF, OF, PF, SF, and ZF are
updated, but CF is not affected
• DEC – DEC Destination
• This instruction subtracts 1 from the
destination word or byte.
• The destination can be a register or a memory
location.
• AF, OF, SF, PF, and ZF are updated, but CF is
not affected
• DAA (DECIMAL ADJUST AFTER BCD ADDITION)
• This instruction is used to make sure the result of
adding two packed BCD numbers is adjusted to be a
legal BCD number.
• The result of the addition must be in AL for DAA to
work correctly.
• If the lower nibble in AL after an addition is greater
than 9 or AF was set by the addition, then the DAA
instruction will add 6 to the lower nibble in AL. If the
result in the upper nibble of AL in now greater than 9
or if the carry flag was set by the addition or correction
• The DAA instruction updates AF, CF, SF, PF, and
ZF; but OF is undefined.
• CBW (CONVERT SIGNED BYTE TO SIGNED
WORD)
• This instruction copies the sign bit of the byte
in AL to all the bits in AH.
• AH is then said to be the sign extension of AL.
• CBW does not affect any flag.
• AAA (ASCII Adjust after Addition):
• The data entered from the terminal is in ASCII
format
• In ASCII, 0 – 9 are represented by 30H – 39H.
• This instruction allows us to add the ASCII
codes.
• This instruction does not have any operand.
• The AAA instruction works only on the AL
register.
• The AAA instruction updates AF and CF; but
OF, PF, SF and ZF are left undefined.
• Other ASCII Instructions:
• AAS (ASCII Adjust after Subtraction)
• AAM (ASCII Adjust after Multiplication)
• AAD (ASCII Adjust Before Division)
• CMP Des, Src:
• It compares two specified bytes or words.
• The Src and Des can be a constant, register or memory
location.
• Both operands cannot be a memory location at the
same time.
• The comparison is done simply by internally
subtracting the source from destination.
• The value of source and destination does not change,
but the flags are modified to indicate the result.
 Logical Instruction
• AND – AND Destination, Source
• This instruction ANDs each bit in a source byte or
word with the same numbered bit in a
destination byte or word.
• The result is put in the specified destination. The
content of the specified source is not changed.
• CF and OF are both 0 after AND. PF, SF, and ZF are
updated by the AND instruction. AF is undefined.
• OR – OR Destination, Source
• This instruction ORs each bit in a source byte or
word with the same numbered bit in a
destination byte or word.
• The result is put in the specified destination. The
content of the specified source is not changed.
• CF and OF are both 0 after OR. PF, SF, and ZF are
updated by the OR instruction. AF is undefined.
• XOR – XOR Destination, Source
• This instruction Exclusive-ORs each bit in a
source byte or word with the same numbered
bit in a destination byte or word.
• The result is put in the specified destination.
The content of the specified source is not
changed.
• CF and OF are both 0 after XOR. PF, SF, and ZF
are updated.
• NOT – NOT Destination
• The NOT instruction inverts each bit (forms
the 1’s complement) of a byte or word in the
specified destination. The destination can be a
register or a memory location.
• This instruction does not affect any flag.
• NEG – NEG Destination
• This instruction replaces the number in a
destination with its 2’s complement.
• The destination can be a register or a memory
location.
• It gives the same result as the invert each bit
and add one algorithm.
• The NEG instruction updates AF, AF, PF, ZF, and
OF
• CMP – CMP Destination, Source
• This instruction compares a byte / word in the
specified source with a byte / word in the
specified destination.
• The comparison is actually done by subtracting
the source byte or word from the destination
byte or word.
• The source and the destination are not changed,
but the flags are set to indicate the results of the
comparison.
• AF, OF, SF, ZF, PF, and CF are updated by the
CMP instruction. For the instruction CMP CX,
BX, the values of CF, ZF, and SF will be as
follows:
• TEST – TEST Destination, Source
• This instruction ANDs the byte / word in the
specified source with the byte / word in the
specified destination.
• Flags are updated, but neither operand is
changed.
• The test instruction is often used to set flags
before a Conditional jump instruction.
 Rotate and Shift Instructions
• RCL – RCL Destination, Count
• This instruction rotates all the bits in a specified word
or byte some number of bit positions to the left.
• The operation circular because the MSB of the
operand is rotated into the carry flag and the bit in
the carry flag is rotated around into LSB of the
operand.
• RCR – RCR Destination, Count
• This instruction rotates all the bits in a specified word
or byte some number of bit positions to the right.
• The operation circular because the LSB of the
operand is rotated into the carry flag and the bit in
the carry flag is rotate around into MSB of the
operand.
• ROL – ROL Destination, Count
• This instruction rotates all the bits in a
specified word or byte to the left some
number of bit positions.
• The data bit rotated out of MSB is circled back
into the LSB. It is also copied into CF.

• ROL affects only CF and OF

ROL AX, 1 ; Rotate the word in AX 1 bit position
left, MSB to LSB and CF
MOV CL, 04H ; Load number of bits to rotate in CL
ROL BL, CL ; Rotate BL 4 bit positions
• ROR – ROR Destination, Count
It rotates all the bits in a specified word or
byte some number of bit positions to right.
• The operation is desired as a rotate rather
than shift, because the bit moved out of the
LSB is rotated around into the MSB. The data
bit moved out of the LSB is also copied into CF.
ROR BL, 1 ;Rotate all bits in BL right 1 bit position LSB
to MSB and to CF
MOV CL, 08H ;Load CL with number of bit positions to
be rotated
 Control Instruction
• JMP (UNCONDITIONAL JUMP TO SPECIFIED
DESTINATION)
• This instruction will fetch the next instruction
from the location specified in the instruction
• If the destination is in the same code segment as
the JMP instruction, then only the instruction
pointer will be changed to get the destination
location (near jump).
• If the destination for the jump instruction is in
a segment with a name different from that of
the segment containing the JMP instruction,
then both the instruction pointer and the
code segment register content will be changed
to get the destination location (far jump).
• The JMP instruction does not affect any flag
Other control/branch instructions
String Instructions
Processor Control Instructions
 Assembler Directives
• Assembler directives give instruction to the
assembler.
• Assembler directives are specific for a
particular assembler
• However all the popular assemblers like the
Intel 8086 macro assembler, the turbo
assembler and the IBM macro assembler use
common assembler directives
 Data Defining Directives
DB (DEFINE BYTE)
• The DB directive is used to declare a byte-type
variable or to set aside one or more storage
locations of type byte in memory
 DW (DEFINE WORD)
• The DW directive is used to tell the assembler to
define a variable of type word or to reserve
storage locations of type word in memory.
 DD (DEFINE DOUBLE WORD)
• The DD directive is used to declare a variable of
type double word or to reserve memory
locations, which can be accessed as type double
word.
• The statement ARRAY DD 25629261H, for
example, will define a double word named ARRAY
and initialize the double word with the specified
value when the program is loaded into memory
 DQ (DEFINE QUADWORD)
• The DQ directive is used to tell the assembler to
declare a variable 4 words in length or to reserve
4 words of storage in memory.
• The statement
BIG_NUMBER DQ 243598740192A92BH, will
declare a variable named BIG_NUMBER and
initialize the 4 words set aside with the specified
number when the program is loaded into
memory
 DT (DEFINE TEN BYTES)
• The DT directive is used to tell the assembler to
declare a variable, which is 10 bytes in length or
to reserve 10 bytes of storage in memory.
• The statement
PACKED_BCD DT 11223344556677889900
will declare an array named PACKED_BCD, which
is 10 bytes in length.
 Segment defining Directives
SEGMENT
• The SEGMENT directive is used to indicate the
start of a logical segment.
• Preceding the SEGMENT directive is the name
you want to give the segment.
• For example, the statement CODE SEGMENT
indicates to the assembler the start of a logical
segment called CODE
 ENDS (END SEGMENT)
• This directive is used with the name of a
segment to indicate the end of that logical
segment.

CODE SEGMENT ;Start of logical segment

containing code
instruction statements
CODE ENDS ;End of segment named CODE
 END (END PROCEDURE)
• The END directive is put after the last
statement of a program to tell the assembler
that this is the end of the program module.
• The assembler will ignore any statements
after an END directive
 ASSUME
• The ASSUME directive tell the assembler the
name of the logical segment it should use for
a specified segment
• The statement ASSUME DS: DATA
tells the assembler that for any program
instruction, which refers to the data segment,
it should use the logical segment called DATA
 ENDP (END PROCEDURE)
• The directive is used along with the name of the
procedure to indicate the end of a procedure to
the assembler.
• The directive, together with the procedure
directive, PROC, is used to “bracket” a procedure.
 NAME
• The NAME directive is used to give a specific
name to each assembly module when
programs consisting of several modules are
written.
 EQU (EQUATE)
• EQU is used to give a name to some value or
symbol.
• Each time the assembler finds the given name in
the program, it replaces the name with the value
or symbol you equated with that name.
 PUBLIC
• The PUBLIC directive is used to tell the
assembler that a specified name or label will
be accessed from other modules.
• PUBLIC DIVISOR, DIVIDEND, makes the two
variables DIVISOR and DIVIDEND available to
other assembly modules.
 LENGTH

• LENGTH is an operator, which tells the assembler

to determine the number of elements in some
named data item, such as a string or an array.
• When the assembler reads the statement
MOV CX, LENGTH STRING1,
will determine the number of elements in
STRING1 and load it into CX.
 OFFSET
• OFFSET is an operator, which tells the
assembler to determine the offset or
displacement of a named data item (variable),
a procedure from the start of the segment,
which contains it.
• MOV BX, OFFSET PRICES
• ASSUME
• This directive tells the assembler which
segment to be used as an active segment at
any instant.
• The offset of the active segment is calculated
Syntax
ASSUME Seg register : name
• Example
Name SEGMENT
Num1 DW F012H
Num2 DB 0A00H
Name Ends
• If ASSUME DS:Name is executed, the assembler will
consider the segment Name as the data segment.
• If ASSUME ES:Name is executed, the assembler will
consider the segment Name as an extra segment.
Minimum and Maximum mode
Of
8086
 Introduction
• The 8086 has a combined address and data
bus commonly referred as a time multiplexed
address and data bus.
• The main reason behind multiplexing address
and data over the same pins is the maximum
utilization of processor pins and it facilitates
the use of 40 pin standard DIP package
• The bus can be demultiplexed using a few
latches and transreceivers, when ever
required.
•
 Minimum Mode 8086 System
• The microprocessor 8086 is operated in minimum
mode by making its MN/MX pin to logic 1.
• In this mode, all the control signals are given out by the
microprocessor chip itself. There is a single
microprocessor in the minimum mode system.
• Demultiplexing the Buses
– address/data bus: multiplexed(shared) to reduce no
of pins
– memory and I/O : require that address remains
valid and stable throughout a read and write cycle
• The components in the system are
– Three 8 bit latches (IC 8282)
– Two 8bit transreceivers (IC 8286)
– One clock generator(8284)
– Control signal generator
Minimum Mode configuration
• Latches are generally buffered output D-type
flip-flops like 74LS373 or 8282.
• They are used for separating the valid address
from the multiplexed address/data signals and
are controlled by the ALE signal generated by
8086.
• Transreceivers are the bidirectional buffers
and some times they are called as data
amplifiers.
• They are required to separate the valid data
from the time multiplexed address/data
signals.
• They are controlled by two signals namely,
DEN and DT/R.
• The DEN signal indicates the direction of data,
i.e. from or to the processor.
• The system contains memory for the monitor
and users program storage.
• Usually, EPROM are used for monitor storage,
while RAM for users program storage. A
system may contain I/O devices.
• The BHE and A0 signals are used to select the
proper byte or bytes of memory or I/O word
to be read or write.
• The M/IO, RD and WR signals indicate the
type of data transfer
 Bus Timings for Minimum Mode
• The timing diagrams of input and output
transfers for Minimum Mode Configuration of
8086 are shown below.
Input (read operation)
Output (write operation)
 Steps
• When processor is ready to initiate the bus cycle, it
applies a pulse to ALE during T1. Before the falling edge
of ALE, the address, BHE, M/IO, DEN and DT/R must be
stable i.e. DEN = high and DT/R = 0 for input or DT/R = 1
for output.
• At the trailing edge of ALE, ICs 74LS373 or 8282 latches
the address.
• During T2 the address signals are disabled and S3-S7 are
available on AD16/S3-AD19/S6 and BHE/S7. Also DEN is
lowered to enable transceiver.
• In case of input operation, RD is activated during T2 and
AD0 to AD15 go in high impedance preparing for input.
• If memory or I/O interface can perform the
transfer immediately; there are no wait states
and data is output on the bus during T3.
• After the data is accepted by the processor, RD is
raised high at the beginning of T4.
• Upon detecting this transition during T4, the
memory or I/O device will disable its data signals.
• For an output operation, processor applies WR =
0 and then the data on the data bus during T2.
• In T4, WR is raised high and data signals are
disabled.
• For either input or output operation, DEN is
raised during T4 to disable the Also M/IO is set
according to the next transfer at this time or
during next T1 state. Thus length of bus cycle in
8086 is four clock cycle. If the bus is to be inactive
after completion of bus cycle, then the gap
between the successive cycles is filled by ideal
state clock cycles.
 Maximum Mode 8086 System
• In the maximum mode, the 8086 is operated by
strapping the MN/MX pin to ground.
• In this mode, the processor derives the status
signal S2, S1, S0.
• Another chip called bus controller derives the
control signal using this status information .
• In the maximum mode, there may be more than
one microprocessor in the system configuration.
The components in the system are same as in the
minimum mode system.
• The basic function of the bus controller chip IC
8288, is to derive control signals like RD and
WR ( for memory and I/O devices), DEN, DT/R,
ALE etc. using the information by the
processor on the status lines.
 Maximum Mode Configuration For
8086
• Components are:
– Three 8 bit latches (IC 8282)
– Two 8 bit transreceivers (IC 8286)
– One clock generator (IC 8284)
– Bus controller (8288)
Maximum Mode Configuration For
8086
• In the maximum mode additional circuitry is
required to translate the control signals.
• The additional circuitry converts the status
signals (S2-S0) into the I/O and memory
transfer signals.
• It also generates the control signals required
to direct the data flow and for controlling
8282 latches and 8286 transceivers.
• AEN and IOB are generally grounded.
• CEN pin is usually tied to +5V.
• The significance of the MCE/PDEN output
depends upon the status of the IOB pin.
• INTA pin used to issue two interrupt
acknowledge pulses to the interrupt controller
or to an interrupting device.
• IORC, IOWC are I/O read command and I/O write
command signals respectively . These signals
enable an IO interface to read or write the data
from or to the address port.
• The MRDC, MWTC are memory read command
and memory write command signals respectively
and may be used as memory read or write
signals.
• All these command signals instructs the memory
to accept or send data from or to the bus.
 Bus Timings of input operation for
Maximum Mode Configuration of 8086
 Bus Timings of output operation for
Maximum Mode Configuration of 8086
 Steps
• S0,S1,S2 are set at the beginning of bus cycle. On
detecting the change on passive state S0 = S1 =
S2 = 1, the 8288 bus controller will output a pulse
on its ALE and apply a required signal to its DT/R
pin during T1.
• In T2, 8288 will set DEN = 1 thus enabling
transceiver. For an input, 8288 it will activates
MRDC or IORC. These signals are activated
until T4. For an output, the AMWC or AIOWC is
activated from T2 to T4 and MWTC or IOWC is
activated from T3 to T4.
• The status bits S0 to S2 remain active until T3,
and become passive during T3 and T4.
• If ready input is not activated before T3, wait
state will be inserted between T3 and T4.
 8288 Bus Controller
• It generates the control signals required to
direct the data flow and for controlling 8282
latches and 8286 transceivers.
• It also decodes the S2-S0 signals to generate
MRDC, MWTC, IORC, IOWC, MCE/PDEN, AEN,
IOB, CEN, AIOWC, and AMWC signals.
8288 Bus Controller
Bus status codes
• MRDC (Memory Read Command) : It instructs
the memory to put the contents of the addressed
location on the data bus.
• MWTC (Memory Write Command) : It instructs
the memory to accept the data on the data bus
and load the data into the addressed memory
location.
• IORC (I/O Read Command) : It instructs an I/O
device to put the data contained in the addressed
port on the data bus.
• IOWC (I/0 Write Command) : It instructs an I/O
device to accept the data on the data bus and
load the data into the addressed port.
• MCE/PDEN (Master Cascade Enable/Peripheral
Data Enable) : It controls the mode of operation
of 8259. It selects cascade operation for 8259
(interrupt controller) if IOB signal is grounded and
enables the I/O bus transceivers if IOB is tied
high.
• AEN, IOB and CEN : These pins are used in
multiprocessor system.
– With a single processor in the system, AEN and
IOB are grounded and CEN is tied high.
– AEN causes the 8288 to enable the memory
control signals. IOB (I/O bus mode) signal selects
either the I/O bus mode or system bus mode
operation.
– CEN (control enable) input enables the command
output pins on the 8288.
• AIOWC/AMWC (Advance I/O Write
Command/Advance Memory Write
Command) :
– These signals are similar to IOWC and MWTC
except that they are activated one clock pulse
earlier.
– This gives slow interfaces an extra clock cycle to
prepare to input the data.